Characterization and modeling of hot carrier injection in LDMOS for L-band radar application

This paper reports a methodology to correlate Hot Carrier Injection (HCI) degradation mechanism and electrical figures of merit on Lateral-Diffused Metal-Oxide-Semiconductor (LDMOS) transistor. This method is based on RF life test in radar operating conditions coupled to a high drain voltage in order to make visible HCI degradation. We propose drain current modeling vs. time based on a simple extraction procedure. The electron density trapped in the oxide is extracted from hot carrier induced series resistance enhancement model (HISREM - i.e. ΔR_d model). From this methodology, the degradation of RF-LDMOS due to HCI is quantified and could be simulated with EDA.     

Study of hot-carrier effects on power RF LDMOS device reliability

This paper reports comparative reliability of the hot carrier induced electrical performance degradation in power RF LDMOS transistors after RF life-tests and novel methods for accelerated ageing tests under various conditions (electrical and/or thermal stress): thermal shock tests (TST, air–air test) and thermal cycling tests (TCT, air–air test) under various conditions (with and without DC bias, TST cold and hot, different channel current I_DS and different extremes temperatures ΔT values). It is important to understand the effects of the reliability degradation mechanisms on the S-parameters and in turn on static and dynamic parameters. The analysis of the experimental results is presented and the physical processes responsible for the observed degradation at different stress conditions are studied by means of 2D ATLAS-SILVACO simulations. The RF performance degradation of hot-carrier effects power RF LDMOS transistors can be explained by the transconductance and miller capacitance shifts, which are resulted from the interface state generation and trapped electrons, thereafter results in a build up of negative charge at Si/SiO₂ interface.     

Comparative analysis of RF LDMOS capacitance reliability under accelerated ageing tests

This paper presents the results of comparative reliability study of C–V characteristics through three accelerated ageing tests for stress applied to an RF LDMOS: Thermal shock tests (TST, air–air test), thermal cycling tests (TCT, air–air test) and high temperature storage life (HTSL). The two first tests are carried out with a drain current flowing through the device during stress. The investigation findings of electrical parameter degradations after various ageing tests are discussed. Feedback capacitance (Crs) is reduced by 16% and gate–drain capacitance (Cgd) by 42%. This means that the tracking of these parameters enables to consider the hot carrier injection as the dominant degradation phenomenon. A physical simulation software has been used to confirm qualitatively degradation phenomena.     

Comparative analysis of accelerated ageing effects on power RF LDMOS reliability

We present in this paper results of comparative reliability study of three accelerated ageing tests applied on power RF LDMOS: Thermal Shock Tests (TST, air-air test), Thermal Cycling Tests (TCT, air-air test) and High Temperature Storage Life (HTSL). The two first tests are carried out with a drain current flowing through the device during stress. The results obtained show the variation and the Device’s performance quantitative shifts for some macroscopic electric parameters such as threshold voltage (V_th), transconductance (G_m), drain-source current (I_ds), on-state resistance (R_{ds_on}) and feedback capacitance (C_rs) under various ageing tests. To understand the degradation phenomena that appear after ageing, we used a new electro-thermal model implemented in Agilent’s ADS as a reliability tool.     

S波段1OWLDMOS功率管匹配电路设计

RFLDMOSs}／率管具有高输出功率、高增益、高线性、良好的热稳定性等优点,广泛应用于移动通信基站、数字广播电视发射以及射频通信领域、微波雷达系统。阻抗匹配是LDMOS~率管应用电路设计的关键任务,LDMOS功率管匹配电路的主要任务是实现功率管的最大功率传输。文中选择中国电子科技集团公司第58研究所研制的S波段10wLDMOS功率管,利用微波仿真工具ADS设计外匹配电路。经过精心调试后,s波段LDMOSs}／率管输入回波损耗、增益、输出功率、效率、谐波等技术指标达到设计要求。完成匹配电路设计的S波段LDMOS功率管在3．1～3．4GHz频率范围内,输出功率大于13．8W,功率增益大于12．4dB,效率大于37．9％。     

Superjunction LDMOS on thick-SOI technology for RF applications

The feasibility of applying the superjunction (SJ) concept to a thick-SOI LDMOS transistor for RF base station applications is studied in this paper. The electrical performances of SJ thick-SOI LDMOS transistors are compared with those of the conventional RF LDMOS counterparts through an extensive 3D simulation work in terms of transconductance (g_m), specific-on resistance (R_ON), voltage capability (V_BR) and C-V characteristics. It is expected that SJ thick-SOI LDMOS structures will exhibit a significant R_ON reduction thanks to the N-doping concentration increment in the drift region. The charge balance in structures integrated on thick-SOI substrates with a P-type epitaxial layer requires a fit of the N and P pillar doping concentration, being the P pillar slightly lower doped than the N one. Variation of pillars doping concentrations is directly related to the device performance. Therefore, the R_ON/V_BR trade-off and the R_ON components and the C_gd evolution are shown as a function of pillar doping ratio.     

Thin-film silicon-on-sapphire LDMOS structures for RF power amplifier applications

This work is addressed to the investigation of the electro-thermal performance of RF-LDMOS transistors integrated in TF-SOI, TF-SOS and thinned TF-SOS substrates by means of numerical simulations. Reported experimental trap density, carrier mobility and capture cross-section values have been used together with sapphire datasheet thermal properties, in order to provide accurate simulation results. It is found that subthreshold characteristics are the same for all the analysed substrates while blocking-state, on-state and power dissipation process depends on the substrate type.     

RF LDMOS功率器件研制

基于ISE TCAD模拟软件对RF LDMOS器件的工艺流程和器件结构进行了优化设计,采用带栅极金属总线的版图结构降低栅电阻,同时简化了LDMOS器件的封装设计.通过实际流片和测试分析,重点讨论了漂移区注入剂量和漂移区长度对LDMOS器件的转移特性、击穿特性、截止频率及最大振荡频率的影响.测试结果表明该器件的阈值电压为1.8 V,击穿电压可达70 V,截止频率和最大振荡频率分别为9 GHz和12.6 GHz,并可提供0.7 W/mm的输出功率密度.     

一种适用于射频集成电路的抗击穿LDMOS设计

提出了一种具有深阱结构的RF LDMOS,该结构改善了表面电场分布,从而提高了器件的击穿电压。通过sil-vaco器件模拟软件对该结构进行验证,并对器件的掺杂浓度、阱宽、阱深、栅长进行优化,结果表明,在保证LDMOS器件参数不变的条件下,采用深阱工艺可使其击穿电压提升50%以上。     

具有n埋层pSOI三明治结构的射频功率LDMOS的输出特性

提出了具有n埋层pSOI三明治结构的射频功率LDMOS器件.漏至衬底寄生电容是影响射频功率LDMOS器件输出特性的重要因素之一,寄生电容越小,输出特性越好.分析表明n埋层pSOI三明治结构的射频功率LDMOS漏至衬底的结电容比常规射频功率LDMOS和n埋层pSOI射频功率LDMOS分别降低46.6%和11.5%.该结构器件IdB压缩点处的输出功率比常规LDMOS和n埋层pSOI LDMOS分别提高188%和10.6%,附加功率效率从n埋层pSOI LDMOS的37.3%增加到38.3%.同时该结构器件的耐压比常规LDMOS提高了约11%.     

A Nonlinear Electro-Thermal Scalable Model for High-Power RF LDMOS Transistors

A new nonlinear charge-conservative scalable dynamic electro-thermal compact model for laterally defused MOS (LDMOS) RF power transistors is described in this paper. The transistor is characterized using pulsed I–V and S-parameter measurements, to ensure isothermal conditions. A new extrinsic network and extrinsic parameter-extraction methodology is developed for high-power RF LDMOS transistor modeling, using manifold deembedding by electromagnetic simulation, and optimization of the extrinsic network parameter values over a broad frequency range. The intrinsic model comprises controlled charge and current sources that have been implemented using artificial neural networks, designed to permit accurate extrapolation of the transistor's performance outside of the measured data domain. A thermal sub-circuit is coupled to the nonlinear model. Large-signal validation of this new model shows a very good agreement with measurements at 2.14 GHz.      

Evolution study of the ElectroMagnetic Interference for RF LDMOS in series chopper application after thermal accelerated tests

The temperature is a critical parameter, for proper functioning of a system or a circuit, particularly in RF electronic devices. It considerable influence on reliability and performances; consequently plays an essential part in failure mechanisms and in lifetime. Recent studies have been focused in ElectroMagnetic Interferences (EMI) evolution after accelerated ageing tests and their effects on robustness behaviours (static, dynamic and RF). Even rarer to use RF devices in a power application.This paper deals with the (EMI) evolution of conducted interferences in common and differential mode of RF LDMOS (Radio Frequency Lateral Diffused Metal–Oxide–Semiconductor) devices applied to a series chopper. In addition their influences on the electrical parameters are studied after various thermal accelerated ageing tests. The experimental results (spectre and waveform parameters) are presented and discussed. The obtained measurements have highlighted that there is a clear increase in the amplitude of resonances on the interference spectra after ageing. The evolution is not the same for all the parameters and for the different thermal tests. The shift is proportional to temperature. To reach a better understanding of the physical mechanisms of parameter’s shift after thermal tests, a numerical model (Silvaco-Atlas) was employed to confirm the degradation phenomena. Actually, the charge trapping in the gate oxide causes a decrease in the Miller capacity value (C_rss), thereafter in turn a decrease in the disturbances level.     

Hot carrier effects on analog performance of N- and P-MOSFET's withoxynitride gate dielectrics

In this paper we report the impact of hot-carrier stress on analog performance of n- and p-MOSFET's with conventional oxide, NH₃-nitrided oxide (RTN) and reoxidized nitrided oxide (RTN/RTO) as gate dielectrics. Changes due to hot-carrier stress in crucial analog parameters viz., drain output resistance, voltage gain, and input offset voltage of a source coupled differential MOSFET pair are investigated. Results show that RTN/RTO gate dielectrics suppress degradation of analog parameters in n-MOSFET's but increase it slightly in p-MOSFET's, as compared to conventional oxide MOSFET's     

具有n埋层pSOI三明治结构的射频功率LDMOS的输出特性

提出了具有n埋层pSOI三明治结构的射频功率LDMOS器件. 漏至衬底寄生电容是影响射频功率LDMOS器件输出特性的重要因素之一,寄生电容越小,输出特性越好. 分析表明n埋层pSOI三明治结构的射频功率LDMOS漏至衬底的结电容比常规射频功率LDMOS和n埋层pSOI射频功率LDMOS分别降低46.6%和11.5%. 该结构器件1dB压缩点处的输出功率比常规LDMOS和n埋层pSOI LDMOS分别提高188%和10.6%,附加功率效率从n埋层pSOI LDMOS的37.3%增加到38.3%. 同时该结构器件的耐压比常规LDMOS提高了约11%.     

Comparative Analysis of VDMOS/LDMOS Power Transistors for RF Amplifiers

A comparison between the RF performance of vertical and lateral power MOSFETs is presented. The role of each parasitic parameter in the assessment of the power gain, 1-dB compression point, efficiency, stability, and output matching is evaluated quantitatively using new analytical expressions derived from a ten-element model. This study reveals that the contribution of the parasitic parameter on degradation of performance depends upon the specific technology and generic perceptions of source inductance and feedback capacitance in VDMOS degradation may not always hold. This conclusion is supported by a detailed analysis of three devices of the same power rating from three different commercial vendors. A methodology for optimizing a device technology, specifically for RF performance and power amplifier performance is demonstrated.      

功率RF LDMOS的关键参数研究

在功率RF LDMOS器件中，击穿电压、截止频率fT和导通电阻Ron是器件性能的关键参数，为提高这几个器件性能参数可采取的各种措施又往往是互相矛盾和相互制约的. 文中研究了几个关键参数之间的关系和优化方案，以及国际上在这方面所开展的研究和取得的进展，为进一步的研究和探索提供参考.     

射频功率LDMOS槽形漂移区结构优化设计

对射频功率LDMOS槽形漂移区的结构进行了优化设计.基于射频功率LDMOS的频率特性,提出了矩形、倒三角形和正三角形槽结构,对槽的位置、深度、宽度进行分析,在满足相同的耐压和导通电阻条件下,得出最优结构为正三角形槽结构,该结构实现了最大程度地减小寄生反馈电容的目的,寄生反馈电容减小了24%,LDMOS的截止频率提高了15%.     

功率RF LDMOS的关键参数研究

在功率RF LDMOS器件中,击穿电压、截止频率fT和导通电阻Ron是器件性能的关键参数,为提高这几个器件性能参数可采取的各种措施又往往是互相矛盾和相互制约的.文中研究了几个关键参数之间的关系和优化方案,以及国际上在这方面所开展的研究和取得的进展,为进一步的研究和探索提供参考.     

功率RF LDMOS的关键参数研究

在功率RF LDMOS器件中,击穿电压、截止频率fT和导通电阻Ron是器件性能的关键参数,为提高这几个器件性能参数可采取的各种措施又往往是互相矛盾和相互制约的.文中研究了几个关键参数之间的关系和优化方案,以及国际上在这方面所开展的研究和取得的进展,为进一步的研究和探索提供参考.     

RF LDMOS功率器件关键参数仿真

在RF LDMOS功率器件中,击穿电压、截止频率fT和导通电阻Ron是器件的关键参数,为提高这几个器件性能参数可采取的各种措施又往往是相互矛盾和相互制约的。文中研究了几个参数之间的关系和优化方案。现在RF LDMOS功率器件在向高工作电压、高输出功率、高可靠性以及脉冲应用等方向发展。所研制器件采用沟背面源结构,采用场板技术降低栅漏电容,采用多晶硅金属硅化物结构降低栅阻。研制结果表明,在漏源工作电压6V、频率520MHz、连续波的测试条件下,输出功率达到5.6W,增益大于12dB,效率大于55%。