A self-testing 2-/spl mu/m CMOS chip set for FFT applications

A chip set for high-speed radix-2 fast Fourier transform (FFT) applications up to 512 points is described. The chip set comprises a (16+16)/spl times/(12+12)-bit complex number multiplier, and a 16-bit butterfly chip for data reordering, twiddle factor generation, and butterfly arithmetic. The chips have been implemented using a standard cell design methodology on a 2-/spl mu/m bulk CMOS process. Three chips implement a complex FFT butterfly with a throughput of 10 MHz, and are cascadable up to 512 points. The chips feature an offline self-testing capability.     

An analog GFSK modulator in 0.35-/spl mu/m CMOS

An analog Gaussian frequency shift keying (GFSK) modulator designed in 0.35-/spl mu/m CMOS consumes 600 /spl mu/A from a 3-V supply and realizes an analog implementation of the FM differential equation. The modulator operates at baseband and is intended for use in a direct-conversion Bluetooth transmitter. It achieves a frequency deviation of 160 kHz with better than /spl plusmn/3% accuracy. The modulator implements an amplitude control loop to achieve a well-defined output swing. The total output harmonic distortion is less than 1%.     

A 92-MHz 13-bit IF digitizer using optimized SC integrators in 0.35-/spl mu/m CMOS technology

A feedforward compensation scheme with no Miller capacitors is proposed to overcome the bandwidth limitations of traditional Miller compensation schemes. The technique has been used in the design of an operational transconductance amplifier (OTA) with a dc gain of 80 dB, gain bandwidth of 1.4 GHz, phase margin of 62/spl deg/, and 2 ns settling time for 2-pF load capacitor in a standard 0.35-/spl mu/m CMOS technology. The OTA's current consumption is 4.6 mA. The OTA is used in the design of a fourth-order switched-capacitor bandpass /spl Sigma//spl Delta/ modulator with a clock frequency of 92 MHz. It achieves a peak signal-to-noise ratio of 80 and 54 dB for 270-kHz (GSM) and 3.84-MHz (CDMA) bandwidths, respectively and consumes 19 mA of current from a /spl plusmn/1.25-V supply.     

A 0.35-/spl mu/m CMOS 2-GHz VCO in wafer-level package

This letter presents a complementary metal oxide semiconductor (CMOS) voltage-controlled oscillator (VCO) with a high-Q inductor in a wafer-level package for the LC-resonator. The on-chip inductor is implemented using the redistribution metal layer of the wafer-level package (WLP), and therefore it is called a WLP inductor. Using the thick passivation and copper metallization, the WLP inductor has high quality-factor (Q-factor). A 2-nH inductor exhibits a Q-factor of 8 at 2 GHz. The center frequency of the VCO is 2.16 GHz with a tuning range of 385 MHz (18%). The minimum phase noise is measured to be -120.2 dBc/Hz at an offset frequency of 600 kHz. The dc power consumed by the VCO-core is 1.87 mW with a supply voltage of 1.7 V and a current of 1.1 mA. The output power with a 50-/spl Omega/ load is -12.5/spl plusmn/1.3 dBm throughout the whole tuning range. From the best of our knowledge, compared with recently published 2-GHz-band 0.35 /spl mu/m CMOS VCOs in the literature, the VCO in this work shows the lowest power consumption and the best figure-of-merit.     

A dual-mode 802.11b/bluetooth radio in 0.35-/spl mu/m CMOS

A fully integrated dual-mode CMOS transceiver tuned to 2.4 GHz consumes 65 mA in receive mode and 78 mA in transmit mode from a 3-V supply. The radio includes all the receive and transmit building blocks, such as frequency synthesizer, voltage-controlled oscillator (VCO), and power amplifier, and is intended for use in 802.11b and Bluetooth applications. The Bluetooth receiver uses a low-IF architecture for higher level of integration and lower power consumption, while the 802.11b receiver is direct conversion. The receiver achieves a typical sensitivity of -88 dBm at 11 Mb/s for 802.11b, and -83 dBm for Bluetooth mode. The receiver minimum IIP3 is -8 dBm. Both transmitters use a direct-conversion architecture, and deliver a nominal output power of 0 dBm, with a power range of 20 dB in 2-dB steps.     

A 3-V, 0.35-/spl mu/m CMOS Bluetooth receiver IC

A fully integrated CMOS low-IF Bluetooth receiver is presented. The receiver consists of a radio frequency (RF) front end, a phase-locked loop (PLL), an active complex filter, a Gaussian frequency shift keying (GFSK) demodulator, and a frequency offset cancellation circuit. The highlights of the receiver include a low-power active complex filter with a nonconventional tuning scheme and a high-performance mixed-mode GFSK demodulator. The chip was fabricated on a 6.25-mm/sup 2/ die using TSMC 0.35-/spl mu/m standard CMOS process. -82 dBm sensitivity at 1e-3 bit error rate, -10 dBm IIP3, and 15 dB noise figure were achieved in the measurements. The receiver active current is about 65 mA from a 3-V power supply.     

A 10.7-MHz sixth-order SC ladder filter in 0.35-/spl mu/m CMOS technology

A sixth-order 10.7-MHz bandpass switched-capacitor filter based on a double terminated ladder filter is presented. The filter uses a multipath operational transconductance amplifier (OTA) that presents both better accuracy and higher slew rate than previously reported Class-A OTA topologies. Design techniques based on charge cancellation and slower clocks are used to reduce the overall capacitance from 782 down to 219 unity capacitors. The filter's center frequency and bandwidth are 10.7 MHz and 400 kHz, respectively, and a passband ripple of 1 dB in the entire passband. The quality factor of the resonators used as filter terminations is around 32. The measured (filter + buffer) third-intermodulation (IM3) distortion is less than -40 dB for a two-tone input signal of +3-dBm power level each. The signal-to-noise ratio is roughly 58 dB while the IM3 is -45 dB; the power consumption for the standalone filter is 42 mW. The chip was fabricated in a 0.35-/spl mu/m CMOS process; filter's area is 0.84 mm/sup 2/.     

6 GHz transimpedance amplifier for optical sensing system in low-cost 0.35 /spl mu/m CMOS

A high-speed transimpedance amplifier (TIA) has been designed and implemented in a low cost 0.35 mum CMOS technology. Combining the techniques of regulated cascode input stage, current shunt feedback and inductive-series peaking, the TIA achieves a transimpedance gain of 51 dBOmega and 3 dB bandwidth of 6 GHz, in the presence of a photodiode capacitance of 0.6 pF. This is believed to be the fastest TIA ever reported in 0.35 mum CMOS technology     

A 1.5-V 45-mW direct-conversion WCDMA receiver IC in 0.13-/spl mu/m CMOS

A 2-GHz direct-conversion receiver for wide-band code division multiple access (WCDMA) is presented. It includes two low-noise amplifiers (LNAs), an I/Q demodulator, and two sixth-order baseband channel select filters with programmable gain. Quadrature local oscillator (LO) signals are generated on chip in a frequency divider flip-flop. An external interstage filter between the LNAs rejects transmitter leakage to relax demodulator linearity requirements. A low-voltage demodulator topology improves linearity as well as demodulator output pole accuracy. The active-RC baseband filter uses a programmable servo loop for offset compensation and provides an adjacent channel rejection of 39 dB. Programmable gain over 71-dB range in 1-dB steps is merged with the filter to maximize dynamic range. An automatic on-chip frequency calibration scheme provides better than 1.5% corner frequency accuracy. The receiver is integrated in a 0.13-/spl mu/m CMOS process with metal-insulator-metal (MIM) capacitors. Measured receiver performance includes a 6.5-dB noise figure, IIP2 of +27 dBm, and IIP3 of -8.6 dBm. Power consumption is 45 mW.     

A 2-GHz carrier leakage calibrated direct-conversion WCDMA transmitter in 0.13-/spl mu/m CMOS

A highly integrated 2-GHz, 0.13-/spl mu/m CMOS direct-conversion transmitter for wide-band code division multiple access (WCDMA) is described. Different circuit and calibration techniques are presented that successfully suppress the carrier leakage and enable the direct-upconversion architecture to meet all WCDMA specifications. The transmitter delivers +2.5 dBm output power while consuming only 45 mA from its nominal 1.5-V supply. The overall gain can be programmed in 1-dB steps over a 100-dB range with 0.4 dB accuracy. The transmitter achieves an OIP3 of +19.3 dBm, an error vector magnitude of 4.3%, and an adjacent channel leakage ratio of -38 dBc. The measured output noise of -146 dBm/Hz in the DCS Rx band and -149 dBm/Hz in the UMTS Rx band is sufficiently low to provide an option to increase the integration level even further by eliminating the external Tx interstage filter between the power amplifier and its driver.     

Ultra low power 2.4-GHz 0.35-/spl mu/m CMOS dual-modulus prescaler design

This letter presents the design and implementation of a dual-modulus (64/65) prescaler based upon the phase-switching technique. Low power consumption is achieved by using one dynamic flip-flop in the full-speed divide-by-four circuit and no power-hungry synchronizing circuits to tackle the glitch problem. The proposed design is fabricated using 0.35-/spl mu/m standard CMOS process and is measured to operate from 2.08-2.66GHz with power dissipation of less than 1mW.     

Dual-modulus 127/128 FOM enhanced prescaler design in 0.35-/spl mu/m CMOS technology

The dual-modulus prescaler is a critical block in CMOS systems like high-speed frequency synthesizers. However, the design of high-moduli, high-speed, and low-power dual-modulus prescalers remains a challenge. To face the challenge, this paper introduces the idea of using transmission gates and pseudo-PMOS logic to realize the dual-modulus prescaler. The topology of the prescaler proposed is different from prior designs primarily in two ways: 1) it uses transmission gates in the critical path and 2) the D flip-flops (DFFs) used in the synchronous counter comprise pseudo-PMOS inverters and ratioed latches. A pseudo-PMOS logic-based DFF is introduced and used in the proposed prescaler design. Based on the proposed topology, a dual-modulus divide-by-127/128 prescaler is implemented in 0.35-/spl mu/m CMOS technology. It consumes 4.8 mW from a 3-V supply. The measured phase noise is -143.4 dBc/Hz at 600 kHz. The silicon area required is only 0.06 mm/sup 2/. There are no flip flops or logic gates in the critical path. This topology is suitable for high-speed and high-moduli prescaler designs. It reduces: 1) design complexity; 2) power consumption; and 3) input loading. Measurement results are provided. An improvement in the figure of merit is shown.     

A Bluetooth radio in 0.18-/spl mu/m CMOS

This paper describes the results of an implementation of a Bluetooth radio in a 0.18-/spl mu/m CMOS process. A low-IF image-reject conversion architecture is used for the receiver. The transmitter uses direct IQ-upconversion. The VCO runs at 4.8-5.0 GHz, thus facilitating the generation of 0/spl deg/ and 90/spl deg/ signals for both the receiver and transmitter. By using an inductor-less LNA and the extensive use of mismatch simulations, the smallest silicon area for a Bluetooth radio implementation so far can be reached: 5.5 mm/sup 2/. The transceiver consumes 30 mA in receive mode and 35 mA in transmit mode from a 2.5 to 3.0-V power supply. As the radio operates on the same die as baseband and SW, the crosstalk-on-silicon is an important issue. This crosstalk problem was taken into consideration from the start of the project. Sensitivity was measured at -82 dBm.     

A 1-V 2.5-mW 5.2-GHz frequency divider in a 0.35-/spl mu/m CMOS process

A 1-V low-power high-speed dynamic-loading frequency divider is proposed using novel D flip-flops with a common-gate topology and with a single clock phase. A simple and accurate small-signal analysis model is provided to estimate the operating frequencies of the divider. Implemented in a standard digital 0.35-/spl mu/m CMOS process and at 1-V supply, the proposed frequency divider measures a maximum operating frequency up to 5.2 GHz with a power consumption of 2.5 mW.     

An 8-Gb/s/pin simultaneously bidirectional transceiver in 0.35-/spl mu/m CMOS

This paper presents architecture, circuits, and test results for a single-ended, simultaneously bidirectional interface capable of a total throughput of 8 Gb/s per pin. The interface addresses noise reduction challenges by utilizing a pseudodifferential reference with noise immunity approaching that of a fully differential reference. The transmitter supports on-chip termination, predistortion, and low-skew near-end outgoing signal echo cancellation. The receiver's sense amplifier evaluates the average of two differential input signals without use of analog components and utilizes imbalanced charge injection to compensate for offset voltages. A test chip integrated in a 0.35-/spl mu/m digital CMOS technology uses the proposed techniques to implement an 8-bit wide single-ended voltage-mode simultaneous bidirectional interface and achieves a performance of 8 Gb/s per pin.     

A 0.8-dB insertion-loss, 17.4-dBm power-handling, 5-GHz transmit/receive switch with DETs in a 0.18-/spl mu/m CMOS process

An optimized single-pole double-throw (SPDT) transmit/receive (T/R) switch has been fabricated using depletion-layer-extended transistors (DETs) in a 0.18 /spl mu/m CMOS process. The switch features the highest performance to date of any switch using a CMOS process, of a 0.8 dB insertion-loss, 23 dB isolation and 17.4 dBm power-handling capability at 5 GHz. The low insertion-loss has been achieved with the effects of junction capacitance decrease and substrate resistance increase in the DET, the adoption of low-loss shielded-pads, and several layout optimizations. The high power-handling capability is owing to the combined effect of the adoption of the source/drain dc biasing scheme and the high substrate resistance in the DET.     

A 2-V 2.3/4.6-GHz dual-band frequency synthesizer in 0.35-/spl mu/m digital CMOS process

This brief describes the design of a frequency synthesizer for 2.3/4.6-GHz wireless applications in a 0.35-/spl mu/m digital CMOS process. This synthesizer provides dual-band output signals by means of frequency doubling techniques. Output frequency of the proposed synthesizer ranges from 1.87-2.3 GHz, and 3.74-4.6GHz. This chip consumes a total power of 80 mW from a single 2-V supply, including 45 mW for dual-band output buffers. Core size is 2200 /spl mu/m/spl times/1600 /spl mu/m.     

Low-output-impedance 0.6 /spl mu/m CMOS sub-bandgap reference

A 0.6 mum CMOS sub-bandgap reference circuit, the output voltage of which is, unlike reported in the literature, concurrently low voltage and low output impedance, is presented. Experimental measurements verify that the proposed circuit, which produces a first-order temperature-compensated reference voltage of 890 my sources up to 5 mA of load current and rejects noise by a factor of 30.8-8.1 dB at 500 kHz- 4 MHz, neither of which feature is achieved by state-of-the-art sub-bandgap circuits.     

A 17-mW transmitter and frequency synthesizer for 900-MHz GSM fully integrated in 0.35-/spl mu/m CMOS

A fractional-N phase-locked loop (PLL) serves as a Gaussian minimum-shift keying (GMSK) transmitter and a receive frequency synthesizer for GSM. The entire transmitter/synthesizer is fully integrated in 0.35-/spl mu/m CMOS and consumes 17.4 and 12 mW from 2.5 V in the transmit and receive modes, respectively, including an on-chip voltage-controlled oscillator. The circuit meets GSM specifications on modulation accuracy in transmit mode, and measured phase noise from the closed-loop PLL is -148 dBc/Hz and -162 dBc/Hz, respectively, at 3- and 20-MHz offset. Worst case spur at 13-MHz offset is -77 dBc.     

A low-voltage folded-switching mixer in 0.18-/spl mu/m CMOS

Scaling of CMOS technologies has a great impact on analog design. The most severe consequence is the reduction of the voltage supply. In this paper, a low voltage, low power, AC-coupled folded-switching mixer with current-reuse is presented. The main advantages of the introduced mixer topology are: high voltage gain, moderate noise figure, moderate linearity, and operation at low supply voltages. Insight into the mixer operation is given by analyzing voltage gain, noise figure (NF), linearity (IIP3), and DC stability. The mixer is designed and implemented in 0.18-/spl mu/m CMOS technology with metal-insulator-metal (MIM) capacitors as an option. The active chip area is 160 /spl mu/m/spl times/200 /spl mu/m. At 2.4 GHz a single side band (SSB) noise figure of 13.9 dB, a voltage gain of 11.9 dB and an IIP3 of -3 dBm are measured at a supply voltage of 1 V and with a power consumption of only 3.2 mW. At a supply voltage of 1.8 V, an SSB noise figure of 12.9 dB, a voltage gain of 16 dB and an IIP3 of 1 dBm are measured at a power consumption of 8.1 mW.