一种高精度BiCMOS电流模带隙基准源

采用Xfab0.35μmBiCMOS工艺设计了一种高电源抑制比（PSRR）、低温漂、输出0.5V的带隙基准源电路。该设计中,电路采用新型电流模带隙基准,解决了传统电流模带隙基准的第三简并态的问题,且实现了较低的基准电压;增加了修调电路,实现了基准电压的微调。利用Cadence软件对其进行仿真验证,其结果显示,当温度在-40～＋120℃范围内变化时,输出基准电压的温度系数为15ppm/℃;电源电压在2～4V范围内变化时,基准电压摆动小于0.06mV;低频下具有-102.6dB的PSRR,40kHz前电源抑制比仍小于-100dB。     

一种低温漂、高精度CMOS带隙基准源设计

基于线性分段补偿的基本原理,依据输出支路内部的温度负反馈结构,提出了一种结构简单、适应不同开口方向的高阶补偿方法。并设计了一种基于电流镜结构的低温漂、高精度的电压基准电路。CSMC 0.35 μm CMOS工艺的仿真结果表明,经高阶补偿的电压模基准,在-40~125 ℃温区范围内温度系数为2.84×10^-6/℃,低频100 Hz时的PSRR达到-70.6 dB,10 kHz为-63.36 dB。当电源电压在2~3 V范围内变化时,其电压值波动为3 mV/V。整个带隙基准电压源具有较好的综合性能。     

A CMOS voltage reference based on weighted /spl Delta/V/sub GS/ for CMOS low-dropout linear regulators

A CMOS voltage reference, which is based on the weighted difference of the gate-source voltages of an NMOST and a PMOST operating in saturation region, is presented. The voltage reference is designed for CMOS low-dropout linear regulators and has been implemented in a standard 0.6-/spl mu/m CMOS technology (V/sub thn//spl ap/|V/sub thp/|/spl ap/0.9 V at 0/spl deg/C). The occupied chip area is 0.055 mm/sup 2/. The minimum supply voltage is 1.4 V, and the maximum supply current is 9.7 /spl mu/A. A typical mean uncalibrated temperature coefficient of 36.9 ppm//spl deg/C is achieved, and the typical mean line regulation is /spl plusmn/0.083%/V. The power-supply rejection ratio without any filtering capacitor at 100 Hz and 10 MHz are -47 and -20 dB, respectively. Moreover, the measured noise density with a 100-nF filtering capacitor at 100 Hz is 152 nV//spl radic/(Hz) and that at 100 kHz is 1.6 nV//spl radic/(Hz).     

高电源抑制比低噪声带隙基准电压源的设计

基于带隙基准原理,通过优化电路结构和采用BiCMOS技术,提出一种精度高、噪声小的带隙基准源电路。利用具有高开环增益的折叠式共源共栅放大器,提高了低频电压抑制比;应用低跨导PMOS对管及电路输出端低通滤波器,实现了更低的噪声输出;合理的版图设计减小了失调电压带来的影响。Hspice仿真结果表明,在3V电源电压下,输出基准电压为1.2182mV,温度系数为1.257×10-5/℃;频率从103～105 Hz变化时,输出噪声最大值的变化量小于5μV。流片测试结果表明,该基准源输出基准电压的电源抑制比高,温度系数小,噪声与功耗低。     

一种无电阻高电源抑制比的CMOS带隙基准源

提出一种输出低于1V的、无电阻高电源抑制比的CMOS带隙基准源(BGR).该电路适用于片上电源转换器.用HJTC0.18μm CMOS工艺设计并流片实现了该带隙基准源,芯片面积(不包括pad和静电保护电路)为0.031mm2.测试结果表明,采用前调制器结构,带隙基准源电路的输出在100Hz与lkHz处分别获得了-70与-62dB的高电源抑制比.电路输出一个0.5582V的稳定参考电压,当温度在0～85℃范围内变化时,输出电压的变化仅为1.5mV.电源电压VDD在2.4～4V范围内变化时,带隙基准输出电压的变化不超过2mV.     

一种-100 dB电源抑制比的非带隙基准电压源

该文提出一种非带隙基准电路,通过一个带超级源极跟随器的预调制电路提供一个稳定的电压,为基准核心电路供电。超级源极跟随器通过降低基准核心电路电源端的对地阻抗,有效提高了基准电路的电源抑制能力。该基准电路采用0.35 m CMOS 工艺设计并流片,测试结果表明,该电路的工作电源电压为1.8~5 V,静态电流约为13 A。低频处电源抑制比(PSRR)约等于-100 dB,在小于1 kHz频率范围内PSRR均优于-93 dB。并且其片上面积仅为0.013 mm2。     

一种用于音频Σ-ΔA/D转换器的CMOS带隙电压基准源

在传统带隙基准电压源电路结构的基础上,通过在运放中引入增益提高级,实现了一种用于音频Σ-ΔA/D转换器的CMOS带隙电压基准源。在一阶温度补偿下实现了较高的电源抑制比(PSRR)和较低的温度系数。该电路采用SIMC 0.18-μm CMOS工艺实现。利用Cadence/Spectre仿真器进行仿真,结果表明,在1.8 V电源电压下,-40～125℃范围内,温度系数为9.699 ppm/℃;在27℃下,10 Hz时电源抑制比为90.2 dB,20 kHz时为74.97 dB。     

一种二阶曲率补偿带隙基准电压源

利用CMOS工艺中Poly电阻和N-well电阻温度系数的不同,设计了一种输出可调的二阶曲率补偿带隙基准电压源.采用Chartered 0.35μm CMOS工艺模型,使用Cadence工具对电路进行了仿真,结果表明电路在电源电压为1.8V时可正常工作,当其在1.8～3V范围内变化时,基准电压变化仅有3.8mV;工作电压为2V时,输出基准电压在-40°C到80°C的温度范围内温度系数为1.6ppm/°C,工作电流为24μA,低频下的电源抑制比为-47dB.该带隙基准电压源的设计可以满足低温漂、高稳定性、低电源电压以及低功耗的要求.     

Low-voltage high-gain differential OTA for SC circuits

A new differential operational transconductance amplifier (OTA) for SC circuits that operates with a supply voltage of less than two transistor threshold voltages is presented. Its simplicity relies on the use of a low-voltage regulated cascode circuit, which achieves very high output impedance under low-voltage restrictions. The OTA has been designed to operate with a supply voltage of V/sub DD/=1.5 V, using a 0.6 /spl mu/m CMOS technology with transistor threshold voltages of V/sub TN/=0.75 V and V/sub TP/=-0.85 V. Post-layout simulation results for a load capacitance (C/sub L/) of 2 pF show a 75 MHz gain-bandwidth product and 100 dB DC gain with a quiescent power consumption of 750 /spl mu/W.     

Low-power low-voltage reference using peaking current mirror circuit

A low-power low-voltage bandgap reference using the peaking current mirror circuit with MOSFETs operated in the subthreshold region is presented. A demonstrative chip was fabricated in 0.35 /spl mu/m CMOS technology, achieving the minimum supply voltage 1.4 V, the reference voltage around 580 mV, the temperature coefficient 62 ppm//spl deg/C, the supplied current 2.3 /spl mu/A, and the power supply noise rejection ratio of -84 dB at 1 kHz.     

一种改进型BiCMOS带隙基准源的仿真设计

依据带隙基准原理,设计了一种基于90 nm BiCMOS工艺的改进型带隙基准源电路.该电路设置运算跨导放大器以实现低压工作,用共源-共栅MOS管提高电路的电源抑制比,并加设了新颖的启动电路.HSPICE仿真结果表明,在低于1.1 V的电源电压下,所设计的电路能稳定地工作,输出稳定的基准电压约为610 mV;在电源电压V_(DD)为1.2 v、温度27℃、频率为10 kHz以下时,电源噪声抑制比约为-45 dB;当温度为-40～120℃时,电路的温度系数约为11 × 10~(-6)℃,因此该基准源具有低工作电压、高电源抑制比、低温度系数等性能优势.     

Sub-1-V CMOS proportional-to-absolute temperature references

Presents a new all-MOS circuit technique for very-low-voltage proportional-to-absolute temperature (PTAT) references. Optimization of supply scaling below the sum of threshold voltages is based on log companding and implemented by operating the MOSFET in weak inversion. The key design equations for current (/spl mu/A) and voltage (sub-100 mV) references and their standard deviations (around 5%) are derived by analytical analysis. Two sub-1-V sub-5-/spl mu/W integrated PTAT references are presented and exhaustively tested for 1.2- and 0.35-/spl mu/m very large scale integration technologies. Both designs report good agreement between analytical, simulated, and experimental data, exhibiting PSRR(DC)+>60 dB. Hence, the resulting PTAT circuits are suitable for very-low-voltage system-on-a-chip applications in digital CMOS technologies.     

带2阶温度补偿的多输出带隙基准电压源

基于传统带隙基准的原理,通过优化电路结构,消除双极晶体管基极．发射极电压中的非线性项,设计了一种带2阶补偿的多输出带隙基准电压源。整个电路采用CSMC0．5μmCMOS工艺模型进行仿真。Spectre仿真结果表明,在-55～125℃的温度范围内,带隙基准电压源的温度系数为3．1ppm／℃,在5V电源电压下,输出基准电压为1．2994V;带隙基准电压源的电源抑制比在低频时为84．5dB;在5v电源电压下,可以同时输出0—5V多个基准电压。     

A 0.6V 44.6 ppm/ºC subthreshold CMOS voltage reference with wide temperature range and inherent leakage compensation

In this paper, a 0.6 V subthsheshold CMOS voltage reference (CVR) achieving wide temperature range and high power supply ripple rejection (PSRR) is presented. The proposed CVR structure can compensate the high temperature leakage and current mirror induced mismatches so as to increase the operating temperature range. The generated reference voltage of the proposed CVR circuit is the threshold voltage difference of two NMOS transistors, leading to relatively small variations. Moreover, the enhanced current source helps achieve high PSRR. The proposed CVR circuit is implemented in a standard 0.18-μm CMOS technology. Measurement results show that, with one single trimming, a mean output of 344 mV with standard deviation of only 2.89 mV and average TC of 44.6 ppm/°C over a wide temperature range from −40 °C to 125 °C is achieved. The measured PSRR is −68 dB, −52 dB and −52 dB at 10 Hz, 100 kHz and 10 MHz, respectively. The measured line sensitivity (LS) is 0.06%/V with a power supply from 0.6 V to 2 V while consuming 19.8  nW at 0.6 V supply. The active area is 0.019 mm².     

Micro-power low-offset instrumentation amplifier IC design for biomedical system applications

This work presents a micro-power low-offset CMOS instrumentation amplifier integrated circuit with a large operating range for biomedical system applications. The equivalent input offset voltage is improved using a new circuit technique of offset cancellation that involves a two-phase clocking scheme with a frequency of 20 kHz. Channel charge injection is cancelled by the symmetrical circuit topology. With the wide-swing cascode bias circuit design, this amplifier realizes a very high power-supply rejection ratio (PSRR), and can be operated at single supply voltage in the range between 2.5-7.5 V. It was fabricated using 0.5-/spl mu/m double-poly double-metal n-well CMOS technology, and occupies a die area of 0.2 mm/sup 2/. This amplifier achieves a 160-/spl mu/V typical input offset voltage, 0.05% gain linearity, greater than 102-dB PSRR, an input-referred rms noise voltage of 45 /spl mu/V, and a current consumption of 61 /spl mu/A at a low supply voltage of 2.5 V. Experimental results indicate that the proposed amplifier can process the input electrocardiogram signal of a patient monitoring system and other portable biomedical devices.     

一种低功耗低温度系数基准电压源的设计

基于0.35μm CMOS工艺,设计一种不带电阻的低功耗基准电压源,该基准源工作电压范围1.2 V~3.6 V.在3.6 V和室温时测量最大的电源电流为130 nA.在-20℃~100℃温度范围内,该基准电压温度系数为7.5×10-6/℃.在1.2 V~3.6 V电源电压范围内,线灵敏度为40×10-6/V,且在100 Hz时电源抑制比为-50 dB.该基准电压源适合在一些例如移动设备、植入式医疗设备和智能传感器网络等节能集成电路上应用.     

基于温度补偿的无运放低压带隙基准源设计

设计了一种带温度补偿的无运放低压带隙基准电路。提出了同时产生带隙基准电压源和基准电流源的技术,通过改进带隙基准电路中的带隙负载结构以及基准核心电路,基准电压和基准电流可以分别进行温度补偿。在0.5μmCMOS N阱工艺条件下,采用spectre进行模拟验证。仿真结果表明,在3.3V条件下,在-20～100℃范围内,带隙基准电压源和基准电流源的温度系数分别为35.6ppm/℃和37.8ppm/℃,直流时的电源抑制比为-68dB,基准源电路的供电电压范围为2.2～4.5V。     

一种高精度CMOS带隙基准电路的设计

采用ASMC0.35μm CMOS工艺设计了低功耗、高电源抑制比(PSRR)、低温漂、输出1V的带隙基准源电路。该设计中,偏置电压采用级联自偏置结构,运放的输出作为驱动的同时也作为自身电流源的驱动,实现了与绝对温度成正比(PTAT)温度补偿。通过对其进行仿真验证,当温度在-40～125℃和电源电压在1.6～5V时,输出基准电压具有3.68×10-6/℃的温度系数,Vref摆动小于0.094mV;在低频时具有-114.6dB的PSRR,其中在1kHz时为-109.3dB,在10kHz时为-90.72dB。     

一种阵列式版图布局的低温度系数CMOS带隙基准电压源

设计了一款低温度系数的自偏置CMOS带隙基准电压源电路,分析了输出基准电压与关键器件的温度依存关系,实现了低温度系数的电压输出。后端物理设计采用多指栅晶体管阵列结构进行对称式版图布局,以压缩版图面积。基于65 nm/3.3 V CMOS RF器件模型,在Cadence IC设计平台进行原理图和电路版图设计,并对输出参考电压的精度、温度系数、电源抑制比(PSRR)和功耗特性进行了仿真分析和对比。结果表明,在3.3 V电源和27℃室温条件下,输出基准电压的平均值为765.7 mV,功耗为0.75μW;在温度为-55~125℃时,温度系数为6.85×10~(-6)/℃。此外,输出基准电压受电源纹波的影响较小,1 kHz时的PSRR为-65.3 dB。     

低温漂高PSRR新型带隙基准电压源的研制

利用带隙电压基准的基本原理,结合自偏置共源共栅电流镜以及适当的启动电路,设计了一种新型基准电压源。获得了一个低温度系数、高电源抑制比的电压基准。通过对输出端添加运算放大器,把带隙基准电路产生的1.2 V电压提高到3.5 V,提高了芯片性能。用Cadence软件和CSMC的0.5μm CMOS工艺进行了仿真,结果表明,当温度在-20～+120℃,温度系数为9.3×10-6/℃,直流时的电源抑制比为-82 dB。该基准电压源能够满足开关电源管理芯片的使用要求,并取得了较好的效果。