Statistical equipment modeling for VLSI manufacturing: anapplication for LPCVD

An equipment characterization and modeling methodology has been developed. The methodology is based on the development of generic first-principle process models. These models are subsequently refined and fitted to specific manufacturing equipment by using a multistage D-optimal experimental design. The methodology has been successfully applied to a low-pressure chemical vapor deposition (LPCVD) furnace for undoped polysilicon deposition. A two-stage D-optimal experiment with 24 runs has yielded fitted models for the film growth rate and film residual stress. The calibrated models agree well with the experimental data and account for the observed variations     

Methodology for feedback variable selection for control of semiconductor manufacturing processes - Part 1: Analytical and simulation results

As integrated circuit feature size continues to shrink, yield loss due to parametric variation will become more and more significant. Real-time feedback control provides a means of reducing parametric variation and therefore limiting this type of yield loss. A challenge in applying feedback control to semiconductor manufacturing processes is selecting the variables to feed back. In many manufacturing processes, the important product variables cannot be measured in real-time and therefore cannot be directly controlled using real-time feedback control. An alternative, which has proven effective, is to feed back process variables closely related to the product variables. Typically, selection of process variables to feed back is based upon qualitative knowledge about the process, which in many cases is limited. In this paper, an empirical methodology for selecting the best process variables for feedback in order to minimize variation in the product variables is presented. Two versions of this methodology are described, a full version and a "lite" version. The latter is an abridged version of the former. Prior to introducing this methodology, a condition under which real-time feedback control will reduce product variable variation is derived. This condition is used to highlight the sources of variance in the product variables, information which is used to explain how the methodology works. The methodology is evaluated using simulated experiments. Both the full and lite versions prove to be effective under the assumptions stated for this study although the full version is clearly superior in terms of performance. Application of the methodology to a reactive ion etch process is described in a companion work.     

Statistical feedback control of a plasma etch process

This paper presents the methodology developed for the automatic feedback control of a silicon nitride plasma etch process. The methodology provides an augmented level of control for semiconductor manufacturing processes, to the level that the operator inputs the required process quality characteristics (e.g. etch rate and uniformity values) instead of the desired process conditions (e.g., specific RF power, pressure, gas flows). The optimal equipment settings are determined from previously generated process/equipment models. The control algorithm is driven by the in-situ measurements, using in-line sensors monitoring each wafer. The sensor data is subjected to Statistical Quality Control (SQC) to determine if deviations from the required process observable values can be attributed to noise in the system or are due to a sustained anomalous behavior of the equipment. Once a change in equipment behavior is detected, the process/equipment models are adjusted to match the new state of the equipment. The updated models are used to run subsequent wafers until a new SQC failure is observed. The algorithms developed have been implemented and tested, and are currently being used to control the etching of wafers under standard manufacturing conditions     

Simulation of yield/cost learning curves with Y4

This paper describes a prototype of a discrete event simulator-Y4 (yield forecaster)-capable of simulating defect related yield loss and manufacturing cost as a function of time, for a multiproduct IC manufacturing line. The methodology of estimating yield and cost is based on mimicking the operation and characteristics of a manufacturing line in the time domain. The paper presents a set of models that take into account the effect of particles introduced during wafer processing as well as changes in their densities due to process improvements. These models also illustrate a possible way of accounting for the primary attributes of fabrication, product, and failure analysis which affect yield learning. A spectrum of results are presented for a manufacturing scenario to demonstrate the usefulness of the simulator in formulating IC manufacturing strategies     

Analysis of process models

Process modeling tools, such as the integrated definition (IDEF) methodology, allow for a systematic representation of processes in manufacturing, product development, and service applications. Most of the process modeling methodologies are based on informal notation, lack mathematical rigor, and are static and qualitative, and thus can be difficult to use for analysis. In this paper, a new analysis approach for process models based on signed directed graphs (SDGs) and fuzzy sets is presented. A membership function of fuzzy sets quantifies and transforms incomplete and ambiguous information of process variables into an SDG qualitative model. The effectiveness of the approach is illustrated with an industrial example. The architecture of an intelligent system for qualitative/quantitative analysis of process models is presented     

Nanotechnology copper interconnect processes integrations for high aspect ratio without middle etching stop layer

As design rules for interconnection tend to result in the reduction of silicon chip size, devices have been miniaturized and fabrication processes have become more complex. Implementation of Cu and low dielectric constant (low-k) materials in the manufacturing process integration require a complete understanding of these process characteristics and the challenges that appear during the hard mask based dual damascene approach. To create highly reliable electrical interconnects, the interfaces between the Cu metal and low-k must be optimized during the lithography, etching, ashing and copper processes. For higher aspect ratios interconnect profiles, however this approach leads to increased sidewall roughness and undercut. To suppress problems in the fabrication processes, the balance of the processes integration should be quantitatively and instantaneously controlled to the optimum manufacturing technologies. These process characteristics and manufacturing mechanism optimization will also be discussed.     

A control-to-target architecture for process control

In this paper, we present an architecture for a run-to-run supervisory process control system that allows the engineer to tailor the form of control for specific processes. The architecture supports different degrees of control, from model-based control to statistical process control to diagnosis. The architecture is compatible with different techniques for model optimization, data acquisition and analysis, and model adjustment and feedback. A primary feature of this architecture is that engineers can define processes In terms of their desired effects, and use process models that transform those effects into machine settings. We have used object technology as the basis for our design and implementation of the architecture. Object-oriented modeling provides the flexibility required to support the varying degrees of control required in a large-scale manufacturing facility. In this paper, we define the components of the architecture, and describe in detail a process control system that was built with this architecture and used in the Computer Integrated manufacturing (CIM) system built for the Microelectronics Manufacturing Science and Technology (MMST) demonstration facility. Although the architecture was developed for the purpose of controlling semiconductor manufacturing processes, the principles behind the architecture may be applied to the control of any process     

Feasible approach for processes integration of CMOS transistor gate/side-wall spacer patterning fabrication

As the gate length is scaling down, the spacer design for CMOS transistor becomes increasingly critical manufacturing process. In recent CMOS technologies, side-wall spacers play an important role in the control of short channel effects by offsetting ion implantation profiles from the edge of the gate. The present approach to overcome these fabrication limitations. The spacer patterning technology yields critical dimension variations of minimum-sized features which are much smaller than achieved by optical integrated lithography and etching processes. Generally relates to semiconductor manufacturing, and more particularly to nanotechnology fabrication feasibility for CMOS wafer process on gate spacer technology manufacture feasibility. A modified side-wall spacer patterning method was implemented for using conventional lithography and etching processing technology. Based on the systematical investigation of the effects of the various etch conditions on etching profile and their impacts on the sidewall transistor gate structure, a novel integrated process for well controlled side-wall spacer formation was developed for fabrication.     

Neurofuzzy modeling of chemical vapor deposition processes

The modeling of semiconductor manufacturing processes has been the subject of intensive research efforts for years. Physical-based (first-principle) models have been shown to be difficult to develop for processes such as plasma etching and plasma deposition, which exhibit highly nonlinear and complex multidimensional relationships between input and output process variables. As a result, many researchers have turned to empirical techniques to model many semiconductor processes. This paper presents a neurofuzzy approach as a general tool for modeling chemical vapor deposition (CVD) processes. A five-layer feedforward neural network is proposed to model the input-output relationships of a plasma-enhanced CVD deposition of a SiN film. The proposed five-layer network is constructed from a set of input-output training data using unsupervised and supervised neural learning techniques. Product space data clustering is used to perform the partitioning of the input and output spaces. Fuzzy logic rules that describe the input-output relationships are then determined using competitive learning algorithms. Finally, the fuzzy membership functions of the input and output variables are optimally adjusted using the backpropagation learning algorithm. A salient feature of the proposed neurofuzzy network is that after the training process, the internal units are transparent to the user, and the input-output relationship of the CVD process can be described linguistically in terms of IF-THEN fuzzy rules. Computer simulations are conducted to verify the validity and the performance of the proposed neurofuzzy network for modeling CVD processes     

Parametric manufacturing yield modeling of GaAs/AlGaAs multiplequantum well avalanche photodiodes

GaAs/AlGaAs multiple quantum well (MQW) avalanche photodiodes (APD's) are of interest as an ultra-low noise image capture mechanism for high-definition systems. Since literally millions of these devices must be fabricated for imaging arrays, it is critical to evaluate potential performance variations of individual devices in light of the realities of semiconductor manufacturing. Specifically, even in a defect-free manufacturing environment, random variations in the fabrication process will lead to varying levels of device performance, Accurate device performance prediction requires precise characterization of these variations. This paper presents a systematic methodology for modeling the parametric performance of GaAs MQW APD's. The approach described requires a model of the probability distribution of each of the relevant process variables, as well as a second model to account for the correlation between this measured process data and device performance metrics. The availability of these models enables the computation of the joint probability density function required for predicting performance using the Jacobian transformation method. The resulting density function can then be numerically integrated to determine parametric yield. Since they have demonstrated the capability of highly accurate function approximation and mapping of complex, nonlinear data sets, neural networks are proposed as the preferred tool for generating the models described above. In applying this methodology to MQW APD's, it is shown that using a small number of test devices with varying active diameters, barrier and well widths, and doping concentrations enables prediction of the expected performance variation of APD gain and noise in larger populations of devices. This approach compares favorably with Monte Carlo techniques and allows device yield prediction prior to high volume manufacturing in order to evaluate the impact of both design decisions and process capability     

Statistical experimental design in plasma etch modeling

The objective of this work is to obtain a comprehensive set of empirical models for plasma etch rates, uniformity, selectivity, and anisotropy. These models accurately represent the behavior of a specific piece of equipment under a wide range of etch recipes, thus making them ideal for manufacturing and diagnostic purposes. The response characteristics of a CCl₄-based plasma process used to etch doped polysilicon were examined via a 2^6-1 fractional factorial experiment followed by a Box-Wilson design. The effects of variation in RF power, pressure, electrode spacing, CCl₄ flow, He flow and O₂ flow on several output variables, including etch rate, selectivity, and process uniformity, were investigated. Etch anisotropy was also measured by scanning electron microscopy analysis on a 2^6-2 fraction of the original experiment. The screening factorial experiment was designed to isolate the most significant input parameters. Using this information as a platform from which to proceed, the subsequent phase of the experiment allowed the development of empirical models of etch behavior using response surface methodology (G. E. P. Box and N. D. Draper, 1987). The models were subsequently used to optimize the etch process     

VLSI: linking design and manufacturing

A set of computer-aided design (CAD) tools that predict the effects of various manufacturing steps along with the chip's internal dimensions is described. Called the Process Engineer's Workbench, the system predicts the chip's characteristics, their statistical distribution, and the manufacturing yield likely from any one fabrication process. The tools are even sensitive to the small random variations that increase in significance as devices shrink in size. Workbench can be used to compare its programs' predictions and those of other software tools with actual measurements of devices and processes. Some existing CAD tools are reviewed to highlight the Workbench's advantages, and the features of the latter are examined. Written in C language for a Digital Equipment VAXstation, Workbench was designed to be portable and runs on several other popular workstations. It contains two basic libraries, namely, one of device models, the other of process step models     

The Design of 4D-Printed Hygromorphs: State-of-the-Art and Future Challenges

In recent years, 4D printing has allowed the rapid development of new concepts of multifunctional/adaptive structures. The 4D printing technology makes it possible to generate new shapes and/or property-changing capabilities by combining smart materials, multiphysics stimuli, and additive manufacturing. Hygromorphs constitute a specific class of new smart materials where their properties and morphing capabilities are dependent on the surrounding humidity, which drives actuation. Although multiple efforts have been made to fabricate hygromorph demonstrators, a comprehensive design process to produce hygromorphs by multiple 4D printing techniques is not yet available. The broad aim of this review and concept paper is to i) highlight existing scientific and technology gaps in the field of 4D-printed hygromorphs, ii) identify tools existing in other research fields for filling those gaps, and iii) discuss a series of guidelines for tackling future challenges and opportunities to develop 4D-printed composite hygromorph materials and related manufacturing processes. Accordingly, this review describes the materials and additive manufacturing techniques used for hygromorph composite fabrication. Moreover, the relevant parameters that control actuation, the models selection and performance, the design methods and the actuation measurements for customized 4D-printed hygromorph materials, are discussed.     

Enhancement of process capability for strip force of tight sets of optical fiber using Taguchi’s Quality Engineering

Strip force is the key to identifying the quality of product during manufacturing tight sets of fiber. This study used Integrated computer-aided manufacturing DEFinition 0 (IDEF0) modeling to discuss detailed cladding processes of tight sets of fiber in transnational optical connector manufacturing. The results showed that, the key factor causing an instable interface connection is the extruder adjustment process. The factors causing improper strip force were analyzed through literature, practice, and gray relational analysis. The parameters design method of Taguchi’s Quality Engineering was used to determine the optimal experimental combinations for processes of tight sets of fiber. This study employed case empirical analysis to obtain a model for improving the process of strip force of tight sets of fiber, and determines the correlation factors that affect the processes of quality for tight sets of fiber. The findings indicated that, process capability index (C_PK) increased significantly, which can facilitate improvement of the product process capability and quality. The empirical results can serve as a reference for improving the product quality of the optical fiber industry.     

Control of MMST RTP: repeatability, uniformity, and integration forflexible manufacturing [ICs]

A real-time multivariable strategy is used to control the uniformity and repeatability of wafer temperature in rapid thermal processing (RTP) semiconductor device manufacturing equipment. This strategy is based on a physical model of the process where the model parameters are estimated using an experimental design procedure. The internal model control (IMC) law design methodology is used to automatically compute the lamp powers to a multizone array of concentric heating zones to achieve wafer temperature uniformity. Control actions are made in response to real-time feedback information provided by temperature sensing, via pyrometry, at multiple points across the wafer. Several modules, including model-scheduling and antiovershoot, are coordinated with IMC to achieve temperature control specifications. The control strategy, originally developed for prototype equipment at Stanford University, is analyzed via the customization, integration, and performance on eight RTP reactors at Texas Instruments conducting thirteen different thermal fabrication operations of two sub-half-micron CMOS process technologies used in the the Microelectronics Manufacturing Science and Technology (MMST) program     

Extending Fault-Based Testing to Microelectromechanical Systems

As stable fabrication processes for MicroElectroMechanical Systems (MEMS) emerge, research efforts shift towards the design of systems of increasing complexity. The ways in which testing is going to be performed for large volume complex devices embedding MEMS are not known. As in the microelectronics industry, the development of cost-effective tests for larger systems may well require test stimuli targeting actual faults, developing fault lists and fault models for realistic manufacturing defects and failure modes, and using fault simulation as a major approach for assessing testability and dependability. In this paper, we illustrate how fault-based testing can be extended to MEMS, both for bulk and surface micromachining technologies, making possible the reuse of analog testing techniques.