Layer-transfer process for silicon-on-insulator with improved manufacturability

We observe hydrogen platelet buildup in single-crystalline silicon caused by hydrogen-plasma processing. The platelets are aligned along a layer of lattice defects formed in silicon before the plasma processing. The buried-defect layer is formed by either silicon-into-silicon or argon-into-silicon implantation. We discuss the platelet nucleation, growth, and merge phenomena and discuss applicability of the plasma hydrogenation to silicon-on-insulator (SOI) wafer fabrication by layer transfer.     

基于TCAD软件的单层多晶EEPROM器件模拟分析

利用TCAD软件对单层多晶EEPROM器件特性进行了模拟分析,介绍了单层多晶EEPROM存储单元结构与原理的基础,针对TCAD软件中模拟分析单层多晶EEPROM器件特性时存在的困难,提出了一种两个MOS管外加电阻的等效模型来替代单层多晶EEPROM存储单元结构进行等效模拟.通过编程模拟了单层多晶EEPROM器件性能,模拟分析得到的特性曲线与理论曲线能较好吻合,验证了等效模型方案的可行性.     

混合信号集成电路的衬底耦合噪声分析

本文系统分析了混合信号集成电路的衬底噪声耦合的研究进展.简要分析了衬底噪声的基本机理,及其对混合信号电路的影响,在此基础上分析比较了目前已提出的几种主要的衬底耦合噪声模型.通过分析不同类型衬底内的噪声耦合,介绍了一些电路设计中的去耦方法.最后讨论了衬底耦合噪声研究的发展方向.     

针对应用选择正确的MOSFET驱动器

目前,现有的MOSFET技术和硅工艺种类繁多,达使得选择合适的MOSFET驱动器成了一个富有挑战性的过程.     

CMOS image sensor with mixed-signal processor array

We present a single-chip integration of a CMOS image sensor with an embedded flexible processing array and dedicated analog-to-digital converter. The processor array is designed to perform convolution and transformation algorithms with arbitrary kernels. It has been designed to carry out the multiplication of analog image data with given digital kernel coefficients and to add up the results. The processor array is an analog implementation of a highly parallel architecture which is scalable to any desired sensor resolution while preserving video-rate operation. A prototype implementation has been realized in a 0.6-/spl mu/m CMOS technology. Switched current technique has been applied to obtain compact and robust circuits. The prototype's sensor resolution is 64 /spl times/ 128 pixels. The processor array occupies a small chip area and consumes only a small percentage of the power (250 /spl mu/W) of the whole image sensor.     

Overlooked aspects of design for manufacturability

Three manufacturing methods are considered: manual (people do the assembly tasks), soft automation (reprogrammable robots are used), and hard automation (specially designed machine tools are used). The discussion covers: uniaxis assembly, focusing on its suitability when used with the above methods; determining the manufacturing method before design; the resultant shift of decision-making power in a company to the designer; and the importance of building on a company's strengths where choosing an assembly method     

Improving the manufacturability of electronic designs

The application of statistical circuit design techniques can prevent problems of low yield in manufacture of circuits. Statistical circuit design techniques analyze the yields of circuit designs whose underlying components exhibit random fluctuations. These techniques can help produce more robust designs by calling attention to areas where statistical variations are likely to combine in such a way as to cause circuit failure. Nonparametric boundary analysis (NBA), a technique introduced in Hewlett Packard EEsof's IC-CAP 5.0, permits yield analysis when the random fluctuations result from an arbitrary stochastic process, in addition to well-studied processes such as the Gaussian     

On the device design assessment of multigate FETs (MuGFETs) using full process and device simulation with 3D TCAD

A design evaluation is reported for multigate FETs (MuGFETs) by implementing a full process flow using a commercial three-dimensional technology CAD (TCAD) tool within the context of optimizing the device design and underlying fabrication processes. The simulation is based on and refers to the development of the SOI-based 30 nm MuGFET devices. Using our real process flow, various process simulation parameters from diffusion and activation models are first calibrated to the experimental data. Device simulations are then performed with varying fin doping, fin width, fin height, L_dd and halo implant tilt, and box thickness. For a given fin thickness and increasing fin height, the threshold voltage, off-current, delay and short channel effects (SCEs) remain approximately insensitive, while the on-current and transconductance increases approximately linearly with the increase in fin height. On the other hand drain-induced barrier lowering (DIBL), subthreshold slope (S) and off-current I_OFF are quite sensitive to the variations in fin width (at fixed fin height). We found that the lower L_dd and halo implant tilt angle (20–30°) are beneficial in reducing the SCEs and off-current. Finally, a comparison of the simulation results with electrical measurement data is presented, which shows fairly good agreement.     

A mixed-signal array processor with early vision applications

Many early vision tasks require only 6 to 8 b of precision. For these applications, a special-purpose analog circuit is often a smaller, faster, and lower power solution than a general-purpose digital processor, but the analog chips lack the programmability of digital image processors. This paper presents a programmable mixed-signal array processor which combines the programmability of a digital processor with the small area and low power of an analog circuit. Each processor cell in the array utilizes a digitally programmable analog arithmetic unit with an accuracy of 1.3%. The analog arithmetic unit utilizes a unique circuit that combines a cyclic switched-capacitor analog-to-digital converter (ADC) and digital-to-analog converter (DAC) to perform addition, subtraction, multiplication, and division, Each processor cell, fabricated in a 0.8-μm triple-metal CMOS process, operates at a speed of 0.8 MIPS, consumes 1.8 mW of power at 5 V, and uses 700 μm by 270 μm of silicon area. An array of these processor cells performed an edge detection algorithm and a subpixel resolution algorithm     

Lifetime and manufacturability of integrated power electronics

In case of battery electric cars, market data show a traditional exponential gradient of sales figures, known from other technology transitions. The worldwide installed wind and photovoltaic capacity show also an exponential gradient. Even the power density of power electronics is growing exponentially.Power electronics is a prerequisite to enable the exponential growth of power density.Requirements on power electronic packaging technologies are electric performance, thermal performance and robust design. Due to the lack of bond wires, SMD capacitors can be mounted close to semiconductors, resulting in a minimization of parasitic inductance. Thermally, the packaging technology benefits from heat spreading inside the copper leadframe and thin dielectric layers. It obtains a thermal resistance of 0.5 K/W, and there is potential to further reduce the thermal resistance by alternative dielectric material. The thermal resistance can be further reduced to at least 0.42 K/W by the construction of a double side chip cooling.A robust design can be offered by the combination of a chip copper metallization connecting to copper microvias connecting to the top copper layer, which means no difference in coefficients of thermal expansion. On the bottom side, a silver sinter layer offers a reliable connection between chip and leadframe.This paper describes production process optimizations, thermal optimization possibilities, power cycling lifetime measurements and first conductive anodic filament lifetime measurements at 1000 V DC. The outlook onto an integrated 120 A 700 V SiC MOSFET demonstrator is given.     

Analysis and application of digital spectral warping in analog and mixed-signal testing

Spectral warping is a digital signal processing transform which shifts the frequencies contained within a signal along the frequency axis. The Fourier transform coefficients of a warped signal correspond to frequency-domain 'samples' of the original signal which are unevenly spaced along the frequency axis. This property allows the technique to be efficiently used for DSP-based analog and mixed-signal testing. The analysis and application of spectral warping for test signal generation, response analysis, filter design, frequency response evaluation, etc. are discussed in this paper along with examples of the software and hardware implementation.     

彩电机壳结构CAD（Ⅷ）：第八讲彩电机壳结构静力分析

本文采用有限元方法对彩色电视机机壳进行结构静力分析。文中详述了计算倚化方案和荷载施加情况,并给出了部分分析结果。     

彩电机壳结构CAD(Ⅹ) 第十讲 彩电机壳有限元网格生成

本文详述彩电机壳有限元分析的网格生成,是彩电微机系统CEDS中结构分析子系统的一部分。     

彩电机壳结构CAD(Ⅴ) TV-HCCS系统的模块化程序设计

本文从机壳的结构分解及TV-HCCS软件模块划分两个方面介绍了系统模块化处理的情况,以及系统的显示管理,并举例说明了结构设计程序模块的具体建造方法。     

彩电机壳结构CAD(Ⅺ)——冲击锤试验中机壳的动强度计算

本文采用能量法计算冲击锤试验中机壳的动强度,其计算为彩电微机系统CEDS中结构分析子系统的一部分。     

Salicides: materials, scaling and manufacturability issues for future integrated circuits (invited)

In this paper we present an overview of the development of advanced salicide processes at Texas Instruments, addressing both Ti and Co salicides. Scaling issues, such as sheet resistance of deep sub-micron structures for Ti salicide and diode leakage on shallow junctions for Co salicide, are discussed, as well as processes developed to overcome these issues. The key material aspects controlling these variables are reviewed, such as Ti silicide phase formation and transformations and mechanisms of direct formation of C54 TiSi₂, which control sheet resistance, and silicide–silicon interface characteristics for Co salicide, impacting diode leakage. Implementation and manufacturability aspects are also discussed. We present advanced Ti and Co salicide processes with manufacturing and high yield capability demonstrated for sub-0.25 μm CMOS technologies. Process modifications that extend the applicability of these salicides to 0.1 μm CMOS are also presented.     

TCAD study on gate-all-around cylindrical (GAAC) transistor for CMOS scaling to the end of the roadmap

In this paper, we report TCAD study on gate-all-around cylindrical (GAAC) transistor for sub-10-nm scaling. The GAAC transistor device physics, TCAD simulation, and proposed fabrication procedure have been discussed. Among all other novel fin field effect transistor (FinFET) devices, the gate-all-around cylindrical device can be particularly used for reducing the problems of conventional multi-gate FinFET, improving device performance, and scaling-down capabilities. With gate-all-around cylindrical architecture, the transistor is controlled essentially by infinite number of gates surrounding the entire cylinder-shaped channel. Electrical integrity within the channel is improved by reducing the leakage current due to the non-symmetrical field accumulation such as the corner effect. Our proposed fabrication procedure for making devices having the gate-all-around cylindrical (GAAC) device architecture is also discussed.     

CAD modeling of coplanar waveguide (CPW) air-bridges

In this paper, first, a comprehensive review of existing models for the coplanar waveguide (CPW) air-bridge is presented. Then, a new CAD model is proposed, in which the bridge is modeled as a small section of a microshield line, whose characteristics are obtained using the conformal mapping technique. Our results are in good agreement with full-wave results.     

SOC混合信号测试难题的解决策略

缺乏可控制性和可观察性是SOC嵌入式内核测试电路最难解决的问题.本文提出在SOC嵌入式内核测试电路中引入DFT和BIST方法.介绍了IEEE1149.4混合信号测试总线及其应用特点,讨论运用重配置的DFT方法和测试点插入的DFT方法来增强混合信号系统的可控制性和可观察性.阐述ADC/DAC与PLL两种电路的BIST技术在SOC嵌入式内核测试的应用.为解决SOC混合信号测试难题提供一种有效的方法.