基于FPGA的TPC编译码器设计与实现

介绍了Turbo乘积码(TPC)的编译码原理,并对TPC码字结构进行了分析。在高斯信道下给出了子码为扩展汉明码(64,57,4)的TPC码的误码率性能,并对编译码器的模块设计进行说明,同时采用Altera公司的EP2S180芯片完成了方案验证。结果表明,在系统时钟为100 MHz的情况下,译码时延约为44 μs,可较好地满足实时性需求。     

Turbo乘积码的两种迭代译码器的比较

提出了Turbo乘积码的并行迭代译码原理,对比分析了一种新的并行迭代译码器和传统的串行译码器,给出了以扩展汉明码(32,26,4)、(64,57,4)为子码的二维Turbo乘积码(32,26,4)。、(64,57,4)。在通过两种不同的译码器时的仿真结果。仿真结果表明,采取并行迭代译码器,在保持同样的译码性能的同时降低了译码延时。     

DTMB标准中BCH译码算法及其FPGA的实现

首先证明了DTMB标准中采用的BCH码是纠错能力为1的循环汉明码,并基于此提出了适用于该BCH码的译码算法,及其串行和并行两种FPGA实现电路。考虑到该BCH码缩短码的特性,通过修改差错检测电路,使其译码时延缩短34%。实现结果表明,译码器译码正确无误,FPGA资源占用极少。串行译码器总时延为762个时钟周期,最大工作时钟频率可达357MHz。并行译码器总时延仅为77个时钟周期,最大工作时钟频率可达276MHz。     

DTMB系统中BCH译码算法及其FPGA实现

首先证明了DTMB系统中采用的BCH码是纠错能力为1的循环汉明码,并基于此提出了适用于该BCH码的译码算法,及其串行和并行两种FPGA实现电路.考虑到该BCH缩短码的特性,通过修改差错检测电路,使其译码时延缩短34％.实验结果表明,译码器译码正确无误,FPGA资源占用极少.串行译码器总时延为762个时钟周期,最大工作时钟频率可达357 MHz.并行译码器总时延仅为77个时钟周期,最大工作时钟频率可达276 MHz.     

BCH-Turbo编码的设计与仿真实现

本文针对Turbo码在低信噪比下迭代次数多、译码时延长问题,在分析了Turbo码的编译码原理和算法基础上,提出一种可以有效降低平均迭代次数、减少译码时延的基于BCH迭代停止准则的Turbo码迭代译码的设计方案。本方案采用BCH码作为Turbo迭代译码的停止准则。并对每一个分量译码器结果都进行判断。可提前停止迭代。通过Monte Carlo仿真表明在AWGN信道下,误码率有所降低。Turbo码译码的平均迭代次数与交叉熵准则相比有明显下降。本文还分析了BCH码编码效率和分组长度的选择对系统性能的影响。     

BCH-Turbo码的设计与仿真实现

本文针对Turbo码在低信噪比下迭代次数多、译码时延长问题,在分析了Turbo码的编译码原理和算法基础上,提出一种可以有效降低平均迭代次数、减少译码时延的基于BCH迭代停止准则的Turbo码迭代译码的设计方案.本方案采用BCH码作为Turbo迭代译码的停止准则,并对每一个分量译码器结果都进行判断,可提前停止迭代.通过Monte Carlo仿真表明在AWGN信道下,误码率有所降低,Turbo码译码的平均迭代次数与交叉熵准则相比有明显下降.本文还分析了BCH码编码效率和分组长度的选择对系统性能的影响.     

(25,20)线性分组编译码器设计及其FPGA实现

随着通信速率的提高,有噪信道的可靠通信通过信道编码来实现。文中设计的(25,20)线性分组编译码器结合汉明码能纠正一位错误且具有编码效率较高、译码电路简单、译码延时小等优点。分析伴随式与错误图样的对应关系,采用并行处理的方式,使用硬件描述语言VHDL在Xilinx公司的Vivado 2016.1环境下编程实现。通过ModelSim仿真平台验证,降低了实现的复杂度。在工程实践中将编译码器加入某实测通信系统,实现了在Artix-7系列xc7z030fbg676-1的芯片上占用较少的硬件资源实现(25,20)线性分组编译码,提高系统传输的可靠性,验证了该设计的优良性能。     

跳频系统下Turbo编译码器的设计

在介绍Turbo码编译码原理基础上,针对特定跳频系统,设计了一种Turbo编译码方案。详细论述了该方案中编译码器的设计、建模和仿真过程。该方案中采用MAX-LOG-MAP的迭代译码算法,仿真验证了译码器采用6次迭代可以在保证抗干扰性能的前提下,面向硬件实现计算量适中。因此,该方法具有一定的工程应用价值。     

一种改进的Turbo码结构设计及DSP实现

针对传统Turbo码在高码率场景下的错误平层问题,以及通信数据链项目中更大的码率范围需求,研究了增强型Turbo码方案和并行译码算法。采用咬尾码结构解决了译码错误平层问题,设计了更低码率的编译码器结构,以满足更低的码率范围,并取得了0.4～0.6 dB的误码率（Bit Error Ratio,BER）性能提升。最后结合并行译码算法和数字信号处理器（Digital Signal Processor,DSP）(TMS320C668)优化技术,对译码器的定点实现进行了优化,使译码计算取得了2.6～3.7的加速比。仿真和项目验证表明该设计具有良好的性能和较高的工程实践价值。     

基于FPGA的LDPC码编译码器联合设计

该文通过对低密度校验(LDPC)码的编译码过程进行分析,提出了一种基于FPGA的LDPC码编译码器联合设计方法,该方法使编码器和译码器共用同一校验计算电路和复用相同的RAM存储块,有效减少了硬件资源的消耗量。该方法适合于采用校验矩阵进行编码和译码的情况,不仅适用于全并行的编译码器结构,同时也适用于目前广泛采用的部分并行结构,且能够使用和积、最小和等多种译码算法。采用该方法对两组不同的LDPC码进行部分并行结构的编译码器联合设计,在Xilinx XC4VLX80 FPGA上的实现结果表明,设计得到的编码器和译码器可并行工作,且仅占用略多于单个译码器的硬件资源,提出的设计方法能够在不降低吞吐量的同时有效减少系统对硬件资源的需求。     

A Subthreshold PMOS Analog Cortex Decoder for the (8, 4, 4) Hamming Code

This paper presents a method for decoding high minimal distance (d_min) short codes, termed Cortex codes. These codes are systematic block codes of rate 1/2 and can have higher d_min than turbo codes. Despite this characteristic, these codes have been impossible to decode with good performance because, to reach high d_min, several encoding stages are connected through interleavers. This generates a large number of hidden variables and increases the complexity of the scheduling and initialization. However, the structure of the encoder is well suited for analog decoding. A proof‐of‐concept Cortex decoder for the (8, 4, 4) Hamming code is implemented in subthreshold 0.25‐μm CMOS. It outperforms an equivalent LDPC‐like decoder by 1 dB at BER=10^?5 and is 44 percent smaller and consumes 28 percent less energy per decoded bit.     

可调串行光码分多址编码器/解码器

分析了目前存在的编解码器的优缺点 ,提出一种可调串行全光码分多址 (CDMA)编解码器。根据其工作原理 ,推导其最佳设计参数 ,并进行功能仿真 ,验证了该编解码器的正确性及可实现串行编解码、地址码可调、编解码器一体、既可用于同步码分多址又可用于异步码分多址通信等特点。     

Discrete Hartley transform in error control coding

A new class of real-valued linear code obtained by using the discrete Hartley transform (DHT) is defined. The authors have derived the limitation on the choice of parity frequencies so as to define DHT codes with the cyclic-shift property. Then, by introducing the well-established encoding/decoding algorithm for cyclic codes in error control coding, they have constructed the encoder/decoder for the DHT cyclic codes     

802.11b中卷积码和Viterbi译码的FPGA设计实现

卷积码是一种重要的信道纠错编码方式,其纠错性能通常优于分组码,目前(2,1,6)卷积码已广泛应用于无线通信系统中,Viterbi译码算法能最大限度地发挥卷积码的纠错性能。阐述了802.11b中卷积码的编码及其Viterbi译码方法,给出了编译码器的设计方法,并利用Verilog HDL硬件描述语言完成编译码器的FPGA实现。使用逻辑分析仪,在EP2C5T144C8芯片上完成了编译码器的硬件调试。     

High-rate serially concatenated coding with extended Hamming codes

This letter shows that concatenation of extended Hamming codes with rate-1 recursive convolutional encoder and iterative decoding achieves near Shannon limit performance for very high rate coding. These codes can be decoded efficiently, and have large adaptability in code lengths and code rates.     

Viterbi decoding of the (63, 57) Hamming code-implementation andperformance results

Use of the Viterbi decoder to decode the (63, 57) Hamming code is considered, Implementation and performance of systematic and nonsystematic codes are addressed. It is shown that a Viterbi decoder for the constraint length seven, rate-½ convolutional code can be used to decode both systematic and nonsystematic (63, 57) Hamming codes, but an additional step is needed to complete the decoding of the systematic code. Bounds and simulation results for postdecoding bit-error probability are given and it is shown that the systematic code performs 0.4 dB better than the nonsystematic code. A heuristic explanation is provided     

Variable shortened-and-punctured Reed-Solomon codes for packet loss protection

Techniques using Reed-Solomon (RS) codes to recover lost packets in digital video/audio broadcasting and packet switched network communications are reviewed. Usually, different RS codes and their corresponding encoders/decoders are designed and utilized to meet different requirements for different systems and applications. We incorporate these techniques into a variable RS code and present encoding and decoding algorithms suitable for the variable RS code. A mother RS code can be used to produce a variety of RS codes and the same encoder/decoder can be used for all the derivative codes, with adding/detecting zeros, removing some parity symbols and adding erasures. A VLSI implementation for erasure decoding of the variable RS code is described and the achievable performance is quantitatively analyzed. A typical example shows that the signal processing speed is up to 2.5 Gbits/second and the processing delay is less than one millisecond, when integrating the decoder on a single chip. Therefore, the proposed algorithm and the encoder/decoder can universally be utilized for different applications with various requirements, such as transmission data rate, packet length, packet loss protection capacity, as well as layered protection and adaptive redundancy protection in DVB/DAB, Internet and mobile Internet communications.     

Nonlinear Codes: The Product Construction

The standard product construction is discussed with respect to nonlinear codes. Thus, so-called nonlinear product codes are obtained that are better than linear product codes of similar length and code rate, and at the same time, amenable for encoding/decoding. On the other hand, it is shown that certain notorious nonlinear codes have an augmented product construction, namely, they can be constructed by taking the union of a product code and certain of its cosets. The binary Hamming codes are shown to have similar construction. A simple two-stage decoder is proposed for nonlinear product (NLP) codes. The decoder is shown to be a bounded-distance (BD) information decoder that is the nonlinear equivalent of the BD decoder employed for linear codes. A list-based maximum-likelihood decoder is also discussed.