Extraction of the Effective Mobility of $ hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ MOSFETs

The extraction of the effective mobility on $hbox{In}_{0.53} hbox{Ga}_{0.47}hbox{As}$ metal–oxide–semiconductor field-effect transistors (MOSFETs) is studied and shown to be greater than 3600 $hbox{cm}^{2}/hbox{V} cdot hbox{s}$. The removal of $C_{rm it}$ response in the split $C$–$V$ measurement of these devices is crucial to the accurate analysis of these devices. Low-temperature split $C$–$V$ can be used to freeze out the $D_{rm it}$ response to the ac signal but maintain its effect on the free carrier density through the substrate potential. Simulations that match this low-temperature data can then be “warmed up” to room temperature and an accurate measure of $Q_{rm inv}$ is achieved. These results confirm the fundamental performance advantages of $hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ MOSFETs.      

Lattice-Mismatched $hbox{In}_{0.4}hbox{Ga}_{0.6} hbox{As}$ Source/Drain Stressors With In Situ Doping for Strained $hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ Channel n-MOSFETs

We report the first demonstration of a strained $hbox{In}_{0.53} hbox{Ga}_{0.47}hbox{As}$ channel n-MOSFET featuring in situ doped $hbox{In}_{0.4}hbox{Ga}_{0.6}hbox{As}$ source/drain (S/D) regions. The in situ silicondoped $hbox{In}_{0.4}hbox{Ga}_{0.6}hbox{As}$ S/D was formed by a recess etch and a selective epitaxy of $hbox{In}_{0.4}hbox{Ga}_{0.6}hbox{As}$ in the S/D by metal–organic chemical vapor deposition. A lattice mismatch of $sim$0.9% between $ hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ and $hbox{In}_{0.4} hbox{Ga}_{0.6}hbox{As}$ S/D gives rise to lateral tensile strain and vertical compressive strain in the $hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ channel region. In addition, the in situ Si-doping process increases the carrier concentration in the S/D regions for series-resistance reduction. Significant drive-current improvement over the control n-MOSFET with Si-implanted $hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ S/D regions was achieved. This is attributed to both the strain-induced band-structure modification in the channel that reduces the effective electron mass along the transport direction and the reduction in the S/D series resistance.      

35-nm Zigzag T-Gate $hbox{In}_{0.52}hbox{Al}_{0.48} hbox{As/In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ Metamorphic GaAs HEMTs With an Ultrahigh $f_{max}$ of 520 GHz

Metamorphic GaAs high electron mobility transistors (mHEMTs) with the highest-f _max reported to date are presented here. The 35-nm zigzag T-gate In_0.52Al_0.48As/In_0.53Ga_0.47As metamorphic GaAs HEMTs show f _maxof 520 GHz, f _T of 440 GHz, and maximum transconductance (g _m) of 1100 mS/mm at a drain current of 333 mA/mm. The combinations of f _max and f _T are the highest data yet reported for mHEMTs. These devices are promising candidates for aggressively scaled sub-35-nm T-gate mHEMTs.     

Fabrication of Self-Aligned Enhancement-Mode $ hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ MOSFETs With $ hbox{TaN/HfO}_{2}hbox{/AlN}$ Gate Stack

In this letter, we report the fabrication and characterization of self-aligned inversion-type enhancement-mode In_0.53Ga_0.47As metal-oxide-semiconductor field-effect transistors (MOSFETs). The In_0.53Ga_0.47As surface was passivated by atomic layer deposition of a 2.5-nm-thick AIN interfacial layer. In_0.53Ga_0.47As MOS capacitors showed an excellent frequency dispersion behavior. A maximum drive current of 18.5 muA/mum was obtained at a gate overdrive of 2 V for a MOSFET device with a gate length of 20 mum. An I_on/_off ratio of 104, a positive threshold voltage of 0.15 V, and a subthreshold slope of ~165 mV/dec were extracted from the transfer characteristics. The interface-trap density is estimated to be ~7-8 times 10¹² cm^-2 ldr eV^-1 from the subthreshold characteristics of the MOSFET.     

Impacts of $hbox{N}_{2}$ and $hbox{NH}_{3}$ Plasma Surface Treatments on High-Performance LTPS-TFT With High-$kappa$ Gate Dielectric

Low-temperature polycrystalline-silicon thin-film transistors (LTPS-TFTs) with high- $kappa$ gate dielectrics and plasma surface treatments are demonstrated for the first time. Significant field-effect mobility $mu_{rm FE}$ improvements of $sim$86.0% and 112.5% are observed for LTPS-TFTs with $hbox{HfO}_{2}$ gate dielectric after $hbox{N}_{2}$ and $ hbox{NH}_{3}$ plasma surface treatments, respectively. In addition, the $hbox{N}_{2}$ and $ hbox{NH}_{3}$ plasma surface treatments can also reduce surface roughness scattering to enhance the field-effect mobility $mu_{rm FE}$ at high gate bias voltage $V_{G}$, resulting in 217.0% and 219.6% improvements in driving current, respectively. As a result, high-performance LTPS-TFT with low threshold voltage $V_{rm TH} sim hbox{0.33} hbox{V}$, excellent subthreshold swing S.S. $sim$0.156 V/decade, and high field-effect mobility $mu_{rm FE} sim hbox{62.02} hbox{cm}^{2}/hbox{V} cdot hbox{s}$ would be suitable for the application of system-on-panel.      

$f_{T}$ and $f_{rm MAX}$ of 47 and 81 GHz , Respectively, on N-Polar GaN/AlN MIS-HEMT

In this letter, we demonstrate the record small-signal performance from N-polar GaN-based metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs) by using a GaN spacer structure with an AlN barrier to reduce alloy scattering. High Si doping in GaN without excessive surface roughening has been achieved using a digital doping scheme. A low ohmic contact resistance of 0.16 $Omega cdot hbox{mm}$ was measured. Submicrometer gates were fabricated by electron-beam lithography using a triple-layer resist process. $f_{T}$ and $f_{rm MAX}$ of 47 and 81 GHz, respectively, were obtained for the 150-nm-gate-length device. Further analysis has been done to understand the effect of access resistance on the high-frequency performance, defining a pathway for getting a higher gain and thus achieving a better high-frequency performance from N-polar GaN-based HEMTs.      

Fabrication of 2700-V 12-$hbox{m}Omega cdot hbox{cm}^{2}$ Non Ion-Implanted 4H-SiC BJTs With Common-Emitter Current Gain of 50

High-voltage blocking (2.7-kV) implantation-free SiC bipolar junction transistors with low ON-state resistance (12 mOmegaldrcm²) and high common-emitter current gain of 50 have been fabricated. A graded-base doping was implemented to provide a low-resistive ohmic contact to the epitaxial base. This design features a fully depleted base layer close to the breakdown voltage providing an efficient epitaxial JTE without ion implantation. Eliminating all ion implantation steps in this approach is beneficial for avoiding high-temperature dopant activation annealing and for avoiding generation of lifetime-killing defects that reduce the current gain.     

12 GHz $F_{rm MAX}$ GaN/AlN/AlGaN Nanowire MISFET

GaN/AlN/AlGaN/GaN nanowire metal–insulator–semiconductor field-effect transistors (MISFETs) have been fabricated for the first time with submicrometer gate lengths. Their microwave performances were investigated. An intrinsic current-gain cutoff frequency $(F_{T})$ of 5 GHz as well as an intrinsic maximum available gain $(F_{rm MAX})$ cutoff frequency of 12 GHz have been obtained for the first time and associated with a gate length of 0.5 $muhbox{m}$. These results show the great potentiality of GaN-based nanowire FETs for microwave applications.      

A Monte Carlo Study of $hbox{Hg}_{0.7}hbox{Cd}_{0.3}hbox{Te}$ e-APD

A simple Monte Carlo model is developed for understanding the multiplication process in HgCdTe infrared avalanche photodiodes and the impact of physical and technological parameters. A good agreement is achieved between simulations and experimental measurements of gain and excess noise factor. In both cases, an exponential gain and extremely low noise—$F sim hbox{1}$ for multiplication gains up to 1000—were observed on 5.1-$muhbox{m}$ cutoff devices at 77 K, indicative of a single carrier impact ionization. A comparison study is presented to explain the effect of different combinations of scattering processes on the avalanche phenomenon in HgCdTe.      

First Insight Into the Lifetime Acceleration Model of High-$k$ $hbox{ZrO}_{2}/hbox{SiO}_{2}/hbox{ZrO}_{2}$ Stacks for Advanced DRAM Technology Nodes

Long-term reliability results over six orders of magnitude in time are presented showing that the voltage acceleration model for $hbox{ZrO}_{2}/hbox{SiO}_{2}/hbox{ZrO}_{2}$ exhibits an exponential dependence with voltage, down to 2 V. The voltage acceleration parameter $gamma$ is between 10 and 15 $hbox{V}^{-1}$, depending on the biasing polarity. Soft-breakdown behavior (SILC) is evident prior to the onset of hard breakdown as a result of barrier lowering or charge accumulation in the high- $k$ film. Under ac stress conditions, this SILC branch is lowered in magnitude, translating to a gain in lifetime to breakdown.      

Nonvolatile-Memory Characteristics of $hbox{AlO}^{-}$ -Implanted $hbox{Al}_{2}hbox{O}_{3}$

The nonvolatile-memory (NVM) characteristics of $hbox{AlO}^{-}$ -implanted $hbox{Al}_{2}hbox{O}_{3}$ structures are reported and shown to exhibit promising behaviors, including fast program/erase speeds and high-temperature data retention. Photoconductivity spectra show the existence of two dominant trap levels, located at around 2 and 4 eV below the conduction band minimum of $hbox{Al}_{2}hbox{O}_{3}$, and our calculations show that these levels are likely attributed to the defects in the $hbox{Al}_{2}hbox{O}_{3}$, such as the Al–O divacancy. The relative concentrations of these defects vary with the implant fluence and are shown to explain the NVM characteristics of the samples irradiated to different fluences.      

Gate Influence on the Layout Sensitivity of $ hbox{Si}_{1 - x}hbox{Ge}_{x} hbox{S/D}$ and $hbox{Si}_{1 - y}hbox{C}_{y} hbox{S/D}$ Transistors Including an Analytical Model

We present a simulation study on the effect of the gate module on the channel stress in Si_1-xGe_x and Si_1-yC_y S/D MOS transistors. Stiff gate materials, such as titanium nitride, lead to a decreased channel stress, while a replacement-gate scheme allows the increase of the effectiveness of the Si_1-xGe_x and Si_1-yC_y S/D techniques significantly, independent of the gate material used. The drawback of using a replacement gate is that the channel stress becomes more sensitive to layout variations. In terms of effect on Si_1-xGe_x/Si_1-yC_y S/D stress generation, using a thin metal gate capped by polysilicon is similar to a full metal gate if the thin metal gate thickness exceeds 10 nm. Even metal gates as thin as 1 nm have a clear influence on the stress generation by Si_1-xGe_x/Si_1-yC_y S/D. Removing and redepositing the polysilicon layer while leaving the underlying metal gate unchanged increases the stress, although not to the same extent as for complete gate removal. A simple analytical model that estimates the stress in nested short-channel Si_1-xGe_x and Si_1-yC_y S/D transistors is presented. This model includes the effect of germanium/carbon concentration, active-area length, as well as the effect of gate length and the Young's modulus of the gate. Good qualitative agreement with 2-D finite element modeling is demonstrated.     

A Comparative NBTI Study of $hbox{HfO}_{2}$, $hbox{HfSiO}_{x}$, and SiON p-MOSFETs Using UF-OTF $I_{rm DLIN}$ Technique

The time, temperature, and oxide-field dependence of negative-bias temperature instability is studied in $hbox{HfO}_{2}/hbox{TiN}$, $ hbox{HfSiO}_{x}/hbox{TiN}$, and SiON/poly-Si p-MOSFETs using ultrafast on-the-fly $I_{rm DLIN}$ technique capable of providing measured degradation from very short (approximately microseconds) to long stress time. Similar to rapid thermal nitrided oxide (RTNO) SiON, $hbox{HfO}_{2}$ devices show very high temperature-independent degradation at short (submilliseconds) stress time, not observed for plasma nitrided oxide (PNO) SiON and $hbox{HfSiO}_{x}$ devices. $hbox{HfSiO}_{x}$ shows lower overall degradation, higher long-time power-law exponent, field acceleration, and temperature activation as compared to $hbox{HfO}_{2}$, which are similar to the differences between PNO and RTNO SiON devices, respectively. The difference between $ hbox{HfSiO}_{x}$ and $hbox{HfO}_{2}$ can be attributed to differences in N density in the $hbox{SiO}_{2}$ IL of these devices.      

Negative Differential Resistance in Buried-Channel $hbox{Ge}_{x} hbox{C}_{1 - x}$ pMOSFETs

We study the device characteristics of Si-capped $hbox{Ge}_{x}hbox{C}_{1 - x}$ pMOSFETs from room temperature down to 77 K. The output characteristics of these devices reveal a negative differential resistance (NDR) at temperatures below 150 K. Our measurements indicate a higher effective carrier mobility in the buried-channel $hbox{Ge}_{x}hbox{C}_{1 - x}$ with respect to the Si-reference sample, which suggests that the observed NDR is due to real-space transfer of hot holes from the higher mobility $hbox{Ge}_{x}hbox{C}_{1 - x}$ channel layer into the lower mobility Si cap layer.      

Low Turn-On Voltage and High-Current $hbox{InP}/ hbox{In}_{0.37}hbox{Ga}_{0.63}hbox{As}_{0.89}hbox{Sb}_{0.11}/hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ Double Heterojunction Bipolar Transistors

We report on the dc and microwave characteristics of an $ hbox{InP/In}_{0.37}hbox{Ga}_{0.63}hbox{As}_{0.89}hbox{Sb}_{0.11}/hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ double heterojunction bipolar transistor grown by solid-source molecular beam epitaxy. The pseudomorphic $hbox{In}_{0.37}hbox{Ga}_{0.63}hbox{As}_{0.89}hbox{Sb}_{0.11}$ base reduces the conduction band offset $Delta E_{C}$ at the emitter/base junction and the base band gap, which leads to a very low $V_{rm BE}$ turn-on voltage of 0.35 V at 1 $hbox{A/cm}^{2}$ . A current gain of 125 and a peak $f_{T}$ of 238 GHz have been obtained on the devices with an emitter size of $hbox{1}times hbox{10} muhbox{m}^{2}$, suggesting that a high collector average velocity and a high current capability are achieved due to the type-II lineup at the InGaAsSb/InGaAs base/collector junction.      

AlGaN/GaN MOS-HEMT With $hbox{HfO}_{2}$ Dielectric and $hbox{Al}_{2}hbox{O}_{3}$ Interfacial Passivation Layer Grown by Atomic Layer Deposition

We have developed a novel AlGaN/GaN metal-oxide-semiconductor high-electron mobility transistor using a stack gate HfO₂/Al₂O₃ structure grown by atomic layer deposition. The stack gate consists of a thin HfO₂ (30-A) gate dielectric and a thin Al₂O₃ (20- A) interfacial passivation layer (IPL). For the 50-A stack gate, no measurable C-V hysteresis and a smaller threshold voltage shift were observed, indicating that a high-quality interface can be achieved using a Al₂O₃ IPL on an AlGaN substrate. Good surface passivation effects of the Al₂O₃ IPL have also been confirmed by pulsed gate measurements. Devices with 1- mum gate lengths exhibit a cutoff frequency (fT) of 12 GHz and a maximum frequency of oscillation (f _MAX) of 34 GHz, as well as a maximum drain current of 800 mA/mm and a peak transconductance of 150 mS/mm, whereas the gate leakage current is at least six orders of magnitude lower than that of the reference high-electron mobility transistors at a positive gate bias.     

Scaling Properties of $hbox{Ge}$ –$hbox{Si}_{x}hbox{Ge}_{1 - x}$ Core–Shell Nanowire Field-Effect Transistors

We demonstrate the fabrication of high-performance $hbox{Ge}$ –$hbox{Si}_{x}hbox{Ge}_{1 - x}$ core–shell nanowire (NW) field-effect transistors with highly doped source (S) and drain (D) and systematically investigate their scaling properties. Highly doped S and D regions are realized by low-energy boron implantation, which enables efficient carrier injection with a contact resistance much lower than the NW resistance. We extract key device parameters, such as intrinsic channel resistance, carrier mobility, effective channel length, and external contact resistance, as well as benchmark the device switching speed and on/off current ratio.      

Performance of $hbox{YBa}_{2}hbox{Cu}_{3} hbox{O}_{x}$ Tapes With Different Structures Under AC Overcurrent Conditions

The voltage and temperature of $hbox{YBa}_{2}hbox{Cu}_{3}hbox{O}_{x}$ (YBCO) tapes with different structures were measured at alternating-current overcurrent conditions in liquid nitrogen. A safety temperature limit of the tapes with different structure was obtained based on the measured critical-current degradation data of the YBCO tapes. According to heat conduction model, the electrical and thermal performances of YBCO tapes were analyzed for tapes with different stabilizers. The comparison was presented for simulation and test data. The results are helpful for the design of superconducting electrical equipment.      

High-Performance $hbox{In}_{0.7}hbox{Ga}_{0.3}hbox{As}$ -Channel MOSFETs With High-$kappa$ Gate Dielectrics and $alpha$-Si Passivation

Long and short buried-channel $hbox{In}_{0.7}hbox{Ga}_{0.3}hbox{As}$ MOSFETs with and without $alpha$-Si passivation are demonstrated. Devices with $alpha$-Si passivation show much higher transconductance and an effective peak mobility of 3810 $hbox{cm}^{2}/ hbox{V} cdot hbox{s}$. Short-channel MOSFETs with a gate length of 160 nm display a current of 825 $muhbox{A}/muhbox{m}$ at $V_{g} - V_{t} = hbox{1.6} hbox{V}$ and peak transconductance of 715 $muhbox{S}/muhbox{m}$. In addition, the virtual source velocity extracted from the short-channel devices is 1.4–1.7 times higher than that of Si MOSFETs. These results indicate that the high-performance $hbox{In}_{0.7}hbox{Ga}_{0.3} hbox{As}$-channel MOSFETs passivated by an $alpha$ -Si layer are promising candidates for advanced post-Si CMOS applications.