Highly reliable and low-power magnetic full-adder designs for nanoscale technologies

The MTJ-based circuits have been considered as a candidate for next generation digital integrated circuits thanks to their attractive features such as nonvolatility, low leakage current, high endurance, and CMOS integration compatibility. However, incurred energy and delay by reconfiguration of their employed conventional MTJs limit their application. Besides, the issue of read-disturbance is another challenge in such MTJ-based circuit designs. In this article, a new magnetic-based full-adder (MFA) circuit based on a new three-terminal two-in-one magnetic tunnel junction (TIO-MTJ) cell is proposed. Comparing with the previous MFA circuits, the proposed circuit offers a lower energy for the write operation and also a disturbance-free reading. Two improved structures based on the proposed MFA are also suggested to obtain the advantages of nonvolatility for the power-gating architectures and also radiation hardening for the radiation harsh environments.     

基于探索式分区和测试向量生成的硬件木马检测方法

本文提出基于分区和最优测试向量生成的硬件木马检测方法.首先,采用基于扫描细胞分布的分区算法将电路划分为多个区域.然后,提出测试向量重组算法,对各区域依据其自身结构生成近似最优的测试向量.最后,进行分区激活和功耗分析以检测木马,并采用信号校正技术消减制造变异和噪声的影响.优点是成倍提高了检测精度,克服了制造变异的影响,解决了面对大电路的扩展性问题,并可以定位木马.在基准电路上的验证实验表明检测性能有较大的提升.     

Preface: Special Issue on Large Scale Integration

The interests of the solid-state circuits community have been focused on integrated circuits during the past several years. Through a potent combination of technological and economic factors, the development of digital integrated circuits has progressed at a particularly rapid rate during this petiod. At present, large scale integration represents the region of singular importance in the field of digital integrated circuits. Typically, large scale integration consists of the combination of a multiplicity of circuit elements within a basic cell and the further combination of a multiplicity of cells in a monolithic structure to form a highly complex integrated circuit or an integrated equipment component. A most significant feature of an integrated equipment component is the uniquely intimate interdependence of its material, device, circuit, and system-design considerations. Recognizing this interdependence, the central position of large scale integration in electronics and its salient importance in solid-state circuits, the purpose of this issue is to act as an expose of advanced work being done in this field.     

Precision measurement technique of integrated MOS capacitor mismatching using a simple on-chip circuit

A precision measurement technique of the capacitor mismatchings of integrated circuits has been required, that is insensitive to parasitic capacitors on the chip, stray capacitors in measurement circuits, and external noises. A new ac measurement technique is developed here that uses an on-chip source-follower circuit and a simple algorithm. The source-follower circuit lowers the output impedance and thereby excludes the effects of external noises and stray capacitors in measurement circuits. In the present technique, capacitively divided ac voltage after the bandpass filter is measured in two steps by exchanging the terminals of the serial capacitors using external switches. Capacitor mismatching, defined by the relative capacitance toleranceDelta C/C, is derived as the ratio of the difference between the two measured voltages to their average. This derivation significantly reduces errors arising from parasitic capacitors on the chip, the nonlinearity of the source-follower circuit, and the pulse wave that can give the gate bias voltage of the source-follower transistor. The measurement error is estimated to be, in the worst case, 0.1 percent ofDelta C/C.     

Supply-current analysis (scan) as a screen for bipolar integrated circuits

A novel technique utilising the analysis of supply-current variations is proposed as a screen for digital integrated circuits. The application of the method to a simple m.s.i. circuit is used to demonstrate its capability of indicating the presence of flaws at internal circuit nodes.     

Statistical methods for the estimation of process variation effects on circuit operation

In this paper, a technology computer-aided design (TCAD) driven method for accurate prediction of the performance spread of integrated circuits due to process variations is presented. The methodology starts with the development of the nominal process recipe and process simulators are calibrated to an existing process to obtain nominal device characteristics. After determining nominal process parameters, their variations are introduced followed by screening experiments to determine the relative effects of given process variations on the input-output delay and the average power dissipation in a circuit. Response surface models (RSMs) are then generated based on critical process factors identified. Process parameter optimization is performed using these RSM models to tune the mean circuit performance and to improve the yield. This methodology is demonstrated on a 33-stage ring oscillator manufactured with a CMOS design flow. The proposed methodology maps the process domain to design space, and plays a key role in design for manufacturability (DFM) to quantify direct impact of the process variations on circuits.     

Noise in interconecction lines for submicrometer CMOS integrated circuits

The growing use of high performance portable systems is the main driving force for the significant advance in the technology of VLSI-CMOS integrated circuits. This advance has been carried out through scaling the transistor and interconnection sizes. However, as the transistor's size and interconnections are getting smaller, the signal integrity is becoming a critical issue. Therefore it is required to develop noise tolerant design circuit techniques in order to enhance the noise tolerance. In addition, these techniques should have a minimum impact on the circuit performance. In this paper, the noise immunity of dynamic logical circuits as the technology scales down is analyzed by using a reliable scaling scenario, and a new noise tolerant design technique is proposed. Prototype circuits implementing the proposed technique have been designed and fabricated. A one-bit carry look-ahead adder was designed using 0.35 mm CMOS-AMS technology. The experimental results show that the design technique here presented, results in an improvement of the ANTE by a factor of 3.4X when compared with the conventional TSPC, and an improvement by a factor of 1.7X when compared with the best noise tolerant technique currently published.     

Analog implementation of radix-2, 16-FFT processor for OFDM receivers: non-linearity behaviours and system performance analysis

Analog implementations of decoders have been widely studied by considering circuit complexity, as well as power and speed, and their integration with other analog blocks is an extension of analog decoding research. In the front-end blocks of orthogonal frequency-division multiplexing (OFDM) systems, combination of an analog fast Fourier transform (FFT) with an analog decoder is suitable. In this article, the implementation of a 16-symbol FFT processor based on analog complementary metal-oxide-semiconductor current mirrors within circuit and system levels is presented, and the FFT is implemented using a butterfly diagram, where each node is implemented using analog circuits. Implementation details include consideration of effects of transistor mismatch and inherent noises and effects of circuit non-linearity in OFDM system performance. It is shown that not only can transistor inherent noises be measured but also transistor mismatch can be applied as an input-referred noise source that can be used in system- and circuit-level studies. Simulations of a radix-2, 16-symbol FFT show that proposed circuits consume very low power, and impacts of noise, mismatch and non-linearity for each node of this processor are very small.     

工艺变化下互连线分布参数随机建模与延迟分析

随着超大规模集成电路制造进入深亚微米和超深亚微米阶段,电路制造过程中的工艺变化已经成为影响集成电路互连线传输性能的重要因素.文中引入高斯白噪声建立了互连线分布参数的随机模型,并提出基于Elmore延迟度量的工艺变化下的互连延迟估计式;通过简化工艺变化量与互连线参数之间的关系式,对延迟一阶变化量与二阶变化量进行了分析,给出一般工艺变化下互连延迟的统计特性计算方法;另,针对线宽工艺变化推导出互连延迟均值与方差的计算公式.最后通过仿真实验对工艺变化下互连线延迟分析方法及其统计特性计算公式的有效性进行了验证.     

Estimation and compensation of process-induced variations in capacitors for improved reliability in integrated circuits

This paper describes a method for the estimation of capacitor process variations in integrated circuits and for the subsequent compensation of such variations through a calibration scheme that exploits a variable capacitor bank. An architecture for the calibration circuit is proposed, and various problems that arise during implementation are discussed. The design consists of an oscillator whose output frequency is inversely proportional to the capacitor value and simple state machine for measurement of capacitor process variations. The design of optimum capacitor bank is described together with the adequate tuning plan. The circuit is fabricated and verified in 130 nm RF CMOS process and can be easily scaled to sub-100-nm technologies.     

Uniplanar MMIC Hybrids--A Proposed New MMIC Structure

A new "uniplanar" circuit configuration for monolithic microwave integrated circuits (MMIC's) has been proposed. It uses a combination of coplanar waveguides and slotlines on one side of the substrate. The key components for the uniplanar structure are air bridges, which provide T junctions and transitions from coplanar waveguides to slotlines or vice versa. Novel hybrid circuits such as a magic T and a branch-line coupler have been fabricated and tested at K-band, and good performance has been achieved. This new circuit configuration is promising for applications in other microwave circuits.     

Verification of CDM circuit simulation using an ESD evaluation circuit

In this work, the capability of circuit simulation to predict CDM robustness of integrated circuits and to determine weak circuit elements is studied. The applicability is demonstrated for an ESD evaluation circuit designed to enable the analysis and optimization of ESD protection strategies in an early design phase during the introduction of a new technology. CDM circuit simulation is compared to the measurement results of variations of this circuit in two different package types. Failure locations are verified with physical failure analysis. The failure locations and CDM failure levels were reproduced accurately with circuit simulation for all circuit and package variations.     

Simple graphical method to determine line reflections between high-speed-logic integrated circuits

Pulse-shape variations on a line connecting two high-speed-logic integrated circuits due to reflections are determined graphically using Bergeron's theory. Different line lengths with different characteristic impedances have been tested. Reflection effects on the circuit noise immunity are studied. Theory and measurements have shown good agreement.     

Complete Stability Analysis of Multifunction MMIC Circuits

This paper describes a systematic methodology for complete stability analysis of nonlinear microwave multifunction circuits. The proposed strategy has two different stages: the stability analysis of a nominal steady-state solution and the use of continuation techniques to efficiently determine the unstable operation ranges. The stability analysis is demanding due to the multiple loops contained in the large multifunction circuit. The first step is to check the possible fulfillment of the oscillation startup conditions at different circuit nodes followed by pole-zero identification. Given the complexity of the circuit topology, a systematic technique is necessary for the selection of the observation nodes. This has been applied at both the lumped-element schematic and the layout levels. These stability analyses have been carried out at small-signal (linear) and large-signal (nonlinear) since the multifunction circuit includes a nonlinear mixer. In the case of instability, the origin of the oscillation and its characteristics are analyzed versus the critical circuit parameters through the application of continuation techniques to the steady-state oscillatory solution. Moreover, sensitivity yield analysis and variations of environmental conditions combined with the stability techniques have also been taken into account and integrated into the design cycle. The proposed systematic approach has been successfully applied to determine and correct an oscillation of a multifunction monolithic-microwave integrated-circuit converter. It has also been proven in other multifunction circuits in the same way.     

Electronically tunable current-mode instrumentation amplifier with high CMRR and wide bandwidth

A current-mode instrumentation amplifier consists of only two current follower differential input transconductance amplifiers is proposed in this paper. The proposed circuit of instrumentation amplifier is realized without using any passive components. Thus, the proposed circuit structure is very simple and suitable to the integrated circuit technology. The input impedance is low and output impedance is high, therefore the proposed circuit is easily cascadable. The gain of the proposed instrumentation amplifier is electronically controllable. The proposed circuit also enjoys the features of high common mode rejection ratio, wide bandwidth and low power consumption. Additionally, performance of the proposed circuit is tested under process, supply voltage and temperature variations. Furthermore, another circuit of instrumentation amplifier, which is capable of providing higher differential mode gain is also shown. The non-ideal and parasitic studies are included. HSPICE simulations are performed to validate the proposed circuits of instrumentation amplifier.     

The Electronic Circuit Composition and Structure of Thread for a Novel Braid Electronics-Systems by Kumihimo Structure

The new integrated circuit concept that forms electronic equipment by the textile structure using the flexible fiber has been proposed. In this report, we propose another integrated system-concept of flexible electronics based on "braid structure." The braid integrated system forms electronic equipment constructed by the filamentous body. Electronic integrated circuits are constructed with kumihimo-structure by weaving more than eight threads on which field effect transistors, photoelectric transducers, contact electrode pad and wiring pattern are mounted periodically. The circuit composition and a concrete structure of threads for kumihimo are discussed.     

RFID标签中有机补偿电路的设计

当前RFID标签技术有着极为广泛的应用,为了减少RFID标签的制造成本和提高工作的可靠性,提出了一种有机补偿电路。该电路集成了8个阶段的有机整流器,其最高工作频率可以达到14 MHz,以及一个集成的PUF结构,它产生一个不可克隆的随机码,每一个独立的结构生成自己的代码,并可以准确地从其他电路中识别出来,耦合这两个电路以及天线将可以建立一个RFID无源标签。该方案可以应用于塑料薄膜中逐片有机处理的RFID标签中,方便设计和制造出复杂的全有机电路。     

A digitally programmable delay element: design and analysis

Variable delay elements are often used to manipulate the rising or falling edges of the clock or any other signal in integrated circuits (ICs). Delay elements are also used in delay locked loops (DLLs). Although, a few types of digitally controlled delay elements have been proposed, an analytical expression for the delay of these circuits has not been reported. In this paper, we propose a new delay element architecture and develop an analytical equation for the output voltage and an empirical relation for the delay of the circuit. The proposed circuit exhibits improved delay characteristics over previously reported digitally controlled delay elements.     

Computing the Detection Probability for Small Delay Defects of Nanometer ICs

Interconnect imperfections have become an important issue in modern nanometer technologies. Some of them cause Small Delay Defects (SDDs) which are difficult to detect. Those SDDs not detected during testing may pose a reliability problem. Furthermore, nanometer issues (e.g. process variations, spatial correlations) represent important challenges for traditional delay test methods. In this paper, a methodology to compute the Detection Probability (DP) of resistive open and bridge defects using a statistical timing framework that takes into account process variations and other nanometer issues is proposed. The DP gives the sensitivity of the circuit performance to a given resistance range of the defect. The efficiency issue when analyzing large circuits is alleviated using stratified sampling techniques to reduce the space of possible analyzed defect locations This methodology is applied to some ISCAS benchmark circuits. The obtained results show the feasibility of the proposed methodology. Measures can be taken for those circuits presenting non-acceptable DP in order to improve the test quality.     

A Simple Method for Millimeter-Wave Finline Balanced Mixer Design Using Three-Dimensional Field Simulation Software

In this paper, a simple method for millimeter-wave finline balanced mixer design using three-dimensional field simulation software has been proposed. The method can be widely used to design the diode-based circuits, especially for the circuit structures with orthogonal field in some specific hybrid integrated circuits which are unavailable to be designed using the circuit simulator. In these circuits, the power directly at diodes is correlated to the input reflection coefficient. The diodes mounted on the finline circuits are defined as impedance boundary in the commercial computer-aided design (CAD) tool High Frequency Structure Simulator (HFSS) model, and hence simulation with the use of HFSS can be implemented to optimize the input matching network of the finline circuits for transferring maximum power to the diodes. Two finline balanced mixers at U-band using commercial GaAs Schottky diodes have been designed and fabricated to validate this method. Matching structures at the radio frequency (RF) port have been employed for a better return loss and a lower conversion loss. Experiment results are presented and show good agreement with simulation data. The proposed method has proven to be useful for the design of millimeter-wave mixers in finline technique.