用于14位1.25 GS/s ADC的跨导运算放大器

设计了一种用于14位1.25 GS/s 流水线ADC的全差分的跨导运算放大器(OTA)。采用带正反馈和增益自举电路的套筒式两级混合密勒补偿结构,并在传统密勒补偿结构基础上增加了带一组调零电阻的辅助密勒补偿结构。这两种补偿结构使得频率补偿更加灵活。对OTA的零极点进行理论分析和整体传递函数解析,再进行传递函数重构,进而实现了高增益、大带宽和高相位裕度。仿真结果表明,该OTA的增益带宽积大于17 GHz,开环增益大于94 dB。该OTA完全满足14位1.25 GS/s流水线ADC的性能要求。     

10-Gb/s limiting amplifier and laser/modulator driver in 0.18-/spl mu/m CMOS technology

A limiting amplifier incorporates active feedback, inductive peaking, and negative Miller capacitance to achieve a voltage gain of 50 dB, a bandwidth of 9.4 GHz, and a sensitivity of 4.6 mV/sub pp/ for a bit-error rate of 10/sup -12/ while consuming 150 mW. A driver employs T-coil peaking and negative impedance conversion to achieve operation at 10 Gb/s while delivering a current of 100 mA to 25-/spl Omega/ lasers or a voltage swing of 2 V/sub pp/ to 50-/spl Omega/ modulators with a power dissipation of 675 mW. Fabricated in 0.18-/spl mu/m CMOS technology, both prototypes operate with a 1.8-V supply.     

A robust feedforward compensation scheme for multistage operational transconductance amplifiers with no Miller capacitors

A multistage operational transconductance amplifier with a feedforward compensation scheme which does not use Miller capacitors is introduced. The compensation scheme uses the positive phase shift of left-half-plane (LHP) zeroes caused by the feedforward path to cancel the negative phase shift of poles to achieve a good phase margin. A two-stage path increases further the low frequency gain while a feedforward single-stage amplifier makes the circuit faster. The amplifier bandwidth is not compromised by the absence of the traditional pole-splitting effect of Miller compensation, resulting in a high-gain wideband amplifier. The capacitors of a capacitive amplifier using the proposed techniques can be varied more than a decade without significant settling time degradation. Experimental results for a prototype fabricated in an AMI 0.5-/spl mu/m CMOS process show DC gain of around 90 dB and a 1% settling time of 15 ns for a load capacitor of 12 pF. The power supply used is /spl plusmn/1.25 V.     

0.5-V analog circuit techniques and their application in OTA and filter design

We present design techniques that make possible the operation of analog circuits with very low supply voltages, down to 0.5 V. We use operational transconductance amplifier (OTA) and filter design as a vehicle to introduce these techniques. Two OTAs, one with body inputs and the other with gate inputs, are designed. Biasing strategies to maintain common-mode voltages and attain maximum signal swing over process, voltage, and temperature are proposed. Prototype chips were fabricated in a 0.18-/spl mu/m CMOS process using standard 0.5-V V/sub T/ devices. The body-input OTA has a measured 52-dB DC gain, a 2.5-MHz gain-bandwidth, and consumes 110 /spl mu/W. The gate-input OTA has a measured 62-dB DC gain (with automatic gain-enhancement), a 10-MHz gain-bandwidth, and consumes 75 /spl mu/W. Design techniques for active-RC filters are also presented. Weak-inversion MOS varactors are proposed and modeled. These are used along with 0.5-V gate-input OTAs to design a fully integrated, 135-kHz fifth-order elliptic low-pass filter. The prototype chip in a 0.18-/spl mu/m CMOS process with V/sub T/ of 0.5-V also includes an on-chip phase-locked loop for tuning. The 1-mm/sup 2/ chip has a measured dynamic range of 57 dB and draws 2.2 mA from the 0.5-V supply.     

High-frequency modulation characteristics of 1.3-/spl mu/m InGaAs quantum dot lasers

In this letter, we report results of small-signal modulation characteristics of self-assembled 1.3-/spl mu/m InGaAs-GaAs quantum dot (QD) lasers at room temperature. The narrow ridge-waveguide lasers were fabricated with multistack InGaAs self-assembled QDs in active region. A high characteristic temperature of T/sub o/=210 K with threshold current density of 200A/cm/sup 2/ was obtained. Small-signal modulation bandwidth of f/sub -3 dB/=12 GHz was measured at 300 K with differential gain of dg/dn/spl cong/2.4/spl times/10/sup -14/ cm/sup 2/ from detailed characteristics. We observed that a limitation of modulation bandwidth in high current injection appeared with gain saturation. This property can direct future high-speed QD laser design.     

6-k/spl Omega/ 43-Gb/s differential transimpedance-limiting amplifier with auto-zero feedback and high dynamic range

A high-gain, 43-Gb/s InP HBT transimpedance-limiting amplifier (TIALA) with 100-/spl mu/A/sub pp/ sensitivity and 6 mA/sub pp/ input overload current is presented. The circuit also operates as a limiting amplifier with 40-dB differential gain, better than 15-dB input return loss, and a record-breaking sensitivity of 8 mV/sub pp/ at 43 Gb/s. It features a differential TIA stage with inductive noise suppression in the feedback network and consumes less than 450mW from a single 3.3-V supply. The TIALA has 6-k/spl Omega/ (76dB/spl Omega/) differential transimpedance gain and 35-GHz bandwidth and comprises the transimpedance and limiting gain functions, an auto-zero dc feedback circuit, signal level monitor, and slicing level adjust functions. Other important features include 45-dB isolation and 800-mV/sub pp/ differential output.     

Plug-in type 1.3-/spl mu/m fiber amplifier module for rack-mounted shelves

We have successfully developed a plug-in type PDFA module for rack mounted shelves which is assembled on a printed-board. In this module, we use a newly developed Pr/sup 3+/-doped high-NA PbF/sub 2//InF/sub 3/-based fluoride fiber and wavelength stabilized 1.017-/spl mu/m laser diodes (LDs). We have obtained a small-signal gain of 24 dB and a noise figure of 6.6 dB at 1.30 /spl mu/m with an LD drive current of 240 mA/spl times/2. We achieved an output power of 10 dBm with a signal input power of 0 dBm. The total power consumption of this module, including that of a Peltier cooler, was 3.5 W when the LD drive current was 240 mA/spl times/2.     

High-dynamic-range VGA with temperature compensation and linear-in-dB gain control

This paper presents the design and measured performance of a novel intermediate-frequency variable-gain amplifier for Wideband Code-Division Multiple Access (WCDMA) transmitters. A compensation technique for parasitic coupling is proposed which allows a high dynamic range of 77 dB to be attained at 400 MHz while using a single variable-gain stage. Temperature compensation and decibel-linear characteristic are achieved by means of a control circuit which provides a lower than /spl plusmn/1.5 dB gain error over full temperature and gain ranges. The device is fabricated in a 0.8-/spl mu/m 46 GHz f/sub T/ silicon bipolar technology and drains up to 6 mA from a 2.7-V power supply.     

60-GHz SOI CMOS traveling-wave amplifier with NF below 3.8 dB from 0.1 to 40 GHz

In this paper, the design and the results of a CMOS traveling-wave amplifier (TWA) optimized for minimum noise figure is presented. Design tradeoffs and optimization guidelines for maximum operation frequency, gain and minimum noise are discussed by means of analytical calculations and simulations. The MMIC is fabricated using digital 90-nm silicon on insulator (SOI) technology and requires a chip area of only 0.3 mm/sup 2/. At a supply voltage of 2 V and a supply current of 66 mA, a gain of 9.7 dB/spl plusmn/1.6 dB is measured over a frequency range from 10 to 59 GHz. Toward dc, the gain increases up to 16 dB. The unity gain cutoff frequency is 71 GHz. At 20 and 40 GHz, the circuit has a 1-dB output compression point of 12.5 and 9.5 dBm, respectively. From 0.1 to 40 GHz, a noise figure below 3.8 dB is measured. The results are achieved at source/load impedances of 50 /spl Omega/ and include the pad parasitics. To the author's knowledge, the TWA has by far the lowest noise figure achieved for a silicon-based amplifier with comparable bandwidth.     

A CMOS bandpass filter for low-IF bluetooth receivers

A CMOS fully integrated 12th-order bandpass filter for low interemdiate frequency Bluetooth receivers is presented. The design is optimized to meet the selectivity and dynamic range requirements of Bluetooth while consuming relatively low power. The filter is based on unity gain cells and utilizes linearized MOSFET resistors for tuning. It exhibits a bandwidth of 1 MHz and a programmable center frequency range of 2 to 4 MHz. Experimental results obtained from a standard 0.5-/spl mu/m CMOS chip show that the filter exhibits an in-band dynamic range of 53.3 dB at gain of 0 dB, and 52 dB at gain of 15 dB, while consuming a total current of 1.32 mA. Attenuations of more than 10, 38, and 55 dB, are achieved for blockers one, two, and three, respectively.     

Flip-chip bonded 0.85-/spl mu/m bottom-emitting vertical-cavity laser array on an AlGaAs substrate

We report high-performance 0.85-/spl mu/m bottom-emitting vertical-cavity surface-emitting lasers (VCSELs) on an AlGaAs substrate with 2.1 mA threshold current density 4.2 mW maximum output power, 11.7% power conversion efficiency and a maximum operating temperature of 130/spl deg/C. We also demonstrate a flip-chip bonded 0.85-/spl mu/m bottom-emitting VCSEL array, and confirm all pixels across the 8/spl times/8 VCSEL array operate at a f/sub 3/ dB bandwidth of 2.6 GHz at only 4.2 mA.     

A 1-V 140-/spl mu/W 88-dB audio sigma-delta modulator in 90-nm CMOS

A single-loop third-order switched-capacitor /spl Sigma/-/spl Delta/ modulator in 90-nm standard digital CMOS technology is presented. The design is intended to minimize the power consumption in a low-voltage environment. A load-compensated OTA with rail-to-rail output swing and gain enhancement is chosen in this design, which provides higher power efficiency than the two-stage OTA. To lower the power consumption further, class-AB operation is also adapted in the OTA design. Due to the relatively low threshold voltage of the advanced technology, no clock bootstrapping circuits are needed to drive the switches and the power consumption of the digital circuits is reduced. All the capacitors are implemented using multilayer metal-wall structure, which can provide high-density capacitance. The modulator achieves 88-dB dynamic range in 20-kHz signal bandwidth with an oversampling ratio of 100. The power consumption is 140 /spl mu/W under 1-V supply voltage and the chip core size is 0.18 mm/sup 2/.     

A monolithic CMOS 2368/spl plusmn/30 MHz transformer based Q-enhanced series-C coupled resonator bandpass filter

A three-pole 0.1 dB ripple Chebyshev series-C coupled resonator bandpass filter with transformer-based Q-enhancement is presented. This Q-enhancement technique compensates resonator loss and produces a flat passband response with low insertion loss. The compensation scheme uses frequency-dependent negative resistance to compensate frequency-dependent inductor losses, avoiding passband distortion, which is a problem with cross-coupled negative resistance circuits. Fabricated in 0.18 /spl mu/m CMOS, the measured filter center frequency is 2368 MHz with a 60 MHz (3 dB) bandwidth, including probe pad and connecting trace parasitic losses. The filter draws 5.84 mA at 1.5 V, and the die area is 1.5 mm/spl times/1.5 mm.     

Low-threshold proton-implanted 1.3-/spl mu/m vertical-cavity top-surface-emitting lasers with dielectric and wafer-bonded GaAs-AlAs Bragg mirrors

We demonstrate a new structure for long-wavelength (1.3-/spl mu/m) vertical-cavity top-surface-emitting lasers using proton implantation for current confinement. Wafer bonded GaAs-AlAs Bragg mirrors and dielectric mirrors are used for bottom and top mirrors, respectively. The gain medium of the lasers consists of nine strain-compensated AlGaInAs quantum wells. A record low room temperature pulsed threshold current density of 1.13 kA/cm/sup 2/ has been achieved for 15-/spl mu/m diameter devices with a threshold current of 2 mA. The side-mode-suppression-ratio is greater than 35 dB.     

A 60-dB 246-MHz CMOS variable gain amplifier for subsampling GSM receivers

A variable gain amplifier (VGA) is designed for a GSM subsampling receiver. The VGA is implemented in a 0.35-/spl mu/m CMOS process and approximately occupies 0.64 mm/sup 2/. It operates at an IF frequency of 246 MHz. The VGA provides a 60-dB digitally controlled gain range in 2-dB steps. The overall gain accuracy is less than 0.3 dB. The current is 9 mA at 3 V supply. The noise figure at maximum gain is 8.7 dB. The IIP3 is -4 dBm at minimum gain, while the OIP3 is -1 dBm at maximum gain. The group delay is 1.5 ns across 5-MHz bandwidth.     

A 95-dB linear low-power variable gain amplifier

An all-CMOS variable gain amplifier (VGA) that adopts a new approximated exponential equation is presented. The proposed VGA is characterized by a wide range of gain variation, temperature-independence gain characteristic, low-power consumption, small chip size, and controllable dynamic gain range. The two-stage VGA is fabricated in 0.18-/spl mu/m CMOS technology and shows the maximum gain variation of more than 95 dB and a 90-dB linear range with linearity error of less than /spl plusmn/ 1 dB. The range of gain variation can be controlled from 68 to 95 dB. The P1dB varies from - 48 to - 17 dBm, and the 3-dB bandwidth is from 32 MHz (at maximum gain of 43 dB) to 1.05 GHz (at minimum gain of - 52 dB). The VGA dissipates less than 3.6 mA from 1.8-V supply while occupying 0.4 mm/sup 2/ of chip area excluding bondpads.     

A 1.8-V 10-Gb/s fully integrated CMOS optical receiver analog front-end

A fully integrated 10-Gb/s optical receiver analog front-end (AFE) design that includes a transimpedance amplifier (TIA) and a limiting amplifier (LA) is demonstrated to require less chip area and is suitable for both low-cost and low-voltage applications. The AFE is fabricated using a 0.18-/spl mu/m CMOS technology. The tiny photo current received by the receiver AFE is amplified to a differential voltage swing of 400 mV/sub (pp)/. In order to avoid off-chip noise interference, the TIA and LA are dc-coupled on the chip instead of ac-coupled though a large external capacitor. The receiver front-end provides a conversion gain of up to 87 dB/spl Omega/ and -3dB bandwidth of 7.6 GHz. The measured sensitivity of the optical receiver is -12dBm at a bit-error rate of 10/sup -12/ with a 2/sup 31/-1 pseudorandom test pattern. Three-dimensional symmetric transformers are utilized in the AFE design for bandwidth enhancement. Operating under a 1.8-V supply, the power dissipation is 210 mW, and the chip size is 1028 /spl mu/m/spl times/1796 /spl mu/m.     

Positive feedback frequency compensation for low-voltage low-power three-stage amplifier

The use of a new frequency compensation scheme for a three-stage operational amplifier is presented. The use of a positive feedback compensation (PFC) is employed to improve frequency response when compared to nested Miller compensation. A set of design equations is derived to give insight into the sizing of the amplifier. In addition, some characteristics relevant to the low-voltage low-power circuits using operational amplifiers have been modeled. Finally, an optimization algorithm was used with the purpose of extracting the most efficient solution. The PFC is especially suitable for driving large capacitance loads. It improves frequency response, slew rate (SR), and settling time. Small compensation capacitors make it appropriate for integration in commercial CMOS processes. With an active area of 0.03 mm/sup 2/ and working at 1.5 V, the circuit dissipates 275 /spl mu/W, has more than a 100-dB gain, a gain bandwidth of 2.7 MHz, and 1.0 V/spl mu/s average SR while driving a 130-pF load. Both measured frequency and transient step response show that the amplifier is stable.     

A 50-MHz dB-linear programmable-gain amplifier with 98-dB dynamic range and 2-dB gain steps for 3 V power supply

A programmable-gain amplifier (PGA) circuit introduced in this paper has a dynamic gain range of 98 dB with 2 dB gain steps and is controlled by 6-bit gain control bits for a 3 V power supply. It has been fabricated in a 0.5 /spl mu/m 15 GHz f/sub T/ Si BiCMOS process and draws 13 mA. The active die area taken up by the circuit is 400 /spl mu/m /spl times/ 1170 /spl mu/m. A noise figure (NF) of 4.9 dB was measured at the maximum gain setting. In addition, an analysis of the bias current generation to provide dB-linear gain control is presented.     

K-band low-noise amplifiers using 0.18 /spl mu/m CMOS technology

Two K-Band low-noise amplifiers (LNAs) are designed and implemented in a standard 0.18 /spl mu/m CMOS technology. The 24 GHz LNA has demonstrated a 12.86 dB gain and a 5.6 dB noise figure (NF) at 23.5 GHz. The 26 GHz LNA achieves an 8.9 dB gain at the peak gain frequency of 25.7 GHz and a 6.93 dB NF at 25 GHz. The input referred third-order intercept point (IIP3) is >+2 dBm for both LNAs with a current consumption of 30 mA from a 1.8 V power supply. To our knowledge, the LNAs show the highest operation frequencies ever reported for LNAs in a standard CMOS process.