A 1.2 V 10-bit 5MS/s low power CMOS cyclic ADC based on double-sampling technique

This paper presents a 1.2 V 10-bit 5MS/s low power cyclic analog-to-digital converter (ADC). The strategy to minimize the power adopts the double-sampling technique. At the front-end, a timing-skew-insensitive double-sampled Miller-capacitance-based sample-and-hold circuit (S/H) is employed to enhance the dynamic performance of the cyclic ADC. Double sampling technique is also applied to multiplying digital-to-analog converter (MDAC). This scheme provides a better power efficiency for the proposed cyclic ADC. Furthermore, bootstrapped switch is used to achieve rail-to-rail signal swing at low-voltage power supply. The prototype ADC, fabricated in TSMC 0.18 μm CMOS 1P6 M process, achieves DNL and INL of 0.32LSB and 0.45LSB respectively, while SFDR is 69.1 dB and SNDR is 58.6 dB at an input frequency of 600 kHz. Operating at 5MS/s sampling rate under a single 1.2 V power supply, the power consumption is 1.68 mW.     

A 7-bit 40 MS/s single-ended asynchronous SAR ADC in 65 nm CMOS

This paper presents a 7-bit 40 MS/s single-ended asynchronous SAR ADC intended for in-probe use in medical applications, which requires small area and good power efficiency. A single-ended architecture is proposed for a moderate resolution for its simplicity. Together with a double reference technique, the architecture reduces the area of the technology-limited large capacitors. The speed is optimized by an asymmetric delay line embedded in the asynchronous digital logic, enabling a sampling frequency of 40 MS/s. The prototype is fabricated in a 65 nm CMOS technology. Measurement shows that at 1 V supply and 40 MS/s, the ADC achieves an SNDR of 39.73 dB and an ENOB of 6.3 bit, while consuming 298.6 µW, resulting in an energy efficiency of 94.74 fJ/conversion-step. The core circuit layout only occupies 0.017 mm².     

An 8-bit 208 MS/s SAR ADC in 65 nm CMOS

An 8-bit low-power 208MS/s SAR analog-to-digital converter is presented. To achieve a high-speed and low-power operation, a reused terminating capacitor switching procedure is proposed. The proposed switching procedure halves the capacitors leading to a significant power saving over the conventional one. Moreover, the proposed architecture relaxes the settling time of DAC and subsequently improves the conversion rate. The ADC has been simulated in SMIC 65 nm 1.2 V CMOS technology. At a 1.2-V supply and 208 MS/s, the ADC consumes 2.7 mW and achieves an SNDR of 49.6 dB, an SFDR of 61.0 dB with 100 MHz inputs.     

A 1-GS/s 6-bit folding and interpolating ADC in 0.13-μm CMOS

A 1-GS/s 6-bit two-channel time-interleaved folding and interpolating analog-to-digital converter (ADC) is presented in this article. For low voltage applications, input-connection-improved active interpolating amplifiers and cascaded folding amplifiers have been applied. A single front-end track-and-hold (T/H) circuit is used to avoid the sampling-time mismatches between the channels. When supplied with 1.4 V, the circuit achieves signal-to-noise-plus-distortion ratio (SNDR) of 30.74 dB and spurious free dynamic range (SFDR) of 36.91 dB and consumes a power of 66 mW with 500-MHz input and 1-GS/s sampling rate. Differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.57 and 0.81 LSB, respectively. The figure of merit (FoM) is 1.75 pJ/conversionstep. The ADC circuit is prototyped in 0.13-μm CMOS process and occupies a core area of 0.45 mm².     

A 10 b 120 MS/s 108 mW 0.18 μm CMOS ADC with a PVT-insensitive current reference

This paper proposes a 10 b 120 MS/s CMOS ADC with a PVT-insensitive current reference. The designed current reference shows a mean temperature drift of 35.2 ppm/°C in the temperature range from −25 to 100°C and a supply rejection of 1.1%/V between 1.6 and 2.0 V. The prototype ADC fabricated in a 0.18 μm 1P6M CMOS technology demonstrates a measured DNL and INL of 0.18LSB and 0.53LSB with a maximum SNDR and SFDR of 53 and 68 dB at 120 MS/s. The ADC with an active chip area of 1.8 mm² consumes 108 mW at 120 MS/s and 1.8 V while the proposed on-chip current reference consumes 0.35 mW with a die area of 0.02 mm².     

An area-and-power-efficient 8.4-bit ENOB 30 MS/s SAR ADC in 65 nm CMOS

Area and power consumption are two main concerns for the electronics towards the digitalization of in-probe 3D ultrasound imaging systems. This work presents a 10-bit 30 MS/s successive approximation register analog-to-digital converter, which achieves good area efficiency as well as power efficiency, by using a symmetrical MSB-capacitor-split capacitor array with customized small-value finger capacitors. Moreover, simplified dynamic digital logic and a dynamic comparator have been designed. Fabricated in a 65 nm CMOS technology, the core circuit only occupies 0.016 mm². The ADC achieves a signal-to-noise ratio of 52.2 dB, and consumes 61.3 μW at 30 MS/s from a 1 V supply voltage, resulting in a figure of merit (FoM) of 6.2 fJ/conversion-step. The FoM defined by including the area is 0.1 mm² fJ/conversion-step.     

一种57.6mW,10位,50MS/s流水线操作CMOS A/D转换器

在1.8V,0.18μm CMOS工艺下,实现了10位,50MS/s流水线操作A/D转换器的设计和测试.通过优化采样电容和运算跨导放大器(OTA)电流,并采用动态比较器,从而降低功耗;采用复位结构的采样/保持和余量增益电路消除OTA失调电压的影响;优化OTA的次极点,保证其工作稳定.测试结果表明:ADC在整个量化范围内无失码,功耗为57.6mW,失调电压为0.8mV,微分非线性为-0.6～0.7LSB.对5.1MHz的输入信号量化,可获得44.9dB的信号与噪声及谐波失真比.电路面积为0.52mm2.     

一种57.6mW,10位,50MS/s流水线操作CMOS A/D转换器

在1.8V,0.18μm CMOS工艺下,实现了10位,50MS/s流水线操作A/D转换器的设计和测试.通过优化采样电容和运算跨导放大器(OTA)电流,并采用动态比较器,从而降低功耗;采用复位结构的采样/保持和余量增益电路消除OTA失调电压的影响;优化OTA的次极点,保证其工作稳定.测试结果表明:ADC在整个量化范围内无失码,功耗为57.6mW,失调电压为0.8mV,微分非线性为-0.6～0.7LSB.对5.1MHz的输入信号量化,可获得44.9dB的信号与噪声及谐波失真比.电路面积为0.52mm2.     

A 1.5 V 10-b 30-MS/s CMOS pipelined analog-to-digital converter

A 1.5 V 10-b 30MS/s CMOS pipelined analog-to-digital converter (ADC) is described. Low-voltage techniques are proposed for pipelined analog-to-digital converter that avoids the use of low-threshold voltage process, on-chip clock voltage doubler, bootstrapped switch, or switched-opamp technique. At the front-end, a low-voltage S/H circuit with cross-coupled input sampling switch is employed to eliminate the input signal feedthrough and enhance the dynamic performance of the pipelined ADC. Multiplying digital-to-analog converter (MDAC) with cross-coupled configuration also provides an effective common-mode feedback to overcome the problem of common-mode accumulation. The prototype chips have been fabricated and experimental results confirm the feasibility of this new technique.     

A zero-crossing based 10-bit 100 MS/s pipeline ADC with controlled current in 90 nm CMOS

In this paper, a new charging technique for low power zero-crossing based circuit pipeline analog-to-digital converters (ADCs) is presented. The charging current sources are implemented as voltage-controlled current sources in order to charge the sampling capacitors based on the error signal. Using this method, the ADC power consumption is reduced while improving the accuracy. The necessary current control block is shared between consecutive stages further reducing the power consumption and die area. The proposed technique is applied to a 10-bit 100 MS/s pipeline ADC designed in a 90 nm CMOS technology with 1 V power supply. Circuit level simulation results using Cadence Spectre show a signal-to-noise and distortion ratio of 55.6 dB with 3.56 mW power consumption resulting in a figure of merit of 72.3 fJ/conv.step without employing any calibration technique.     

一种3.3 V 9位50 MS/s CMOS流水线A/D转换器

设计了一种3.3 V 9位50 MS/s CMOS流水线A/D转换器。该A/D转换器电路采用1.5位/级,8级流水线结构。相邻级交替工作,各级产生的数据汇总至数字纠错电路,经数字纠错电路输出9位数字值。仿真结果表明,A/D转换器的输出有效位数(ENOB)为8.712位,信噪比(SNR)为54.624 dB,INL小于1 LSB,DNL小于0.6 LSB,芯片面积0.37 mm2,功耗仅为82 mW。     

14位20 MS/s CMOS流水线A/D转换器

介绍了一种14位20 MS/s CMOS流水线结构A/D转换器的设计.采用以内建晶体管失配设置阈值电压的差分动态比较器,省去了1.5位流水线结构所需的±0.25 VR两个参考电平;采用折叠增益自举运算放大器,获得了98 dB的增益和900 MHz的单位增益带宽,基本消除了运放有限增益误差的影响;采用冗余编码和数字校正技术,降低了对比较器失调的敏感性,避免了余差电压超限引起的误差.电路采用0.18 μm CMOS工艺,3.3 V电源电压.仿真中,对频率1 MHz、峰值1 V的正弦输入信号的转换结果为:SNDR 85.6 dB,ENOB 13.92位,SFDR 96.3 dB.     

12位1O MS/s CMOS流水线A/D转换器的设计

文中介绍了一种六级12位10Msample/sCMOS流水线A／D转换器的设计。该设计方案采用了双差分动态比较器结构,保证了处理模拟信号的精度与速度;采用冗余编码技术,进行数字误差校正,减小了多种误差敏感性,避免了由于余量电压超限而导致的失码,并降低了采样／保持电路和D/A转换电路的设计难度。     

A 1.4GS/s 9-bit 45 dB power control RFDAC for digital radio transmitters

This paper presents a high speed, 9-bit RF Digital-to-Analog Converter based on a new architecture implemented in a 0.13 μm BiCMOS process and able to adjust the output power by 45 dB to meet gain control requirements of the new communications standards with a SFDR >25 dBc. The maximum test-demonstrated frequency is 1.4 GHz and the chip dissipates <25 mW.     

An 18-bit high performance audio ∑-△D/A converter

A multi-bit quantized high performance sigma-delta(Σ-Δ) audio DAC is presented.Compared to its singlebit counterpart,the multi-bit quantization offers many advantages,such as simplerΣ-Δmodulator circuit,lower clock frequency and smaller spurious tones.With the data weighted average(DWA) mismatch shaping algorithm,element mismatch errors induced by multi-bit quantization can be pushed out of the signal band,hence the noise floor inside the signal band is greatly lowered.To cope with the crosstalk between ...     

A 10-bit 1.8 V 45 mW 100 MHz CMOS transmitter chip for use in an XDSL modem in a home network

This paper describes a 10-bit 1.8 V 45 mW 100 MHz transmitter chip (TX chip) that is fabricated using 0.18 μm 1P6 M CMOS technology for use in an xDSL modem in a home network. The chip is composed of a 10-bit segmented digital-to-analog converter (DAC) and a fully differential adaptive line driver (LD). In designing the DAC, the switched-current method is used to increase the conversion speed; the anti-process-variation current cell with threshold-voltage compensation is used to reduce the linearity error, and the current cell, with differential input and gain boosting, is used to minimize the feedthrough error and tapered error distribution. The circuit layout of the current source has four-phase symmetry, not only to increase the linearity but also to eliminate the gradient error. To design a fully differential adaptive LD, the feed-forward capacitor and quiescent current control circuit are used to reduce the zero-crossing distortion and to minimize the second-order harmonic. Additionally, the power efficiency is increased using an output-impedance matching circuit. Measurements reveal that, for a TX chip at a differential load of 100 Ω and a supplied voltage of 1.8 V, the efficient number of bits, operating frequency, output voltage, output current, power consumption, differential nonlinearity error and integral nonlinearity error are 9 bits, 100 MHz, ± 0.874 V, ± 10 mA, 45.8 mW, ?0.80 to +0.62 LSB, and ?0.92 to +0.82 LSB, respectively.     

An 18-bit high performance audio Σ-△ D/A converter

A multi-bit quantized high performance sigma-delta (Σ-△) audio DAC is presented.Compared to its singlebit counterpart,the multi-bit quantization offers many advantages,such as simpler Σ-△ modulator circuit,lower clock frequency and smaller spurious tones.With the data weighted average (DWA) mismatch shaping algorithm,element mismatch errors induced by multi-bit quantization can be pushed out of the signal band,hence the noise floor inside the signal band is greatly lowered.To cope with the crosstalk between digital and analog circuits,every analog component is surrounded by a guard ring,which is an innovative attempt.The 18-bit DAC with the above techniques,which is implemented in a 0.18μm mixed-signal CMOS process,occupies a core area of 1.86 mm2.The measured dynamic range (DR) and peak SNDR are 96 dB and 88 dB,respectively.     

A 6-bit 2.5-GS/s flash ADC using comparator redundancy for low power in 90 nm CMOS

A 2.5 GS/s flash ADC, fabricated in 90 nm CMOS utilizes comparator redundancy to avoid traditional power, speed and accuracy trade-offs. The redundancy removes the need to control comparator offsets, allowing the large process-variation induced mismatch of small devices in nanometer technologies. This enables the use of small-sized, ultra-low-power comparators with clock-gating capabilities in order to reduce the power dissipation. The chosen calibration method enables an overall low-power solution and measurement results show that the ADC dissipates 30 mW at 1.2 V. With 63 comparators, the ADC achieves 3.9 effective number of bits.     

A 12-bit 100 MS/s pipelined SAR ADC with addition-only digital error correction

A new redundant successive approximation register (SAR) ADC architecture with digital error correction is presented to avoid the comparator offset issue and subtraction operations. A 2-channel 12-bit 100 MS/s SAR ADCs based on the proposed architecture with voltage-controlled delay lines based time-domain comparator is designed in a 65 nm CMOS technology. Simulation results show that at a supply voltage of 1.2 V, the SAR ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 70.81 dB (11.47 ENOB), a spurious free dynamic range (SFDR) of 80.33 dB for a near Nyquist input at 100 MS/s, while dissipating 11 mW from a 1.2-V supply, giving a FOM of 38.8 fJ/Conversion-step.     

一种12位50MS/s CMOS流水线A/D转换器

采用TSMC 0.18μm 1P6M工艺设计了一个12位50 MS/s流水线A/D转换器（ADC）。为了减小失真和降低功耗,该ADC利用余量增益放大电路（MDAC）内建的采样保持功能,去掉了传统的前端采样保持电路;采用时间常数匹配技术,保证输入高频信号时,ADC依然能有较好的线性度;利用数字校正电路降低了ADC对比较器失调的敏感性。使用Cadence Spectre对电路进行仿真。结果表明,输入耐奎斯特频率的信号时,电路SNDR达到72.19 dB,SFDR达到88.23 dB。当输入频率为50 MHz的信号时,SFDR依然有80.51 dB。使用1.8 V电源电压供电,在50 MHz采样率下,ADC功耗为128 mW。