A Low‐Spur CMOS PLL Using Differential Compensation Scheme

This paper proposes LC voltage‐controlled oscillator (VCO) phase‐locked loop (PLL) and ring‐VCO PLL topologies with low‐phase noise. Differential control loops are used for the PLL locking through a symmetrical transformer‐resonator or bilaterally controlled varactor pair. A differential compensation mechanism suppresses out‐band spurious tones. The prototypes of the proposed PLL are implemented in a CMOS 65‐nm or 45‐nm process. The measured results of the LC‐VCO PLL show operation frequencies of 3.5 GHz to 5.6 GHz, a phase noise of –118 dBc/Hz at a 1 MHz offset, and a spur rejection of 66 dBc, while dissipating 3.2 mA at a 1 V supply. The ring‐VCO PLL shows a phase noise of –95 dBc/Hz at a 1 MHz offset, operation frequencies of 1.2 GHz to 2.04 GHz, and a spur rejection of 59 dBc, while dissipating 5.4 mA at a 1.1 V supply.     

A low spur, low jitter 10-GHz phase-locked loop in 0.13-μm CMOS technology

This paper presents a 10-GHz low spur and low jitter phase-locked loop (PLL).An improved low phase noise VCO and a dynamic phase frequency detector with a short delay reset time are employed to reduce the noise of the PLL.We also discuss the methodology to optimize the high frequency prescaler's noise and the charge pump's current mismatch.The chip was fabricated in a SMIC 0.13-μm RF CMOS process with a 1.2-V power supply.The measured integrated RMS jitter is 757 fs (1 kHz to 10 MHz); the phase noise is -89 and-118.1 dBc/Hz at 10 kHz and 1 MHz frequency offset,respectively; and the reference frequency spur is below -77 dBc.The chip size is 0.32 mm2 and the power consumption is 30.6 mW.     

An integrated 8-12 GHz fractional-N frequency synthesizer in SiGe BiCMOS for satellite communications

We present an integrated fractional-N low-noise frequency synthesizer for satellite applications. By using two integrated VCOs and combining digital and analog tuning techniques, a PLL lock range from 8 to 12 GHz is achieved. Due to a small VCO fine tuning gain and optimized charge pump output biasing, the phase noise is low and almost constant over the tuning range. All 16 sub-bands show a tuning range above 900 MHz each, allowing temperature compensation without sub-band switching. This makes the synthesizer robust against variations of the device parameters with process, supply voltage, temperature and aging. The measured phase noise is ?87 dBc/Hz and ?106 dBc/Hz at 10 kHz and 1 MHz offset, respectively. In integer-N mode, phase noise values down to ?98 dBc/Hz at 10 kHz and ?111 dBc/Hz at 1 MHz offset, respectively, were measured.     

Design challenges of a 65 nm CMOS stacked folded differential PA structure for mobile communications

In this paper, a novel phase-locked loop (PLL) architecture with multiple charge pumps, which is used to design a fast-locking PLL and a low-phase-noise PLL, is proposed. The effective capacitance and resistance of the loop filter in terms of voltage is scaled up/down according to the locking status by controlling the magnitude and direction of the charge pump current. Two PLLs, one with a fast-locking characteristic and the other with a low-phase-noise characteristic, are designed and fabricated in a 0.35-μm CMOS process based on the proposed architecture. The fast-locking PLL has a locking time of less than 6 μs and a phase noise of −90.45 dBc/Hz at 1 MHz offset. The low-phase-noise PLL has a locking time of 25 μs, a phase noise of −105.37 dBc/Hz at 1 MHz offset, and a reference spur of −50 dBc. Both PLLs have an 851.2 MHz output frequency.     

A multiple-pass ring oscillator based dual-loop phase-locked loop

A dual-loop phase-locked loop (PLL) for wideband operation is proposed. The dual-loop architecture combines a coarse-tuning loop with a fine-tuning one, enabling a wide tuning range and low voltage-controlled oscillator (VCO) gain without poisoning phase noise and reference spur suppression performance. An analysis of the phase noise and reference spur of the dual-loop PLL is emphasized. A novel multiple-pass ring VCO is designed for the dual-loop application. It utilizes both voltage-control and current-control simultaneously in the delay cell. The PLL is fabricated in Jazz 0.18-μm RF CMOS technology. The measured tuning range is from 4.2 to 5.9 GHz. It achieves a low phase noise of-99 dBc/Hz @ 1 MHz offset from a 5.5 GHz carrier.     

基于电感电容振荡器的电荷泵锁相环的设计

设计并实现了一种采用电感电容振荡器的电荷泵锁相环,分析了锁相环中鉴频/鉴相器(PFD)、电荷泵(CP)、环路滤波器(LP)、电感电容压控振荡器(VCO)的电路结构和设计考虑。锁相环芯片采用0.13μm MS&RF CMOS工艺制造。测试结果表明,锁相环锁定的频率为5.6～6.9 GHz。在6.25 GHz时,参考杂散为-51.57 dBc;1 MHz频偏处相位噪声为-98.35 dBc/Hz;10 MHz频偏处相位噪声为-120.3 dBc/Hz;在1.2 V/3.3 V电源电压下,锁相环的功耗为51.6 mW。芯片总面积为1.334 mm2。     

A low jitter, low spur multiphase phase-locked loop for an IR-UWB receiver

A low jitter,low spur multiphase phase-locked loop(PLL) for an impulse radio ultra-wideband(IR-UWB) receiver is presented.The PLL is based on a ring oscillator in order to simultaneously meet the jitter requirement, low power consumption and multiphase clock output.In this design,a noise and matching improved voltage-controlled oscillator(VCO) is devised to enhance the timing accuracy and phase noise performance of multiphase clocks.By good matching achieved in the charge pump and careful choice of the l...     

A technique to improve the linearization of frequency–voltage characteristic of LC-VCO

This paper presents a very low-power linearization technique to improve the linearity of frequency-voltage characteristic of LC-VCO (voltage controlled oscillator) using MOS varactor. This reduces the VCO gain (K _VCO) variation and its required value over the tuning voltage range. Low K _VCO improves noise and reference spur performances at the output of phase lock loop/frequency synthesizer (FS). Low K _VCO variation reduces FS loop stability problem. Using this VCO circuit, a fully on-chip integer-N frequency synthesizer has been fabricated in 0.18 μm epi-digital CMOS technology for 2.45 GHz ZigBee application. The measured VCO phase noise is ?115.76 and ?125.23 dBc/Hz at 1 and 3 MHz offset frequencies, respectively from 2.445 GHz carrier and the reference spur of the frequency synthesizer is ?68.62 dBc. The used supply voltage is 1.5 V.     

A 5.7–6.0 GHz CMOS PLL with low phase noise and −68 dBc reference spur

This paper presents a 5.7–6.0 GHz Phase-Locked Loop (PLL) design using a 130 nm 2P6M CMOS process. We propose to suppress reference spur through reducing the current mismatch in charge pump (CP), controlling the delay time in phase frequency detector (PFD), and using a smaller VCO gain (KVCO). With a reference frequency of 32.768 MHz, chip measurement results show that the frequency tuning range is 5.7–6.0 GHz, the reference spur is −68 dBc, the phase noise levels are −109 dBc/Hz and −135 dBc/Hz at 1 MHz and 10 MHz offset respectively for 5.835 GHz. Compared with existing designs in the literature, this work’s reference spur is improved by at least 17% and its phase noise is the lowest. Under a 1.5 V supply voltage, the power dissipation with an output buffer of the PLL is 12 mW.     

A 14-GHz 256/257 dual-modulus prescaler with secondary feedback and its application to a monolithic CMOS 10.4-GHz phase-locked loop

A 14-GHz 256/257 dual-modulus prescaler is implemented using secondary feedback in the synchronous 4/5 divider on a 0.18-/spl mu/m foundry CMOS process. The dual-modulus scheme utilizes a 4/5 synchronous counter which adopts a traditional MOS current mode logic clocked D flip-flop. The secondary feedback paths limit signal swing to achieve high-speed operation. The maximum operating frequency of the prescaler is 14 GHz at V/sub DD/=1.8 V. Utilizing the prescaler, a 10.4-GHz monolithic phase-locked loop (PLL) is demonstrated. The voltage-controlled oscillator (VCO) operates between 9.7-10.4 GHz. The tuning range of the VCO is 690 MHz. The phase noise of the PLL and VCO at a 3-MHz offset with I/sub vco/=4.9 mA is -117 and -119 dBc/Hz, respectively. At the current consumption of I/sub vco/=8.1 mA, the phase noise is -122 and -122 dBc/Hz, respectively. The PLL output phase noise at a 50-kHz offset is -80 dBc/Hz. The PLL consumes /spl sim/31 mA at V/sub DD/=1.8 V.     

一种基于偏移源的频率合成技术分析

针对一种基于偏移源的频率合成技术,建立了锁相环(PLL)线性模型,对相位噪声和杂散信号性能进行分析。从分析结果看,在锁相环反馈支路中使用一个偏移源将压控振荡器(VCO)输出信号下混频至一个较低的中频,从而将锁相环的环路分频比大大降低,使改善后的锁相环噪底达到-135 dBc/Hz。介绍了偏移源和主环的关键合成技术,结合工程应用设计的基于偏移源的C频段频率合成器,相位噪声偏离载波10 kHz处≤-99 dBc/Hz,偏离载波100 kHz处≤-116 dBc/Hz,杂散小于-70 dBc。     

Fully Differential 5‐GHz LC‐Tank VCOs with Improved Phase Noise and Wide Tuning Range

In this paper, we propose two LC voltage‐controlled oscillators (VCOs) that improve both phase noise and tuning range. With both 1/f induced low‐frequency noise and low‐frequency thermal noise around DC or around harmonics suppressed significantly by the employment of a current‐current negative feedback (CCNF) loop, the phase noise in the CCNF LC VCO has been improved by about 10 dB at 6 MHz offset compared to the conventional LC VCO. The phase noise of the CCNF VCO was measured as ?112 dBc/Hz at 6 MHz offset from 5.5 GHz carrier frequency. Also, we present a bandwidth‐enhanced LC VCO whose tuning range has been increased about 250 % by connecting the varactor to the bases of the cross‐coupled pair. The phase noise of the bandwidth‐enhanced LC‐tank VCO has been improved by about 6 dB at 6 MHz offset compared to the conventional LC VCO. The phase noise reduction has been achieved because the DC‐decoupling capacitor Cc prevents the output common‐mode level from modulating the varactor bias point, and the signal power increases in the LC‐tank resonator. The bandwidth‐enhanced LC VCO represents a 12 % bandwidth and phase noise of ?108 dBc/Hz at 6 MHz offset.     

Current-mode phase-locked loop with constant-Q active inductor CCO and active transformer loop filter

This paper presents a current-mode phase-locked loop (PLL) with a constant-Q CMOS active inductor current-controlled oscillator (CCO) and a CMOS current-mode active-transformer loop filter. The constant-Q active inductor provides a large and swing-independent quality factor such that the phase noise of the CCO utilizing the constant-Q active inductor is comparable to that of CCO with spiral inductors. The current-mode active-transformer loop filter offers the advantage of a large and tunable inductance and low silicon consumption such that the loop bandwidth of the PLL can be made small and tunable. The PLL was designed in TSMC-0.18 μm 6-metal 1.8V CMOS technology and analyzed using SpectreRF from Cadence Design Systems with BSIM3v3 device models. The phase noise of the PLL was analyzed using Cadence’s Verilog-AMS behavioral modeling. The phase noise of the CCO with the constant-Q active inductor is ?123.1 dBc/Hz at 1 MHz frequency offset, over 10 dB better as compared with that of the CCO with conventional active inductors, and is only a few dB higher than that of the CCO with spiral inductors. The phase noise of the PLL with an active-transformer loop filter and a constant-Q CCO is ?116 dBc/Hz at 1 MHz frequency offset, nearly 20 dB lower than that of the PLL with the same active-transformer loop filter and a conventional active-inductor CCO. The lock time, power consumption, and phase noise of the PLL are 60 ns, 34 mW, and ?116 dBc/Hz at 1 MHz frequency offset, respectively. The total silicon consumption of the PLL excluding bond pads is 0.013 mm².     

A 0.5-1.7 GHz low phase noise ring-oscillator-based PLL for mixed-signal SoCs

This paper describes the design of a fully integrated low phase noise CMOS phase-locked loop for mixedsignal SoCs with a wide range of operating frequencies.The design proposes a multi-regulator PLL architecture,in which every noise-sensitive block from the PLL top level is biased from a dedicated linear or shunt regulator,reducing the parasitic noise and spur coupling between different PLL building blocks.Supply-induced VCO frequency sensitivity of the PLL is less than 0.07%-f_(vco)/1%-V_(DD).The design...     

A self-calibration technique for wide tuning range PLLs

This paper presents a new calibration technique applicable for wide tuning range phase locked loops (PLLs) using very low gain voltage controlled oscillators (VCO). This technique uses the PLL main loop for the coarse and fine tuning of the VCO. Instead of using two loops which has been reported in previous works, in this work the VCO tuning voltage is used to calibrate the VCO switch capacitor array. Since the proposed calibration circuit operates in a closed loop form, it can be used for channel selection as well as adjusting for process, voltage and temperature variations. In addition, the calibration circuit has been used to set the VCO tail current in order to optimize VCO phase noise. A prototype frequency synthesizer has been designed in 0.18-μm CMOS process to work for a frequency range from 2.4 to 2.72 GHz. Simulation results show that using the proposed technique, a spur level of ?60 dB at 5 MHz offset from carrier was achieved while having negligible power overhead.     

A multi-band CMOS PLL-based frequency synthesizer for DRM/DRM+/DAB systems

A wideband frequency synthesizer is designed and fabricated in a 0.18 μm CMOS technology. It is developed for DRM/DRM+/DAB systems and is based on a programmable integer-N phase-locked loop. Instead of using several synthesizers for different bands, only one synthesizer is used, which has three separated divider paths to provide quadrature 8-phase LO signals. A wideband VCO covers a frequency band from 2.0 to 2.9 GHz, generates LO signals from 32 to 72 MHz, and from 250 to 362 MHz. In cooperation with a programmable XTAL multi-divider at the PLL input and output dividers at the PLL output, the frequency step can be altered from 1 to 25 kHz. It provides an average output phase noise of ?80 dBc/Hz at 10 kHz offset, ?95 dBc/Hz at 100 kHz offset, and ?120 dBc/Hz at 1 MHz offset for all the supported channels. The output power of the LO signals is tunable from 0 dBm to +3 dBm, and the phase of quadrature signals can also be adjusted through a varactor in the output buffer. The power consumption of the frequency synthesizer is 45 mW from a 1.8 V supply.     

Parametric Analysis of a Novel Architecture of Phase Locked Loop for Communication System

The work proposed parametric analysis of a novel architecture of phase locked loop (PLL) for pure signal synthesis. It has been widely used in wireless communication systems due to the high frequency resolution and the short locking time. First, we presented a mathematical and accurate model of noise in PLL with take into account noise of its component. Then we predicted output phase noise in term of its parameters. Finally, we described as effective technique for noise in fractional PLL by CppSim simulator. The output phase noise has been reduced from \(-154\) to \(-159\,\) dBc/MHz at 20 MHz offset. The proposed behavioral simulation results show improvement around 5 dBc/MHz. In future, this technique can also be implemented in hybrid PLL.     

Write pulse Generator for 16x DVD recording with symmetric CMOS inverter ring oscillator

This paper reports the design and measurement results of a write pulse generator IC for rewritable CD and DVD disk drives implemented in a standard digital 0.35 /spl mu/m CMOS technology. The chip is the interface between a processor and a laser driver. It provides accurate timing signals to the laser driver via a four-level differential current interface. Transitions between current levels are programmable with 149 ps resolution at a data rate of 420 Mb/s, corresponding to 16x DVD write speed. The chip includes a digital core managing the different write strategies, a CMOS serial interface to the processor for programming, a low power, low phase noise, 64-phase ring voltage-controlled oscillator (VCO) based on CMOS inverters, a phase-locked loop (PLL) locking the VCO to the system clock, and a current interface to the laser driver. The PLL phase noise is -144 dBc/Hz at 10 MHz offset from the 105 MHz carrier. At this frequency, the rms jitter is 1.1 ps with 0.8 mA VCO core supply current. The chip is fully ESD protected.     

Comparison between RTW VCO and LC QVCO 12?GHz PLLs

This paper reports comparisons between RTW VCO and LC QVCO 12?GHz PLLs, designed in a 130?nm CMOS technology for satellite communication applications. The phase noise at 1?MHz offset from the carrier is ?102?dBc/Hz for the RTW VCO PLL and ?98?dBc/Hz for the LC QVCO PLL, and the power consumption is 39 and 17?mW, respectively.     

LC-VCO design optimization at 1/f 2 phase noise performance in 65 nm CMOS technology

A way of analytical calculation in the phase noise modeling of the LC-VCO topology without tail current resource is proposed. The noise current imported by the MOS channel is modeled to give approximate evaluation, and the period of the transistor noise is included in the model. Phase noise introduced by the tank loss resistance is also modeled to evaluate the circuit phase noise performance. The circuit has been implemented in a 65 nm CMOS technology. The chip occupies 951 × 705 um² areas with the buffer and pads. The test result indicates that the VCO core consumes 1.125 mW with a 1.2 V power supply, the frequency of the VCO baseband is from 1.258 to 1.37 GHz, and the multiband frequency is from 0.86 to 1.37 GHz. The best performance of the LC-VCO shows a phase noise of ?129.57 dBc/Hz at 1 MHz offset frequency from a 1.3 GHz carrier, resulting in an excellent FoM of ?191.27 dBc/Hz.