A low-phase-noise and low-power multiband CMOS voltage-controlled oscillator

A low voltage multiband all-pMOS VCO was fabricated in a 0.18-/spl mu/m CMOS process. By using a combination of inductor and capacitor switching, four band (2.4, 2.5, 4.7, and 5 GHz) operation was realized using a single VCO. The VCO with an 1-V power supply has phase noises at 1-MHz offset from a 4.7-GHz carrier of -126 dBc/Hz and -134 dBc/Hz from a 2.4-GHz carrier. The VCO consumes 4.6 mW at 2.4 and 2.5 GHz, and 6 mW at 4.7 and 5 GHz, respectively. At 4.7 GHz, the VCO also achieves -80 dBc/Hz phase noise at 10-kHz offset with 2 mW power consumption.     

High-speed voltage-controlled oscillator with quadrature outputs

A voltage-controlled oscillator topology is described that combines a fully-differential four-stage ring oscillator with a balanced exclusive NOR gate frequency doubler, and provides both inphase and quadrature output signals at twice the ring oscillator frequency. These quadrature signals have a period of only four gate delays, which implies high frequency operation.<>     

一种提供5位频带切换控制的5GHz压控振荡器

设计了一种提供5位频带切换控制的5GHz电容电感压控振荡器,采用NMOS-PMOS交叉耦合结构,并且为消除电流源的闪烁噪声而应用电阻偏置调节工作电流.电路采用TSMC RF0.18μm CMOS工艺进行仿真,仿真结果显示,在1.8V电源电压下,在偏离中心频率1MHz处的相位噪声为-120.8dBc/Hz,调谐范围为24.6%,功耗仅为2.3mW.     

Digital voltage-controlled blocking oscillator

A digital voltage-controlled blocking oscillator is presented, which can generate a number of pulses during a period of blocking oscillation. The number of pulses can be changed due to supply voltage.     

A low-phase noise injection-locked quadrature voltage-controlled oscillator

This article presents a low-phase noise quadrature voltage-controlled oscillator (QVCO) in which the re-filtering technique of the side-band noise is adopted. In the proposed QVCO, besides using re-filtering technique, the passive elements replaced the noisy and lossy active coupling devices. Therefore, due to the elimination of the associate noise sources of the active coupling devices and re-filtering of side-band noise of the circuit, the proposed QVCO shows an excellent phase-noise and FOM. The proposed QVCO was implemented and simulated in TSMC 0.18 μm RF-CMOS technology. The phase noise of the proposed QVCO at 3 MHz offset frequency from the 3 GHz center frequency is ?144 dBc/Hz, for a current consumption of 11.5 mA at a power supply of 1.8-V. Simulation results show the proposed QVCO can operate with power supply as low as 0.6 V. Monte–Carlo analyses for, 3% device mismatch and process variation, result in phase error lower than 0.8°. Generalizing the proposed coupling technique to several core VCOs very low-phase noise multiphase signals can be generated.     

A sinusoidal voltage-controlled oscillator for integrated circuits

This article describes an inductorless near-harmonic voltage-controlled oscillator circuit that utilizes a compensated Wien-bridge topology with a voltage-controlled Miller integrator as the tuning element. Suitable for monolithic integrated realization, the VCO offers a two-to-one control range for frequencies up to 10 MHz, with less than a 1-dB amplitude variation and less than a ten percent total harmonic distortion over the entire control range.     

A phase-noise reduction technique for RF CMOS voltage-controlled oscillator with a series LC resonator

This paper proposes a novel phase-noise reduction technique for high performance voltage-controlled oscillator (VCO) using a cross-coupled series LC resonator, rather than parallel LC resonator. The proposed technique makes a time difference between the zero crossing point of the drain node voltages and that of the gate node voltages of the switching pair. By adding cross coupled PMOS loading, the drain voltages are made close to a rectangular shape, which makes an ideal on–off switching of the VCO. Since the current source contributes large portion of noise to the output, it is removed in the proposed VCO to further improve the noise performance. While the series connected inductor and capacitor enhances the fundamental frequency swing at the LC connection node, it gives a cleaner spectral purity output and suppresses the overall noise at the drain node of the cross-coupled switching cell.     

A 20-GHz InP-HBT voltage-controlled oscillator with wide frequencytuning range

This paper presents the design and implementation of a 20-GHz-band differential voltage-controlled oscillator (VCO) using InP heterojunction-bipolar-transistor process technology. Aimed at 20- or 40-Gb/s fiber-optic applications, the design is based on a single-stage feedback amplifier with no intentional L or C. The salient features of the proposed VCO are wide frequency tuning range compared to LC oscillators, and low power consumption and transistor count compared to ring-oscillator counterparts. The implemented VCO has an adjustable frequency range from 13.75 to 21.5 GHz and provides two complementary outputs. Total power consumption at 18.6 GHz is 130 mW, while the phase noise is -90.0 dBc/Hz measured at 1-MHz offset frequency     

Ultra wideband, low-power, 3-5.6 GHz, CMOS voltage-controlled oscillator

In this paper, a low-power inductorless ultra wideband (UWB) CMOS voltage-controlled oscillator is designed in TSMC 0.18 μm CMOS technology as a part of a ultra wideband FM (UWBFM) transmitter. The VCO includes a current-controlled oscillator (CCO) which generates output frequencies between 1.5 and 2.8 GHz and a voltage-to-current (V-to-I) converter. A low-power frequency doubler based on a Gilbert cell, which operates in weak inversion, doubles the VCO tuning range achieving oscillation frequencies between 3 and 5.6 GHz. Thus, the well-known proportionality between the oscillation frequency and the bias tuning current in CCOs is avoided for the entire achieved tuning range, resulting in a lower power design. The employed architecture provides high suppression, over 45 dB, of the 1st and 3rd harmonics, while enabling high-frequency operation and conversion gain due to the unbalanced structure and the single-ended output. The current consumption is 5 mA at a supply voltage of 1.8 V. The VCO exhibits a phase noise of −80.56 dBc/Hz at 1 MHz frequency offset from the carrier and a very high ratio of tuning range (60.4%) over power consumption equal to 8.26 dB which is essential for a UWBFM transmitter.     

4.6 GHz CMOS voltage-controlled oscillator

A 4.6 GHz voltage-controlled oscillator (VCO) was designed and fabricated using 0.25 μm CMOS technology. A careful circuit design based on a trade-off between frequency-tuning range and phase-noise characteristics, realised both a sufficient frequency-tuning range of 230 MHz and a low phase-noise characteristic of -118.1 dBc/Hz at 1 MHz offset. This phase-noise characteristic is superior to previously reported VCOs     

A 30-MHz low-jitter high-linearity CMOS voltage-controlled oscillator

A fully monolithic voltage-controlled oscillator (VCO) with an on-chip timing capacitor and a maximum oscillation frequency of 30 MHz is reported. Using a novel on-chip servo loop, the VCO displays less than 0.17% nonlinearity in its voltage-frequency transfer function from 1 to 15 MHz without trimming. An improved circuit topology that provides a large swing on the timing capacitor allows the VCO to obtain a cycle-to-cycle jitter of less than 100 p.p.m. The circuit operates on a 5-V supply with a die size of 104 mil/spl times/154 mil.     

A 1.8-GHz CMOS low-phase-noise voltage-controlled oscillator withprescaler

The implementation of the two high-frequency building blocks for a low-phase-noise 1.8-GHz frequency-synthesizing PLL in a standard 0.7-μm CMOS process is discussed. The VCO uses on-chip bondwires, instead of spiral inductors, for low noise and low power. The design of these bondwire inductors is discussed in great detail. A general formula for the theoretical limit of the phase noise of LC-tuned oscillators is presented. The design of a special LC-tank allows a trade-off between noise and power. The realized VCO has a phase noise of -115 dBc/Hz at 200 kHz from the 1.8-GHz carrier and consumes 8 mA from a 3-V supply. The prescaler has a fixed division ratio of 128 and uses an enhanced ECL-alike high-frequency D-flipflop. Its power consumption is 28 mW     

A low-phase-noise voltage-controlled oscillator for 17-GHz applications

A silicon bipolar voltage-controlled oscillator (VCO) for 17-GHz applications is presented. The VCO is composed of a core oscillating at 9GHz followed by a frequency doubler. It adopts a transformer-based topology to obtain both wide tuning range and low noise performance. The VCO exhibits a tuning range of 4.1GHz from 16.4 to 20.5GHz and a phase noise as low as -109dBc/Hz at a 1-MHz frequency offset from a carrier of 18.5GHz.     

A wide-range 22-GHz LC-based CMOS voltage-controlled oscillator

This work presents a novel voltage-controlled oscillator (VCO) design and simulations that combine a varactor bank with a transformer in the LC tank to achieve a high-frequency range. While the varactor bank is responsible for changing the capacitance in the LC tank, the transformer acts as a means to change the value of the inductance, hence allowing tune-ability in the two main components of the VCO. A control mechanism utilises a mixed-mode circuit consisting of comparators and a state machine. It allows efficient tuning of the VCO by controlling the capacitance and transformer in the LC tank. The VCO has a 10.75–22.43 GHz frequency range and the VCO gain, K_VCO, is kept at a low value ranging from 98.6 to 175.7 MHz/V. The simulated phase noise is ?111 dBc/Hz at 1 MHz offset from the 10.75 GHz oscillation frequency. The circuit is designed and simulated in 28 nm CMOS technology and uses a 1 V supply drawing a typical power of 14.74 mW.     

A low-power wide tuning-range CMOS current-controlled oscillator

This paper presents a low-power, small-size, wide tuning-range, and low supply voltage CMOS current-controlled oscillator (CCO) for current converter applications. The proposed oscillator is designed and fabricated in a standard 180-nm, single-poly, six-metal CMOS technology. Experimental results show that the oscillation frequency of the CCO is tunable from 30 Hz to 970 MHz by adjusting the control current in the range of 100 fA to 10 µA, giving an overall dynamic range of over 160 dB. The operation of the circuit is nearly independent of the power supply voltage and the circuit operates at supply voltages as low as 800 mV. Also, at this voltage, with control currents in the range of sub-nano-amperes, the power consumption is about 30 nW. These features are promising in sensory and biomedical applications. The chip area is only 8.8×11.5 µm².     

A low-power biologically-inspired chaotic oscillator with process and temperature tolerance

This paper presents a low-power, biologically-inspired silicon neuron based implementation of a chaotic oscillator circuit. The silicon neuron structure is based on Hodgkin–Huxley neuron model. Subthreshold MOSFET and current reuse techniques have been utilized to achieve a low-power consumption of 180.30 nW for the room temperature (27 °C) and typical process corner. The chaotic behavior of the circuit is confirmed by calculating the largest Lyapunov exponent. A sensitivity analysis of the proposed chaotic oscillator shows that the circuit maintains the chaotic behavior for five different process corners within the temperature range of 0–60 °C.     

A voltage-controlled ring oscillator using InP full enhancement-mode HEMT logic

A voltage-controlled ring oscillator (VCO) based on a full enhancement-mode InAIAs/InGaAs/InP high electron mobility transistor (HEMT) logic is proposed. An enhancement-mode HEMT (E-HEMT) is fabricated, whose threshold is demonstrated to be 10 mV. The model of the E-HEMT is established and used in the SPICE simulation of the VCO. The result proves that the full E-HEMT logic technology can be applied to the VCO. And compared with the HEMT DCFL technology, the complexity of our fabrication process is reduced and the reliability is improved.     

A modified Park-Kim voltage-controlled ring oscillator for multi-Gbps serial links

This paper proposes a new multi-stage CMOS voltage-controlled ring VCO called modified Park-Kim ring VCO for multi-Gbps serial links. An in-depth comparative study of pros and cons of Park-Kim VCO and the modified Park-Kim VCO with both single and dual delay paths is given. We show that the modified Park-Kim VCO offers an improved oscillation frequency, large output voltage swing, comparable frequency tuning range and phase noise as compared with Park-Kim VCO proposed in [1, 2]. We further show that although the modified Park-Kim VCO with single delay path and that with dual delay path offer comparable oscillation frequencies when the number of stages of the VCOs is high, the former provides a large frequency tuning range and reduced circuit complexity. To verify performance improvement, both Park-Kim VCOs and the modified Park-Kim VCOs are implemented in TSMC’s-0.18 μm, 1.8 V CMOS technology and analyzed using SpectreRF from Cadence Design Systems with BSIM3.3 device models. Simulation results are presented.     

A coupled-inductor dual-mode switched voltage-controlled oscillator using GaN-on-Si HEMT technology

A coupled-inductors dual-mode switch cross-coupled pair voltage-controlled oscillator (VCO) was presented, adopting GaN-on-Si high-electron-mobility transistor technology. The coupled inductors create two resonant frequencies that cover a wide frequency range. The two continuous bands were achieved by using coupled inductors, and the fine-tuning is controlled by varactors. The low and high bands of the VCO were 2.77–3.11 GHz and 3–3.28 GHz, in the V_c range between 10 and 17 V, respectively, which corresponds to a 16.7% (510 MHz) tuning range. The lowest phase noise was ?123 dBc/Hz at an offset frequency of 1 MHz, and the highest output power was 17.7 dBm using a 7.5-V power supply.