Measurement of the hot carrier damage profile in LDMOS devices stressed at high drain voltage

In this paper, the hot carrier degradation of laterally diffused nMOSFETs is investigated in detail by the analysis of the fundamental device parameters and charge pumping measurements. Starting from this experimental characterization a new approach based on charge pumping technique is developed to estimate the spatial distribution of the hot carrier damage. This methodology has been applied on test structures, obtaining good results in the prediction of both the interface states and the trapped charges profiling. The supporting assumptions have been verified by fitting to the electrical data and by means of a two-dimensional device simulation.     

An experimental study of carrier heating on channel noise in deep-submicrometer NMOSFETs via body bias

In this paper, RF noise in 0.18-mum NMOSFETs concerning the contribution of carrier heating and hot carrier effect is characterized and analyzed in detail via a novel approach that modulates the channel carrier heating and number of hot carriers using body bias. We confirm qualitatively a negligible role of hot carrier effect on the channel noise in deep-submicrometer MOSFETs. For a device under reverse body bias (V_b), even though the increase in hot carrier population is clearly characterized by dc measurements, the device high-frequency noise is found to be irrelevant to the increase in the channel hot carriers. Experimental results show that the high-frequency noise is slightly reduced with the increase in |V_b|, and can be qualitatively explained by secondary effects such as the suppression of nonequilibrium channel noise and substrate induced noise. The reduction of NF_min and R_n with the increase in |V_b| may provide a possible methodology to finely adjust the device high-frequency noise performance for circuit design     

深亚微米HCI模型参数多目标全域提取方法

研究了一种建立在退化栅电流物理解析模型基础上的深亚微米pMOS器件HCI(hot carrier injection)退化模型. 提出了一种基于L-M (Levenberg-Marquardt）算法的多目标响应全域优化提取策略，并对可靠性模型参数进行优化提取. 分析了优化过程中由于参数灵敏度过低产生的问题并提出采用递归算法求解不同时刻栅电流注入电荷量的加速计算方法. 最后，给出了最优化参数提取的结果，并且将测量值与理论值进行了比较,得到很好的一致性.     

A study on hot carrier effects on N-MOSFETs under high substrate impurity concentration

A systematic investigation of the influences of high substrate doping on the hot carrier characteristics of small geometry n-MOSFETs down to 0.1 /spl mu/m has been carried out. Results indicate that the dependence of substrate current and impact ionization rate on substrate impurity concentration is reversed in long channel and short channel devices. In the long channel case, both increase with rising substrate impurity concentration, while they decrease in the case of short channel devices. An explanation for this phenomenon based on the lucky electron model has been developed. The dependence of other characteristics on impurity concentration has also been studied. The dependence of off-leakage current has been found to fall as the gate oxide is reduced in thickness. Regarding the dependence of hot carrier degradations, the degradation of drain currents becomes smaller as the substrate impurity concentration increases in the case of short channel devices. Further, in the extremely high impurity doping region, a new hot carrier degradation mode was found, in which the maximum transconductance values of n-MOSFETs increase after hot carrier stress. This new degradation mode can be explained in terms of effective channel length shortening caused by electron trapping.<>     

深亚微米MOSFET热载流子退化机理及建模的研究进展

本文给出了深亚微米ＭＯＳ器件热载流子效应及可靠性研究与进展,对当前深亚微米ＭＯＳ器件中的主要热载流子现象以及由其引起的器件性能退化的物理机制进行了详细论述。不仅对热电子,同时也对热空穴的影响进行了重点研究,为深亚微米ＣＭＯＳ电路热载流子可靠性研究奠定了基础。本文还讨论了深亚微米器件热载流子可靠性模型,尤其是ＭＯＳ器件的热载流子退化模型。     

How do hot carriers degrade n-channel MOSFETs?

Explores the mechanisms of hot carrier degradation in n-MOSFETs. In addressing the problem of hot carrier degradation, we examine the carrier injection process, whereby electrons and holes are injected into the oxide from the channel. Next, we'll look at the processes responsible for creating damage. Third, the impact of the damage on the MOSFET's terminal characteristics is deternined. Then the damage process is modeled. Finally, we'll address ways to reduce hot carrier degradation     

Characterization and modeling of hot carrier injection in LDMOS for L-band radar application

This paper reports a methodology to correlate Hot Carrier Injection (HCI) degradation mechanism and electrical figures of merit on Lateral-Diffused Metal-Oxide-Semiconductor (LDMOS) transistor. This method is based on RF life test in radar operating conditions coupled to a high drain voltage in order to make visible HCI degradation. We propose drain current modeling vs. time based on a simple extraction procedure. The electron density trapped in the oxide is extracted from hot carrier induced series resistance enhancement model (HISREM - i.e. ΔR_d model). From this methodology, the degradation of RF-LDMOS due to HCI is quantified and could be simulated with EDA.     

Physical model of drain conductance, gd, degradation ofNMOSFET's due to interface state generation by hot carrierinjection

Degradation of analog device parameters such as drain conductance, g_d, due to hot carrier injection has been modeled for NMOSFET's. In this modeling, mobility reduction caused by interface state generation by hot carrier injection and the gradual channel approximation were employed. It has been found that g_d degradation can be calculated from linear region transconductance, g_m, degradation which is usually monitored for hot carrier degradation of MOSFET's. The values of g_d degradation calculated from g_m degradation fit well to the measured values of g_d degradation The dependence of the g_d degradation lifetime on L_eff has been also studied, this model also provides an explanation of the dependence on L_eff. The model is then useful for lifetime predictions of analog circuits in which g_d degradation is usually more important than g_m degradation     

通过直接栅电流测量研究PMOSFET's热载流子损伤

通过直接栅电流测量方法研究了热载流子退化和高栅压退火过程中PMOSFET's热载流子损伤的生长规律.由此,给出了热载流子引起PMOSFET's器件参数退化的准确物理解释.并证明了直接栅电流测量是一种很好的研究器件损伤生长和器件参数退化的实验方法.     

Hot carrier induced degradation in mesa-isolated n-channel SOIMOSFETs operating in a Bi-MOS mode

A thorough investigation of hot carrier effects is made in mesa-isolated SOI nMOSFETs operating in the Bi-MOS mode (abbreviated as Bi-nMOSFETs). As a result of its unique hybrid operation mechanism, significant reduction of hot carrier induced maximum transconductance degradation and threshold voltage shift in the Bi-nMOSFET is observed in comparison with that in the conventional SOI nMOSFETs. Device lifetime of SOI Bi-nMOSFETs and conventional SOI nMOSFETs was roughly estimated for comparison. In view of the analysis of the degradation mechanism, the devices were stressed under different conditions. The post-stress body current and stress body current in Bi-nMOSFETs as a function of the stress time and stress drain voltage were evaluated as further proofs of the aging reasons. The hot electron injection is found to be the dominant degradation process in the SOI Bi-nMOSFETs. Compared with SOI nMOSFETs, SOI Bi-nMOSFETs show better immunity to the parasitic bipolar transistor action due to the body contact. In addition, the positive body bias can result in lowered hot hole injection into the gate oxide due to the provision of the generated hole leakage path, and thus decreased interface traps     

Experimental study of hot carriers in small size Si-MOSFETs

Hot carrier effects in Si-MOSFETs cause serious reliability problems in VLSI circuits. While most of them have been investigated empirically, it is also important to clarify the microscopic degradation mechanism. In addition, there are other effects which can affect the device characteristics significantly and can be used to study hot carrier transport in MOSFETs. In this paper, several experimental studies associated with hot carrier effects in MOSFETs are reviewed. In particularly, hot electron energy effects are discussed, such as velocity overshoot and photo-emission in MOSFETs, and technological efforts to overcome the degradation problem in actual devices are reviewed briefly.     

Oxide reliability of drain engineered I/O NMOS from hot carrier injection

The impact of hot carrier stress on the breakdown properties of I/O NMOS gate oxide is reported. I/O NMOS devices with drain structures using standard LDD with pocket (S-LDD) and graded LDD without pocket (G-LDD) are used. Time-dependent (TDDB) and voltage-ramp (VRDB) dielectric breakdown tests are performed for devices with and without hot-carrier-injection. It is demonstrated that both I/O structures show similar oxide integrity after hot carrier injection (HCI) when the Idsat degradation is small (<5%), but show significantly different oxide lifetimes when the Idsat degradation is high (>5%). At 10% I/sub dsat/ degradation, the oxide lifetime for the G-LDD structure is reduced by about a factor of 10 compared to that of the S-LDD structure. The correlation between oxide integrity and leakage current indicates that the oxide charge introduced by HCI stress is the reason for oxide degradation. This work clearly demonstrates that the effect of hot carrier induced oxide damage must be included when predicting the oxide lifetimes of advanced I/O NMOS devices.     

DC应力n-MOSFET热载流子退化的1/f噪声特性

研究了DC应力n.MOSFET热载流子退化的Sfγ噪声参量.提出了用噪声参数和Sfγ表征高、中、低三种栅应力下n-MOSFET抗热载流子损伤能力的方法.进行了高、中、低三种栅压DC应力下热载流子退化实验.实验结果和本文模型符合较好.     

Comparison of hot carrier-induced RF performance degradation in H-gate and T-gate SOI MOSFETs

The RF performance degradation of silicon-on-insulator (SOI) MOSFETs with H-gate and T-gate structures after hot carrier stressing has been investigated. Our experimental results show that the RF performance degradation is more significant than the dc performance degradation after hot carrier stressing. Also, the degradation of the H-gate device is more significant than that of the T-gate device due to the higher drain current. Since the degradation of minimum noise figure is the most significant, the hot carrier effects should be taken into account in the design of LNA using the H-gate device although its RF performance is better than that of the T-gate device.     

The optimum fin width in p-MuGFETs with the consideration of NBTI and hot carrier degradation

Generally it is known that NBTI degradation increases with decrease of a channel width in p-MOSFETs but hot carrier degradation decreases. In this work, a guideline for the optimum fin width in p-MuGFETs is suggested with consideration of NBTI and hot carrier degradation. Using the device lifetime defined as the stress time necessary to reach ΔV_TH = 10 mV, the optimum fin widths have been extracted for different stress voltages and temperatures. When a fin width is narrower than the optimum fin width, the device lifetime is governed by the NBTI degradation. However, when fin width is wider than the optimum fin width, the device lifetime is dominantly governed by hot carrier degradation. The optimum fin width decreases with the increase of the stress voltage but it increases with the increase of the stress temperature.     

Hot carrier hardness analysis of submicrometer LDD devices

A detailed analysis of the degradation of various lightly doped drain (LDD) devices is presented. Technology parameters that are varied are gate length, LDD n-dose, and energy for devices with 20-nm gate oxide. Different DC stress conditions are investigated. To gain insight into the degradation process a simulation tool is used that self-consistently calculates the oxide damage during a DC stress experiment. This enables the location and amount of oxide charges and interface states due to hot carrier injection to be obtained. The relationship between stress-induced damage and device hot carrier hardness is discussed     

Hot carriers in quasi-2-D polar semiconductors

This paper reviews hot carrier effects in quasi-2-D polar semiconductors (quantum wells and heterostructures), with special emphasis on the GaAs/AlGaAs system. After briefly introducing the basic concepts in hot carrier physics, we discuss theoretical calculations of carrier-phonon interactions and hot carrier energy loss rates to the lattice in quasi-2-D systems. We then discuss how these quantities are affected by degeneracy, plasma effects, and hot phonons. The bulk of the paper is devoted to a discussion of experimental results and their analysis. Three kinds of experiments are discussed: I-V and related transport measurements, direct time-of-flight measurements of velocity-field characteristics, and measurements which use optical spectroscopy to provide direct information about the carrier distribution function in the presence of external perturbations. The optical studies have given valuable new insight into the behavior of hot carrier relaxation processes in quasi-2-D systems from femtosecond to steady-state conditions.     

Comparison of NMOS and PMOS hot carrier effects from 300 to 77 K

Since hot carrier effects can pose a potential limit to device scaling, hot-carrier-induced device degradation has been one of the major concerns in modern device technology. Currently, there is a great interest in pursuing low-temperature operation of MOS devices since it offers many advantages compared to room temperature operation. Also, low-temperature operation is often required for space applications. However, low-temperature operation exacerbates hot carrier reliability of MOS devices. Even though hot carrier effects are significantly worse at low temperature, most of the studies on hot-carrier-induced device degradation were done at room temperature and little has been done at low temperature. In this work, hot-carrier-induced device degradation is characterized from 77 K to room temperature for both NMOS and PMOS devices with the emphasis on low-temperature behavior of hot carrier degradation. For NMOS devices, the worst case bias condition for hot carrier effects is found to be a function of temperature. It is also determined that one of the primary reasons for the great reduction on hot carrier device lifetime at low temperature is that a given amount of damage simply induces a greater reduction on device performance at low temperature. For PMOS devices, the initial damage appears similar for both room temperature and 77 K; however, subsequent annealing indicates that the damage mechanism at 77 K differs markedly from that at 300 K. Hot carrier stressing on PMOS devices at low temperature appears to induce hole generation and substantial interface state creation upon annealing unlike 300 K stressed devices. This finding may have serious reliability implications for PMOS devices operated at cryogenic temperatures     

A novel hot carrier reliability monitor for LDD p-MOSFETs

The gate-edge shape of an LDD p-MOSFET exhibits large influences upon the hot carrier induced degradation and its performances. It is observed that the gate-to-drain tunneling current is strongly correlated to the reentrant gate oxide thickness and to the device degradation. A simple model is then constructed to provide an explanation for the observation. Under the tunneling current measurement conditions, a thicker oxide at the gate-edge leads to a weaker peak electric field in the p-LDD and to a lower gate-to-drain current. On the other hand, under the hot carrier stressing conditions, the thicker oxide decreases the oxide electric field and thus suppresses the hot electron injection. The observed correlation can be employed to monitor the process induced gate-edge (overlap) variation.     

Temperature dependence of hot carrier induced MOSFET degradation at low gate bias

This paper reports a new experimental finding on the temperature dependence of the substrate current and hot carrier induced device degradation at low gate bias. It has been found that the substrate current increases and the drain current degradation is more significant for high operating temperature at low gate bias. It has been observed that the hot carrier induced performance degradation of a latch-type input buffer increases at the elevated temperature.