The effect of cathode materials on reactive ion etching of silicon and silicon dioxide in a CF4 plasma

Silicon and silicon dioxide have been Reactive Ion Etched in a CF₄ plasma using a diode sputtering configuration to achieve etching. Pressures ranged from 20 to 100 millitorr and power densities to the RF cathode were between 0.1 and 1.0 W/cm². The effect of cathode material on the quality of etched surfaces and on etch rates has been investigated. It has been observed that the etch rate of silicon decreases as the area of silicon exposed to the plasma is increased and that this silicon loading effect is strongly influenced by the material covering the balance of the cathode. For instance, the silicon loading effect is much more pronounced when silicon dioxide rather than aluminum is used to cover the balance of the cathode. This silicon loading effect was investigated further by varying RF power. It was found that loading a silicon dioxide covered cathode with silicon wafers decreases the dependence of silicon etch rate on power. The silicon dioxide etch rate and its dependence on RF power are the same whether silicon, silicon dioxide or aluminum is used to cover the balance of the cathode. Possible explanations for these experimental results will be discussed.     

High-frequency silicon alloy transistor

The silicon alloy transistor is a high-frequency, p-n-p type transistor capable of operation at high temperatures. Its temperature characteristic, derived principally from the use of silicon as the semiconductor, permits operation from - 70°C to 150°C. It achieves its high-frequency characteristic through accurate control of the base geometry. The n-type base of silicon is accurately machined by jet electrochemical techniques. Alloy contacts of aluminum are fused into the bottoms of the etch pits without producing appreciable change in base geometry. The depth of alloy is limited by the thickness of the aluminum, by the temperature, and by the length of time for alloying. Lead wires are soldered to the aluminum contacts and the transistor hermetically sealed in glass-metal containers. The electrical characteristics of typical silicon alloy transistors include an Icoof 0.005 µa, a common emitter forward current gain of 12, and an alpha-cutoff frequency of 12 mc.     

Bulk micromachining of silicon in TMAH-based etchants for aluminum passivation and smooth surface

The fabrication of silicon based micromechanical sensors often requires bulk silicon etching after aluminum metallization. All wet silicon etchants including ordinary undoped tetramethyl ammonium hydroxide (TMAH)-water solution attack the overlaying aluminum metal interconnect during the anisotropic etching of (100) silicon. This paper presents a TMAH-water based etching recipe to achieve high silicon etch rate, a smooth etched surface and almost total protection of the exposed aluminum metallization. The etch rate measurements of (100) silicon, silicon dioxide and aluminum along with the morphology studies of etched surfaces are performed on both n-type and p-type silicon wafers at different concentrations (2, 5, 10 and 15%) for undoped TMAH treated at various temperatures as well as for TMAH solution doped separately and simultaneously with silicic acid and ammonium peroxodisulphate (AP). It is established through a detailed study that 5% TMAH-water solution dual doped with 38 gm/l silicic acid and 7 gm/l AP yields a reasonably high (100) silicon etch rate of 70 μm/h at 80 °C, very small etch rates of SiO₂ and pure aluminum (around 80 Å/h and 50 Å/h, respectively), and a smooth surface (±7 nm) at a bath temperature of 80 °C. The etchant has been successfully used for fabricating several MEMS structures like piezoresistive accelerometer, vaporizing liquid micro-thruster and flow sensor. In all cases, the bulk micromachining is carried out after the formation of aluminum interconnects which is found to remain unaffected during the prolonged etching process at 80 °C. The TMAH based etchant may be attractive in industry due to its compatibility with standard CMOS process.     

聚焦离子束刻蚀性能的研究

对聚焦离子束（FIB）的基本刻蚀性能进行了实验和研究．通过扫描电镜对FIB刻蚀坑的观测,给出了在不同材料上（硅、铝和二氧化硅）FIB的刻蚀速率及刻蚀坑的形貌同离子束流大小的关系．由于不同材料的原子结合能、原子量及晶体结构等因素对离子束溅射产额的影响,从而影响着离子束的刻蚀速率;随着离子束流的增大,刻蚀速率并非线性增加,且刻蚀坑的形貌越来越不均匀,对此也作了系统的分析和探讨．     

Etch characteristics of KOH, TMAH and dual doped TMAH for bulk micromachining of silicon

High precision bulk micromachining of silicon is a key process step to shape spatial structures for fabricating different type of microsensors and microactuators. A series of etching experiments have been carried out using KOH, TMAH and dual doped TMAH at different etchant concentrations and temperatures wherein silicon, silicon dioxide and aluminum etch rates together with <100> silicon surface morphology and <111>/<100> etch rate ratio have been investigated in each etchant. A comparative study of the etch rates and etched silicon surface roughness at different etching ambient is also presented.From the experimental studies, it is found that etch rates vary with variation of etching ambient. The concentrations that maximize silicon etch rate is 3% for TMAH and 22 wt.% for KOH. Aluminum etch rate is high in KOH and undoped TMAH but negligible in dual doped TMAH. Silicon dioxide etch rate is higher in KOH than in TMAH and dual doped TMAH solutions. The <111>/<100> etch rate ratio is highest in TMAH compared to the other two etchants whereas smoothest etched silicon surface is achieved using dual doped TMAH. The study reveals that dual doped TMAH solution is a very attractive CMOS compatible silicon etchant for commercial MEMS fabrication which has superior characteristics compared to other silicon etchants.     

Optimization of Sidewall Masked Isolation Process

This paper presents modifications of the Sidewall Masked Isolation (SWAMI) process for VLSI device isolation which improve process reproducibility, eliminate stress induced defects, and permit flexibility in channel stop implant optimization. A novel "undercut-and-backfill" technique is introduced to eliminate a localized failure mechanism of the oxidation mask by increasing the strength of the nitride-to-nitride joint. The primary variable influencing stress-induced defect generation is the vertical length of the sidewall nitride mask as determined by the amount of recessed silicon etch prior to sidewall nitride formation. In general, a maximum length can be found below which defect-free structures can be fabricated. An optional second recessed silicon etch, following the formation of the sidewall nitride, has been developed which increases the flexibility in optimizing the channel stop implantation. Defect-free low-Ieakage devices with near-zero electrical channel width reduction have been obtained.     

Optimization of sidewall masked isolation process

This paper presents modifications of the Sidewall Masked Isolation (SWAMI) process for VLSI device isolation which improve process reproducibility, eliminate stress induced defects, and permit flexibility in channel stop implant optimization. A novel "undercut-and-backfill" technique is introduced to eliminate a localized failure mechanism of the oxidation mask by increasing the strength of the nitride-to-nitride joint. The primary variable influencing stress-induced defect generation is the vertical length of the sidewall nitride mask as determined by the amount of recessed silicon etch prior to sidewall nitride formation. In general, a maximum length can be found below which defect-free structures can be fabricated. An optional second recessed silicon etch, following the formation of the sidewall nitride, has been developed which increases the flexibility in optimizing the channel stop implantation. Defect-free low-leakage devices with near-zero electrical channel width reduction have been obtained.     

Design-technology-reliability interactions in Al/CVD-SiO2 multilayer IC's

A multilayer conductor-insulator technology suitable for semiconductor memories has been developed utilizing materials and fabrication techniques compatible with high density LSI structures. Interactions between failure modes, structure design, and process design are presented. Both aluminum-silicon contact windows and interlayer (via) conductor windows must be sloped with appropirate contours to avoid discontinuous metal coverage. The processing involves compatible compositions of multicomponent oxides and a via delineation etch which permits extensive oxide removal without a simultaneous aluminum attack. Intra- and inter- connects are formed from electron beamed aluminum films deposited in a planetary system onto substrates at 300°C (room temperature for first level conductors in a CMOS structure). Desirable film properties include relatively large grain size, low hillock density and complete step coverage. Insulator layers are formed by the chemical vapor deposition of SiO₂ as a product of the oxidation of silane gas. The dielectric protrusions over aluminum hillocks are exaggerated. In addition, bulbous glass is formed over the edges of aluminum stripes unless these intraconnects have a trapezoidal cross-section. This configuration is formed with an H₃PO₄-HNO₃-HAc aluminum delineation etch. Glass-enhanced aluminum hillocks can cause both intraconnect opens and interlayer shorts during conductor and via etching unless compensating topographic/photoengraving design rules are observed.     

Pyramid-shaped silicon photodetector with subwavelength aperture[for NSOM]

We present a new type of silicon photodetector with a subwavelength aperture designed to scan material surfaces with a resolution inaccessible by conventional optical microscopy. Such a probe is designed for integration into a near-field scanning optical microscope (NSOM) for scanning and collecting information from the near-field region located at the vicinity of the surface. The photodetector, which was realized by conventional microelectronics technology, is located on top of a 250-μm-high pyramid, enabling detection of reflected as well as transmitted light. The light sensitive part of the probe consists of a micromachined silicon structure built using anisotropic etch solutions such as ethylene diamine pyrocatechol (EDP) and KOH. The shape of the probe is a truncated double pyramid with a ring shape top silicon/aluminum Schottky diode surrounding an exposed silicon photosensitive area of about 150 nm in diameter. Typical I-V characteristics and optical response measurements are presented     

聚焦离子束溅射刻蚀与增强刻蚀的性能研究

利用聚集离子束(F IB)对小线度下(≤3μm)的溅射刻蚀与增强刻蚀的性能进行了实验和分析。通过对硅和铝的刻蚀实验,研究在溅射刻蚀与增强刻蚀方法下刻蚀速率、蚀坑形貌与离子束流大小的关系。实验发现,铝和硅的刻蚀速率与刻蚀束流近似成线性关系;束流增大到一定程度后由于束斑变大及瞬时重淀积的作用,刻蚀速率曲线偏离线性。使用卤化物气体的增强刻蚀,硅和铝的刻蚀速率得到不同程度地提高。根据蚀坑形貌与束流大小的关系分析,发现瞬时重淀积是影响小线度刻蚀质量的主要因素。增强刻蚀大大减小了蚀坑的坑璧倾角,而坑底倾斜问题需综合考虑。     

Encapsulation of naked dies for bulk silicon etching with TMAH

Because of the increasing number of metal levels within a semiconductor device and the ongoing transition to new package types failure analysis from the back side of a die becomes necessary. A useful chemical for bulk silicon removal is tetra-methyl-ammonium-hydroxide (TMAH). Because of the aggressive etch conditions, the edges of naked dies have to be protected against destruction by encapsulation into an appropriate molding compound. Different encapsulation materials were evaluated to identify a useful molding compound and an encapsulation method for bulk silicon removal of naked dies using TMAH. Problems as well as results are described in this paper.     

Pyramid size control and morphology treatment for high-efficiency silicon heterojunction solar cells

This paper investigates the formation process of surface pyramid and etching characteristics during the texturing process of mono-crystalline silicon wafers. It is found that there is an etch rate transition point in alkaline anisotropic etching when {100} plane-dominated etch turns to {111} plane-dominated etch, and the pyramid size has a strong linear correlation with the etch amount at the transition point. Several techniques were developed to control the pyramid size by monitoring and adjusting the etching amount. A wide range of average pyramid sizes were successfully achieved, from 0.5 to 12 μm. The experiments of the pyramid size on the light reflectance, the minority carrier lifetime (MCLT), and the performance of silicon heterojunction (SHJ) solar cells were carried out and analyzed. A desirable range of pyramid sizes was empirically determined by our investigation. In order to reduce the density states on the texturing surface, the wet-chemical smoothing treatment was also investigated. The smoothing treatment improves the passivation quality and the performance of the solar cells. Through pyramid size control and morphology treatment, together with the amorphous silicon (a-Si:H) deposition improvement, and electrode optimization, high performance of SHJ solar cells has been achieved, up to conversion efficiency 23.6%.     

Copper may destroy chip-level reliability: handle withcare-mechanism and conditions for copper migrated resistive shortformation

Although copper has a number of advantageous parameters in comparison with aluminum, and therefore, is expected to become the metallization of future high-speed, high-density silicon devices, its application introduces a new failure mechanism into the systems which has never occurred with aluminum; this is the electrochemical migration (not equal to the electromigration) resulting in short circuit formation between adjacent metallization stripes under DC bias. A great alert signal must be given for semiconductor producers in order to perform lifetime tests before introducing copper into the everyday fabrication process, otherwise the reliability of future electronic systems may dramatically be destroyed     

Role of N2 during chemical dry etching of silicon oxide layers using NF3/N2/Ar remote plasmas

In this work, the role of N₂ gas during the chemical dry etching of silicon oxide layers in NF₃/N₂/Ar remote plasmas was investigated by analyzing the species in the plasma, the reaction by-products in the exhaust, and the chemical properties of the etched surface. Increasing the N₂ gas flow rate resulted in an initial increase in the oxide etch rate up to a maximum value, followed by a subsequent decrease. The increased etch rate of the silicon oxide layers was not ascribed to the increased surface arrival rate of fluorine, but to the enhanced oxygen removal from the silicon oxide caused by the formation of NO₂ molecules. Presumably, the NO radicals formed from the added N₂ gas react chemically with the oxygen in the oxide, leading to the breaking of the Si-O bonds and the effective removal of oxygen, which in turn enhances the formation of SiF₄ resulting in an increased etch rate.     

Vapor Phase Metal‐Assisted Chemical Etching of Silicon

This work introduces and explores vapor phase metal‐assisted chemical etching (VP‐MaCE) of silicon as a method to bypass some of the challenges found in traditional liquid phase metal‐assisted chemical etching (LP‐MaCE). Average etch rates for Ag, Au, and Pd/Au catalysts are established at 31, 70, and 96 nm/min respectively, and the relationship between etch rate and substrate temperature is examined experimentally. Just as with LP‐MaCE, 3D catalyst motion is maintained and three‐dimensional structures are fabricated with nanoparticle‐ and lithography‐patterned catalysts. VP‐MaCE produces less microporous silicon compared with LP‐MaCE and the diffusion/reduction distance of Ag⁺ ions is significantly reduced. This process sacrifices etch rate for increased etch uniformity and lower stiction for applications in micro‐electromechanical systems (MEMS) processing.     

The Effect of Ionic Contaminants on Silicon Transistor Stability

The development of the beam-lead sealed-junction (BLSJ) technology (beam-lead contact metals-silicon nitride passivation) included many experiments to study the effects of various ionic contaminants on silicon transistor stability. Stress aging was performed on standard n-p-n silicon transistors (aluminum contacts and silicon dioxide protection) under various conditions of temperature, bias, contamination, and ambient. These experiments showed the following results. 1) Alkali ions and copper in a reducing ambient are detrimental to the devices. 2) A hydrogen ambient accelerates the effect of alkali ions on the transistor degradation. 3) The degradation is approximately a linear function of the reverse bias and the contamination level from 4 to 400 ? of sodium chloride. 4) Anions have only a secondary effect on the migration of alkali ions in the oxide. The BLSJ technology was developed to protect unencapsulated silicon devices from the degradation seen on standard transistors during the preceding experiments. Results have shown that the median time to failure of sodium-contaminated BLSJ transistors aged in air at 300°C is higher than that for standard silicon transistors aged under identical conditions.     

Modeling of plasma process data using a multi-parameterized generalized regression neural network

For characterization or optimization process, a computer prediction model is in demand. A new technique, to improve the prediction performance of conventional generalized regression neural network (GRNN) of plasma process data was presented. Genetic algorithm (GA) was applied to optimize multi-parameterized training factors of GRNN. To evaluate the technique, two data sets were collected from the etchings of silica and silicon carbide (SiC) thin films in inductively coupled plasmas. Both data sets called Data I and Data II were statistically characterized by means of 2³ and 2⁴ full factorial experiment plus one center point. The GRNN models trained with these data were tested with additional six and 16 experiments. A total of eight etch outputs were modeled and compared with conventional GRNN and statistical regression models. The five etch outputs comprising Data I include silica etch rate, aluminum (Al) etch rate, Al selectivity, profile angle, and DC bias. Data II consisted of three etch outputs, including SiC etch rate, surface roughness, and profile angle. Compared to GRNN models, GA-GRNN models yielded more than 40% and 15% improvements for all etch outputs comprising Data I and Data II, respectively. Similar improvements were also demonstrated with respect to statistical regression models. All these results reveal that a multi-parameterization of training factors and GA optimization is an effective technique to considerably improve the prediction performance of conventional GRNN model.     

Healing of voids in the aluminum metallization of integratedcircuit chips

A thermal treatment for healing voids in the aluminum metallization of integrated circuit (IC) chips has been discovered. The aluminum metallization is alloyed with nominally 1 wt.% of silicon. This discovery arose from efforts to cause further growth of preexisting voids in IC RAMs intended for long-term unattended spacecraft applications. The experimental effort was intended to cause further void propagation for the purpose of establishing a time/temperature propagation relationship, but it resulted instead in a healing of the voids. The thermal treatment consisted of heating IC chips with voids in the aluminum/silicon metallization to temperatures in excess of 200°C, followed by quick immersion into liquid nitrogen. The thermal treatment is described, and a theory based on silicon solubility and migration in aluminum is advanced to explain both the formation and the healing of voids in the aluminum metallization of IC chips     

High-level CAD melds micromachined devices with foundries

The use of the Magic technology file to build transducer devices in the form of micro-heaters for use as IR pixels in a thermal display is described. Magic is a high-level computer-aided design (CAD) software system. The design methodology incorporated into the current MOSIS SCMOS technology file for Magic to implement the fabrication of silicon micromachined device structures is presented. This technology file uses only the layers supplied by a commercial standard CMOS process. The main advantages of this technique is that no major equipment is needed and the post-processing is reduced to a single, maskless etch step. The main disadvantage is that custom layers can not be incorporated into the design; therefore, the sensors/transducers can only be composed of polysilicon and/or aluminum sandwiched with thermal oxide and CVD oxide     

A theoretical model of the formation morphologies of porous silicon

In this paper a qualitative theoretical model describing the mechanism and formation morphology of porous silicon is presented. The model is based on the diffusion limited aggregation models of Witten and Sanders. The validity of this model is verified by performing small scale computer simulations to construct various porous silicon structures. These structures are compared with the known properties of bulk silicon and morphologies of porous silicon. The postulates of the model are sufficiently rich to explain the relationship between pore density, pore diameter, porosity as well as crystallographic etch selectivity and electropolishing.