Multiple output zero-current switching switched-capacitor bidirectional dc–dc converter

The proposed circuit is a multiple output quasi-resonant (QR) zero-current switching (ZCS) switched-capacitor (SC) converter with a bidirectional power flow control conversion scheme. The principles of the proposed multiple output QR ZCS SC bidirectional dc–dc converter are described using a detailed circuit model for analysis. Simulation and experimental results are carried out to verify the validity and the soft switching performance of the proposed converter. The maximum efficiency achievable is about 94 and 92% for the forward and reverse power flow control schemes, respectively. The output voltage can be regulated by changing the switching frequency for the designed compensated closed-loop controller.     

A 3 V 10 MHz pseudo-differential SC bandpass filter using gainenhancement replica amplifier

This paper describes the design strategy and implementation of a high frequency low voltage pseudo-differential SC filter which use opamps with gain enhancement replica amplifier. Experimental results of a biquad SC bandpass with a center frequency of 10 MHz and a Q of 10 are presented. The realized opamp has an open-loop unity-gain bandwidth of 850 MHz, a phase margin of about 62°, and a dc gain of 50 dB. The prototype filter dissipates 23 mW from a 3 V supply and occupies 0.3 mm ² in a 0.8 μm N-well single-poly, double-metal CMOS process     

A 200-Ms/s 10-mW switched-capacitor filter in 0.5-μm CMOStechnology

Wideband amplifiers with low but precisely known dc gain allow the achievement of accurate infinite impulse response switched-capacitor (SC) filters operating at very high sampling frequencies. The low and precise opamp gain value is taken into account while sizing the capacitors (precise opamp gain (FOG) approach), so that no idle phase is required for amplitude error compensation and double-sampling technique can be implemented. In a 0.5-μm standard CMOS technology with 3.3-V power supply, an opamp is designed which exhibits a settling time of about 3 ns (for 0.1% settling accuracy) in a closed-loop configuration with input, feedback, and load capacitors of 0.5 pF, white the slew rate is 1 V/ns. The open-loop dc gain of the amplifier is set to the value of 80 (38 dB) by a gain-control closed loop, which guarantees an accuracy of ±2%. The proposed solution is validated by experimental results from a 200-Ms/s SC filter. From a single 3.3-V supply the filter consumes 10 mW (excluding clock generation) and exhibits a -40 dB total harmonic distortion for a 2-V_pp signal amplitude at 4 MHz, achieving a 62-dB dynamic range     

Striped-channel InAlAs/InGaAs HEMTs with shallow-grating structures

Striped-channel (SC) InAlAs/InGaAs HEMTs have been demonstrated with shallow gratings. The shallow grating structure keeps the gate from touching the channel layer and thus solves the gate leakage problem observed in the deep grating devices on InP substrates. Various channel widths have been realized to study the impact of the channel width on the dc and microwave performance. Due to the enhanced charge control in the SC HEMTs, enhanced transconductance/source-drain current (G_m /I_ds) and transconductance/output conductance (G_m /G_ds) were observed. Compared with conventional HEMTs, the SC HEMTs showed degraded f_T due to additional parasitic capacitances and improved f_max due to better carrier confinement     

A cascade boost-switched-capacitor-converter - two level inverter with an optimized multilevel output waveform

Two structures, a switched-capacitor (SC)-based boost converter and a two-level inverter, are connected in cascade. The dc multilevel voltage of the first stage becomes the input voltage of the classical inverter, resulting in a staircase waveform for the inverter output voltage. Such a multilevel waveform is close to a sinusoid; its harmonics content can be reduced by multiplying the stage number of the SC converter. The output low-pass filter, customary after a two-level inverter, becomes obsolete, resulting in a small size of the system, as the SC circuit can be miniaturized. Both stages are operated at a high switching frequency, resulting in a high-frequency inverter output, as required by some industrial applications. A Fourier analysis of the output waveform is performed. The design is optimized with reference to the nominal duty-cycle for obtaining the minimum total harmonic distortion. Simulations and experiments on two prototypes, one with a five-level output and one with a seven-level output, confirm the theoretical analysis.     

一种用于高精度电流型DAC的输出级设计

提出了一种应用于电流型数模转换器(DAC)的输出电路。在对输出级的功能和稳定性作了分析计算后，设计了一种高增益、低失真的运放(OP)电路。运放模拟的直流增益为108dB，环路带宽为30MHz，环路相位裕量为60度，在输出为1rms时，THD N可达到104．8dB。和传统的开关电容(SC)输出级相比，该电路具有面积小、噪声低等优点，可应用于高精度的电流型DAC。     

高速4阶Sigma-Delta调制器系统级设计及行为级仿真

对高速4阶级联开关电容Sigma-Delta调制器结构的设计进行了分析,利用MATLAB SIMULIK工具搜寻了系统优化参数,并通过系统行为级仿真对实际高速电路中存在的运算放大器非理想因素(例如有限增益、有限单位增益带宽等)和开关热噪声(KT/C噪声)等因素对系统特性可能产生的影响进行了仿真计算,在此基础上得到了系统设计对实际电路模块参数特性的基本要求,为实际实现高阶Sigma-Delta系统打下了基础.仿真结果表明在考虑到各种实际因素的条件下,64 MHz时钟32倍超采样条件下系统精度可以达到14 bits.     

Smart Energy Bricks: Ti3C2@Polymer Electrochemical Energy Storage inside Bricks by 3D Printing

Three-dimensional (3D) printing technology has a pronounced impact on building construction and energy storage devices. Here, the concept of integrating 3D-printed electrochemical devices into insulation voids in construction bricks is demonstrated in order to create electrochemical energy storage as an integral part of home building. The low-cost 3D-printed supercapacitor (SC) electrodes are created using graphene/polylactic acid (PLA) filament in any desired shape such as 3D cylindrical- (3Dcy), disk- (3Ddc), and 3D rectangular- (3Drc) shaped electrodes. To obtain excellent capacitive performance, a Ti₃C₂@polypyrrole (PPy) hybrid is uniformly electroplated on the surface of 3D-printed electrodes. These Ti₃C₂@PPy-coated 3D-printed electrodes exhibit outstanding electrical conductivity, capacitive performance, cycle life, and power density. The bricks themselves act as an excellent scaffold for electrochemical energy devices as they are electrically insulating, fire-resistant, and contain substantial unused thermal insulation voids. A 3Drc Ti₃C₂@PPy SC is integrated into a real brick to showcase a smart house energy storage system that allows to reserve power in the bricks and use it as a power backup source in the event of a power outage in the elevator. This concept provides a platform for future truly smart buildings built from added value “smart brick” energy storage systems.     

Comparison of diversity combining techniques for Rayleigh-fadingchannels

Several methods of diversity combining for a Rayleigh-faded channel are evaluated and compared. The methods considered are, for coherent reception, maximal ratio combining (MRC), selection combining (SC), and a generalization of SC, whereby the two (three) signals with the two (three) largest amplitudes are coherently combined. We will call this method second (third) order SC, and denote it SC2 (SC3). Similar techniques are also investigated for noncoherent reception, with equal gain combining (EGC) replacing MRC, and noncoherent versions of SC2 and SC3. Numerical results indicate that SC2 and SC3 significantly enhances the bit-error rate (BER) performance relative to that achievable with SC, and under certain conditions approaches the performance achieved by MRC or EGG. The performance enhancement of SC2 and SC3 is especially noticable for noncoherent reception, where EGC is seen to provide the best performance only for low BER values. In fact, when the BER is 10 ^-3 or greater, SC2 and SC3 performed comparably to EGG, and in some cases performed better than EGC     

SER of M-ary NCFSK with S + N Selection Combining in Nakagami Fading for Integer m

The performance of M-ary orthogonal noncoherent frequency-shift keying (NCFSK) with N branch signal-plus-noise (S + N) selection combining (SC) in Nakagami-m fading (m, integer) is studied. Both independent, identically distributed (i.i.d) and independent, nonidentically distributed (i.n.d) diversity branches are considered and two S + N SC receiver structures are examined. The performances of the S + N SC receivers are compared to those of classical SC and square-law combining (SLC) receivers. The effects of modulation order, fading parameter and the number of diversity branches on the performance of S + N SC are compared to the effects on the performances of classical SC and SLC. For example, it is shown that in an i.n.d fading channel, the value of signal-to-noise ratio (SNR) at which the error rate curves of classical SC and S + N SC cross, decreases as the modulation order, M, increases. Our results indicate that in i.n.d fading channels classical SC outperforms S + N SC for small ranges of SNR, while for moderate to large SNR values S + N SC has superior performance over classical SC. It is also shown that increasing the diversity order will increase the performance gap of S 4N SC over classical SC and over SLC in both i.i.d and i.n.d Nakagami-m fading channels     

A Novel Topology for Photovoltaic DC/DC Full-Bridge Converter With Flat Efficiency Under Wide PV Module Voltage and Load Range

In this paper, a novel topology for a photovoltaic (PV) dc/dc converter that can dramatically reduce the power rating and increase the efficiency of a PV system by analyzing PV module characteristics is proposed. Based on the analysis, in the proposed topology, only 30.7% power of the total PV system is needed for a dc/dc converter. Furthermore, the dc/dc converter efficiency curve is flat under wide PV module voltage and all load ranges. In particular, the converter efficiency at the lower duty range is dramatically improved. The total PV system is implemented for a 250-kW PV power conditioning system (PCS). This system has only three dc/dc converters with a 25-kW power rating. It is only one-third of the total PV PCS power. The 25-kW prototype PV dc/dc converter is introduced to experimentally verify the proposed topology. In addition, an experimental result shows that the proposed topology exhibits a good performance.     

Positive output multiple-lift push-pull switched-capacitor Luo-converters

Micro-power-consumption technique requires high-power-density dc/dc converters and power supply source. Voltage lift technique is a popular method to apply in electronic circuit design. Since a switched capacitor can be integrated into a power IC chip, its size is small. Combining switched-capacitor and voltage lift technique can construct dc/dc converters with small size, high power density, high-voltage transfer gain, high power efficiency, and low electromagnetic interference. This paper introduces a new series of dc/dc converters-positive output multiple-lift push-pull switched-capacitor dc/dc Luo-converters.     

Low-complex processing element architecture for successive cancellation decoder

A low-complexity design architecture for implementing the Successive Cancellation (SC) decoding algorithm for polar codes is presented. Hardware design of polar decoders is accomplished using SC decoding due to the reduced intricacy of the algorithm. Merged processing element (MPE) block is the primary area occupying factor of the SC decoder as it incorporates numerous sign and magnitude conversions. Two’s complement method is typically used in the MPE block of SC decoder. In this paper, a low-complex MPE architecture with minimal two’s complement conversion is proposed. A reformulation is also applied to the merged processing elements at the final stage of SC decoder to generate two output bits at a time. The proposed merged processing element thereby reduces the hardware complexity of the SC decoder and also reduces latency by an average of 64%. An SC decoder with code length 1024 and code rate 1/2 was designed and synthesized using 45-nm CMOS technology. The implementation results of the proposed decoder display significant improvement in the Technology Scaled Normalized Throughput (TSNT) value and an average 48% reduction in hardware complexity compared to the prevalent SC decoder architectures. Compared to the conventional SC decoder, the presented method displayed a 23% reduction in area.     

一种可调节电流的电流型PWM直流转换器

介绍一种用于驱动发光二极管(LED)的可调节电流的电流型PWM直流转换器.该直流转换器由于接有一个外接电阻,可以通过调节外接电阻的大小来调节输出电流.输出电流调节范围在5～40mA之间.主要分析了电路的输出电流调节功能,和这种输出电流可变的电流型PWM直流转换器的电流和电压反馈环的反馈实现原理.并简要介绍了这种带电流调节功能的PWM直流转换器的工作原理,最后给出了电路在输出不同电流时使用HSPICE软件对反馈参考电压,PWM锁存器输出波形的仿真结果.     

A new simple method for analysing of thermal noise in switched-capacitor filters

Thermal noise is one of the most important challenges in analogue integrated circuits design. This problem is more crucial in switched-capacitor (SC) filters due to the aliasing effect of wide-band thermal noise. In this article, a new simple method is proposed for estimating the power spectrum density of output thermal noise in SC filters, which have acceptable accuracy and short running time. In the proposed method, first using HSPICE simulator, accurate value of accumulated sampled noise on sampler capacitors in each clock state is achieved. Next, using difference equations of the SC filter, frequency response of the SC filter is shaped by time domain analysis. Based on the proposed method, a SC low-pass filter and a second-order SC band-pass filter are analysed. The results are validated by comparing to the previously measured data.     

光纤中超连续谱的研究进展

超连续(SC)谱的研究是当今光通讯领域中的热点问题。把SC谱的研究进展分为三个阶段：单模光纤中SC谱的产生;锥形光纤中SC谱的产生;光子晶体光纤(PCF)中SC谱的产生,总结了光纤中SC谱的主要研究成果。特别对近年来研究比较热门的PCF光纤中产生SC谱的情形做了详细的介绍。     

Effects of Parasitic Capacitance, External Resistance, and Local Stress on the RF Performance of the Transistors Fabricated by Standard 65-nm CMOS Technologies

Effects of parasitic capacitance, external resistance, and local stress on the radio-frequency (RF) performance of the transistors fabricated by 65-nm CMOS technology have been investigated. The effect of parasitic capacitance, particularly C_gb, becomes significant due to the reduced spacing between the gate and the substrate contact (SC) in proportion to scaling down. Current drivability (I_dsat) per unit width has been improved through introduction of mobility enhancement techniques. The influence of external resistance becomes more pronounced for large-dimensional RF transistors due to severe IR drop. Such improved current drivability and large external resistance is responsible for dc performance (g_m) degradation and, eventually, cutoff frequency (f_T) degradation. Local stress effects associated with silicon nitride capping layer and STI stress have been investigated. f_T is largely affected by local stress change, i.e., g_m degradation at minimal gate poly (GP) pitch and gate-to-active spacing, f_T is dominated by increased parasitic capacitance (C_gb) with increasing GP pitch and gate-to-active spacing. Above 10% improvement in f_T has been observed through layout optimization for C_gb reduction by increasing the transistor active-to-SC spacing.     

一个开关电容电路的模拟和优化程序

本文介绍了一个以分析开关电容(SC)电路为目的面向用户的通用程序。该程序可以完成对SC电路的时域、频域和灵敏度模拟,可以对SC电路进行多目标优化,并可以求得SC电路的传输极点,且对电路的输入信号、开关序列、网络拓扑没有限制,文中提出了在改进节点法基础上求出电路传输极点的方法,以贡献的方式建立求传输函数对电容比的灵敏度方程,通过线性变换求得对电容比的灵敏度的方法和SC电路的多目标优化方法。最后给出了用该程序对SC电路进行模拟和优化的两个算例。     

SC网络分析的标度-Pauper算法

本文讨论了一种SC网络的频域分析方法,首先探讨了SC网络的标度性质,根据这条性质和特定的Pauper算法,可以用积木块法将SC网络用一个由放大器、电阻和电容组成的连续时间模拟电路来等效.于是,SC网络的频率响应和灵敏度可以调用现有的标准模拟电路分析程序算出,而无须编制专用程序,与已有方法比较,本方法具有计算速度快的优点。     

Emulating DC constant power load: a robust sliding mode control approach

This article presents emulation of a programmable power electronic, constant power load (CPL) using a dc/dc step-up (boost) converter. The converter is controlled by a robust sliding mode controller (SMC). A novel switching surface is proposed to ensure a required power sunk by the converter. The proposed dc CPL is simple in design, has fast dynamic response and high accuracy, and offers an inexpensive alternative to study converters for cascaded dc distribution power system applications. Furthermore, the proposed CPL is sufficiently robust against the input voltage variations. A laboratory prototype of the proposed dc CPL has been developed and validated with SMC realised through OPAL-RT platform. The capability of the proposed dc CPL is confirmed via experimentations in varied scenarios.