A heterogeneous multiprocessor architecture for flexible mediaprocessing

Eclipse is a scalable architecture template for designing data-dependent stream-processing subsystems of media-processing SoCs. It combines application configuration flexibility with the efficiency of function-specific coprocessors that concurrently execute the tasks of one or more applications     

A layered architecture for flexible Web service invocation

Web service composition is emerging as an interesting approach to integrate business applications and create intra‐organizational business processes. Single Web services are combined to create a complex Web service that will realize the process business logic. Once the process is created, it is executed by an orchestration engine that invokes individual Web services in the correct order. However, Web services composing the workflow sometimes become unavailable during the run‐time phase, blocking process execution. This paper describes an architecture that allows the flexible orchestration of business processes. With this approach, Web services composing the process can be automatically substituted with other compatible Web services during process execution. A methodology is defined to evaluate Web service compatibility based on interface matching, in order to select substitutable Web services. Copyright © 2005 John Wiley & Sons, Ltd.     

A distributed architecture for efficient Web service discovery

Although the definition of service-oriented architecture (SOA) included the presence of a service registry from the beginning, the first implementations (e.g., UDDI) did not really succeed mainly because of security and governance issues. This article tackles the problem by introducing DREAM (Distributed Registry by ExAMple): a publish/subscribe-based solution to integrate existing, different registries, along with a match-making approach to ease the publication and retrieval of services. DREAM fosters the interoperability among registry technologies and supports UDDI, ebXML Registry, and other registries. The publish/subscribe paradigm allows service providers to decide the services they want to publish, and requestors to be informed of the services that satisfy their interests. As for the match-making, DREAM supports different ways to evaluate the matching between published and required services. Besides presenting the architecture of DREAM and the different match-making opportunities, the article also describes the experiments conducted to evaluate proposed solutions.     

光纤通道交换机体系结构的设计

由于光纤通道的高速性,光纤通道交换机面临着现有普通交换机设计没有的问题.针对这些问题,从体系结构的选择,交换机的组成框架.主要部件的功能和结构等方面论述扣分析了光纤通道交换机硬件的总体设计.     

Silicon-aware distributed switch architecture for on-chip networks

It is well-known that current Chip MultiProcessor (CMP) and high-end MultiProcessor System-on-Chip (MPSoC) designs are growing in their number of components. Networks-on-Chip (NoC) provide the required connectivity for such CMP and MPSoC designs at reasonable costs. As technology advances, links become the critical component in the NoC due to their long delay and power consumption, becoming unacceptable for long global interconnects.In this paper we present a new switch architecture that reduces the negative impact of links on the NoC. We call our proposal distributed switch. The distributed switch spreads the circuitry of the switch onto the links. Thus, packets are buffered, routed, and forwarded at the same time they are crossing the link.Distributing a modular switch onto the link improves the trade off between the power consumption and the operating frequency of the entire network. On the contrary, area resources are increased. Additionally, the distributed switch presents better fault tolerance and process variation behavior with respect to a non-distributed switch.     

A highly flexible,distributed multiprocessor architecture for network processing

Network processors (NPs) are an emerging field of programmable processors that are optimized to implement data plane packet processing networking functions. Unlike the general-purpose CPUs that rely heavily on caching for improving performance, the lack of locality in packet processing and need for high-performance I/O have forced designers to come up with innovative architectures that can hide memory latency while still processing packets at high data rates. Most of these NPs use some type of multiprocessing in combination with a hierarchy of memory types to achieve high performance. In addition, to keep up with packets arriving at high data rates over multiple incoming media interfaces, an NP must perform fast I/O and memory operations such as packet storage, table lookup, and extraction of fields in packet headers. We describe an architecture that uses a combination of distributed memory architecture and one or more multithreaded processors to achieve the necessary performance. We describe the challenges in programming such a processor including the issues related to consistency and maintaining packet ordering. We also present a programming model for generic network applications that uses software pipelines. We then demonstrate the use of the programming model in implementing two applications, namely, mapping traffic management algorithms onto a multithreaded architecture and an implementation of a media gateway based on voice-over-AAL2.     

A programmable array processor architecture for flexible approximate string matching algorithms

Approximate string matching problem is a common and often repeated task in information retrieval and bioinformatics. This paper proposes a generic design of a programmable array processor architecture for a wide variety of approximate string matching algorithms to gain high performance at low cost. Further, we describe the architecture of the array and the architecture of the cell in detail in order to efficiently implement for both the preprocessing and searching phases of most string matching algorithms. Further, the architecture performs approximate string matching for complex patterns that contain don’t care, complement and classes symbols. We also simulate and evaluate the proposed architecture on a field programmable gate array (FPGA) device using the JHDL tool for synthesis and the Xilinx Foundation tools for mapping, placement, and routing. Finally, our programmable implementation achieves about 8–340 times faster execution than a desktop computer with a Pentium 4 3.5 GHz for all algorithms when the length of the pattern is 1024.     

A router architecture for flexible routing and switching inmultihop point-to-point networks

Modern parallel and distributed applications have a wide range of communication characteristics and performance requirements. These diverse characteristics affect the performance and suitability of particular routing and switching policies in multihop point-to-point networks. In this paper, we identify a core set of architectural features necessary for flexible selection and implementation of multiple routing and switching schemes. Using this, we present a flexible router whose routing and switching policies can be tailored to the application, allowing the network to meet these diverse needs. By dedicating a small programmable processor to each incoming link, we can implement wormhole, virtual cut-through, and packet switching, as well as hybrid switching schemes, each under a variety of unicast and multicast routing algorithms. In addition, a flexible router can support several applications or traffic types simultaneously, enabling better support of applications with multiple traffic classes. We have designed, implemented, and fabricated the Programmable Routing Controller (PRG). Cycle-level simulations of mesh-connected PRCs also demonstrate that flexible routing and switching can significantly enhance application performance     

H2CM: A holonic architecture for flexible hybrid control systems

Several studies typically arise from the interaction of discrete planning algorithms or control and continuous processes, normally called hybrid control systems. It consists in three distinct levels, the controller, the plant and the interface. Hybrid control systems are conventionally modeled by switching patterns using the whole system instead of atomic resource. Therefore, the reconfiguration process is complex because it must take into account the system as a whole, making the hybrid control systems inflexible and more susceptible to uncertainties. The need for flexibility thus leads several teams to investigate the application of holonic paradigm to hybrid control systems. The objective of this paper is to demonstrate the possibility to apply almost directly a holonic discrete-event based reference architecture to hybrid control systems. A case study of industrial electricity generation process was taken, specifically a combined cycle plant (CCP) for verifying the proper operation of the proposed architecture.     

An architecture for flexible scheduling in Profibus networks

Recently, much attention has been given to the need to endow industrial communication networks used in real-time systems with flexible scheduling. This allows control systems to adapt to the variations in the requirements of traffic generated by modifications in the environment of the system, or changes in its structure. Another active area is multimedia transmission in industrial environments. In this paper, a flexible scheduling system for Profibus networks is presented. There are two objectives. Firstly to allow the characteristics of real-time traffic to deal in run time in a fieldbus and secondly to enable the scheduling of video traffic for industrial monitoring purposes. The system proposed allows, with regard to traditional Profibus MAC/scheduling, rapid dynamic adaptation to the new requirements, minimizing the bandwidth necessary for its management and maximizing the use of the available bandwidth. As a result there is an improvement in quality of video sources as well as the number of video sources, which can co-exist with the control traffic, without affecting its QoS.     

A robust and flexible optimization technique for efficient shrinking of MEMS accelerometers

We report on the automated determination of the minimal required area of a MEMS accelerometer conforming to given specifications. For a realistic nonlinear sensor model this process is only possible by the use of numerical optimization, which typically has the difficulty of finding the global minimum or is time consuming. A miniaturized sensor’s chip size reduces manufacturing cost and leads to more competitive package sizes and new, unforeseen applications. Size reduction is especially important for consumer applications like mobile phones and navigation devices, where an increasing demand for accelerometers is expected in the near future. With further miniaturization of a sensor it is increasingly important to find the optimal design in order to use chip area as efficiently as possible. To achieve a robust and flexible automated area reduction without loss of functionality we uniquely combine available genetic and gradient-based optimization algorithms. Furthermore, we reduce the model complexity, apply different scaling techniques and adapt optimization algorithm settings. The application to a capacitive and a piezoresistive MEMS accelerometer shows significant improvement of efficiency when compared with the use of currently available optimization algorithms.     

A distributed architecture for efficient parallelization and computation of knowledge-based temporal abstractions

Today, data storage capabilities as well as computational power are rapidly increasing. On the one hand, this improvement makes it possible to generate and store a great amount of temporal (time-oriented) data for future query, analysis and discovery of new knowledge. On the other hand, systems and experts are encountering new problems in processing this increased amount of data. The rapid growth in stored time-oriented data necessitates the development of new methods for handling, processing, and interpreting large amounts of temporal data. One approach is to use an automatic summarization process based on predefined knowledge, such the Knowledge-Based Temporal-Abstraction (KBTA) method. This method enables one to summarize and reduce the amount of raw data by creating higher level interpretations based on predefined domain knowledge. Unfortunately, the task of temporal abstraction is inherently computationally expensive, especially when an enormous volume of multivariate data has to be handled and when complex patterns need to be considered. In this research, we address the scalability problem of a temporal-abstraction task that involves processing significantly large amounts of raw data. We propose a new computational framework, the Distributed KBTA (DKBTA), which efficiently distributes the abstraction process among several parallel computational nodes, in order to achieve an acceptable computation time. The DKBTA framework distributes the temporal-abstraction process along one or more computational axes, each of which enables parallelization of one or more temporal-abstraction tasks into which the main temporal-abstraction task is decomposed, such as by different subject groups, concepts types, or abstraction types. We have implemented the DKBTA framework and have evaluated it in a preliminary fashion in the medical and the information security domains, with encouraging results. In our small-scale evaluation, only distribution along the subjects axis and sometimes along the concept-type axis seemed to consistently enhance performance, and only for computations involving individual subjects and not functions of sets of subjects; but this observation might depend on the number of processing units. Additionally, since the communication between the processing units was based on the TCP protocol, we could not observe any speedup even when using two processing units on the same machine. In our further evaluations we plan to use a shared memory architecture in order to exchange data between processing units.     

FASA: A software architecture and runtime framework for flexible distributed automation systems

Modern automation systems have to cope with large amounts of sensor data to be processed, stricter security requirements, heterogeneous hardware, and an increasing need for flexibility. The challenges for tomorrow’s automation systems need software architectures of today’s real-time controllers to evolve.This article presents FASA, a modern software architecture for next-generation automation systems. FASA provides concepts for scalable, flexible, and platform-independent real-time execution frameworks, which also provide advanced features such as software-based fault tolerance and high degrees of isolation and security. We show that FASA caters for robust execution of time-critical applications even in parallel execution environments such as multi-core processors.We present a reference implementation of FASA that controls a magnetic levitation device. This device is sensitive to any disturbance in its real-time control and thus, provides a suitable validation scenario. Our results show that FASA can sustain its advanced features even in high-speed control scenarios at 1 kHz.     

Time efficient systolic architecture for matrix vector multiplication

A modified systolic array architecture for performing matrix vector operation is presented. The vector to be transformed is represented at bit level as a matrix having only binary elements which are multiplied with a weight vector whose ith element is 2ⁱ⁻¹. This modification permits pipelining of verious carry-save adder stages of the multiplier and thereby permitting increased data throughput. It is shown that the throughput rate of the proposed design is independent of the vector size and the word length in contrast to the previously reported architecture by Kung and Liserson (1978). Detailed area time complexity analysis of the proposed design has also been carried out.     

快速高效的半像素运动估计算法的VLSI实现

提出了半像素运动估计算法的硬件实现方案,该方案可有效地提高视频编码的速度,耗费较低的硬件资源,减小处理器的面积。     

A flexible architecture for distributed knowledge based systems with nomadic access through handheld devices

Nowadays any Knowledge Based System (KBS) realization needs of intercommunication among distributed components and to use non-connected and distributed data sources, which poses several challenges to the classical Artificial Intelligence field of KBS.

The multiagent paradigm and the use of ontologies are considered to be suitable tools to face the problems of designing and developing today KBS. On the other hand, using such networked KBS through handheld devices makes more efficient exploitation and interaction with the system.

This paper presents an open and flexible architecture for a distributed KBS and an application of it to construct a system for Psychological Disorders consulting, the so called PDA² (Psychological Disorder Assistant through PDA). We analyze the main features of the architecture as well as the agent tools we may use to construct it. Additionally, we present a support ontology for Psychological Disorders.     

A fast and efficient two-phase sequential learning algorithm for spatial architecture neural network

Spatial architecture neural network (SANN), which is inspired by the connecting mode of excitatory pyramidal neurons and inhibitory interneurons of neocortex, is a multilayer artificial neural network and has good learning accuracy and generalization ability when used in real applications. However, the backpropagation-based learning algorithm (named BP-SANN) may be time consumption and slow convergence. In this paper, a new fast and accurate two-phase sequential learning scheme for SANN is hereby introduced to guarantee the network performance. With this new learning approach (named SFSL-SANN), only the weights connecting to output neurons will be trained during the learning process. In the first phase, a least-squares method is applied to estimate the span-output-weight on the basis of the fixed randomly generated initialized weight values. The improved iterative learning algorithm is then used to learn the feedforward-output-weight in the second phase. Detailed effectiveness comparison of SFSL-SANN is done with BP-SANN and other popular neural network approaches on benchmark problems drawn from the classification, regression and time-series prediction applications. The results demonstrate that the SFSL-SANN is faster convergence and time-saving than BP-SANN, and produces better learning accuracy and generalization performance than other approaches.     

An efficient architecture for a transputer based vehicle simulator

This paper presents an efficient architecture for the rendering and display sections of a vehicle simulator prototype. The architecture for the rendering stage, which consists of three independent concurrent units, has been optimised to support the two-layer dynamic load balancing technique. The display stage has also been partitioned to facilitate parallel updating of the pixel data to the dual frame buffers. The design of the frame buffers and the interface logic to access them by direct memory access (DMA) controllers (via three common address and data buses) and the colour video controller are also presented. Simulation results show that the adoption of DMA based memory transfer between the local memory of the transputer nodes and the frame buffers can alleviate the communication bottleneck prevalent in an earlier prototype.     

A parallel fuzzy-controlled flexible manipulator using optical tip feedback

Investigation and development of a fuzzy-controlled highly non-linear two-axis manipulator with a single-flexible link using a novel patented optical tip displacement feedback is described. The controller comprises a parallel fuzzy supervisor that is used to alter the derivative term of a linear classical PD controller, which is updated in relation to the measured tip error and error rate.Implementation of the supervisory fuzzy controller is described using both serial and parallel operation on transputers.The design of the fuzzy rules was made with a modified closed-loop phase-plane method. The design approach results in a controller implementation that uses only 14 rules and is suitable for cheaper CPU-constrained and memory-challenged embedded processors.The benefits introduced by this procedure include a method to decide where and when the action takes effect in the controller and a greatly reduced rule base. The parallel operation achieved rise times of 0.033 s and settling times of 0.064 s for a payload of 0.7 kg considerably better than other workers did.An 128% increase in payload, 73.5% faster settling time and a reduction of steady-state error of over 50% were achieved using fuzzy control over its classical counterpart.     

Real-time compression architecture for efficient coding in autostereoscopic displays

Integral imaging is a promising technique for delivering high-quality three-dimensional content. However, the large amounts of data produced during acquisition prohibits direct transmission of Integral Image data. A number of highly efficient compression architectures are proposed today that outperform standard two-dimensional encoding schemes. However, critical issues regarding real-time compression for quality demanding applications are a primary concern to currently existing Integral Image encoders. In this work we propose a real-time FPGA-based encoder for Integral Image and integral video content transmission. The proposed encoder is based on a highly efficient compression algorithm used in Integral Imaging applications. Real-time performance is achieved by realizing a pipelined architecture, taking into account the specific structure of an Integral Image. The required memory access operations are minimized by adopting a systolic concept of data flow through the core processing elements, further increasing the performance boost. The encoder targets, real-time, broadcast-type high-resolution Integral Image and video sequences and performs three orders of magnitude faster than the analogous software approach.