A 32-GHz non-uniform distributed amplifier in 0.18-/spl mu/m CMOS

This letter presents a fully integrated distributed amplifier in a standard 0.18-/spl mu/m CMOS technology. By employing a nonuniform architecture for the synthetic transmission lines, the proposed distributed amplifier exhibits enhanced performance in terms of gain and bandwidth. Drawing a dc current of 45mA from a 2.2-V supply voltage, the fabricated circuit exhibits 9.5-dB pass-band gain with a bandwidth of 32GHz while maintaining good input and output return losses over the entire frequency band. With a compact layout technique, the chip size of the distributed amplifier including the testing pads is 940/spl times/860/spl mu/m/sup 2/.     

A 2.4-GHz RF sampling receiver front-end in 0.18-/spl mu/m CMOS

This paper presents an integrable RF sampling receiver front-end architecture, based on a switched-capacitor (SC) RF sampling downconversion (RFSD) filter, for WLAN applications in a 2.4-GHz band. The RFSD filter test chip is fabricated in a 0.18-/spl mu/m CMOS technology and the measurement results show a successful realization of RF sampling, quadrature downconversion, tunable anti-alias filtering, downconversion to baseband, and decimation of the sampling rate. By changing the input sampling rate, the RFSD filter can be tuned to different RF channels. A maximum input sampling rate of 1072 MS/s has been achieved. A single-phase clock is used for the quadrature downconversion and the bandpass operation is realized by a 23-tap FIR filter. The RFSD filter has an IIP/sub 3/ of +5.5 dBm, a gain of -1 dB, and more than 17 dB rejection of alias bands. The measured image rejection is 59 dB and the sampling clock jitter is 0.64 ps. The test chip consumes 47 mW in the analog part and 40 mW in the digital part. It occupies an area of 1 mm/sup 2/.     

A 24-GHz, +14.5-dBm fully integrated power amplifier in 0.18-/spl mu/m CMOS

A 24-GHz +14.5-dBm fully integrated power amplifier with on-chip 50-/spl Omega/ input and output matching is demonstrated in 0.18-/spl mu/m CMOS. The use of substrate-shielded coplanar waveguide structures for matching networks results in low passive loss and small die size. Simple circuit techniques based on stability criteria derived result in an unconditionally stable amplifier. The power amplifier achieves a power gain of 7 dB and a maximum single-ended output power of +14.5-dBm with a 3-dB bandwidth of 3.1 GHz, while drawing 100 mA from a 2.8-V supply. The chip area is 1.26 mm/sup 2/.     

A 2.4-GHz dual-mode 0.18-/spl mu/m CMOS transceiver for Bluetooth and 802.11b

High-level integration of the Bluetooth and 802.11b WLAN radio systems in the 2.4-GHz ISM band is demonstrated in scaled CMOS. A dual-mode RF transceiver IC implements all transmit and receive functions including the low-noise amplifier (LNA), 0-dBm power amplifier, up/down mixers, synthesizers, channel filtering, and limiting/automatic gain control for both standards in a single chip without doubling the required silicon area to reduce the combined system cost. This is achieved by sharing the frequency up/down conversion circuits in the RF section and performing the required baseband channel filtering and gain functions with just one set of reconfigurable channel filter and amplifier for both modes. A chip implemented in 0.18-/spl mu/m CMOS occupies 4/spl times/4 mm/sup 2/ including pad and consumes 60 and 40 mA for RX and TX modes, respectively. The dual-mode receiver exhibits -80-dBm sensitivity at 0.1% BER in Bluetooth mode and at 12-dB SNR in WLAN mode.     

A 0.25-/spl mu/m 20-dBm 2.4-GHz CMOS power amplifier with an integrated diode linearizer

A 2.4-GHz CMOS power amplifier (PA) with an output power 20 dBm using 0.25-/spl mu/m 1P5M standard CMOS process is presented. The PA uses an integrated diode connected NMOS transistor as a diode linearizer. It is believed that this is the first reported use of the diode linearization technique in CMOS PA design. It shows effective improvement in linearity from gain compression and ACPR measured results. Measurements are performed by using an FR-4 PCB test fixture. The fabricated power amplifier exhibits an output power of 20 dBm and a power-added efficiency as high as 28%. The obtained PA performances demonstrate the standard CMOS process potential for medium power RF amplification at 2.4 GHz wireless communication band.     

A matrix amplifier in 0.18-/spl mu/m SOI CMOS

A fully integrated matrix amplifier with two rows and four columns (2-by-4) fabricated in a three-layer metal 0.18-/spl mu/m silicon-on-insulator (SOI) CMOS process is presented. It exhibits an average pass-band gain of 15 dB and a unity-gain bandwidth of 12.5 GHz. The input and output ports are matched to 50 /spl Omega/ using m-derived half sections; the measured S/sub 11/ and S/sub 22/ values exceed -7 and -12 dB, respectively. Integrated in 2.0/spl times/2.9mm/sup 2/, it dissipates 233.4 mW total from 2.4- and 1.8-V power supplies.     

A 1.8-V 2.4/5.15-GHz dual-band LCVCO in 0.18-/spl mu/m CMOS technology

A dual band, fully integrated, low phase-noise and low-power LC voltage-controlled oscillator (VCO) operating at the 2.4-GHz industrial scientific and medical band and 5.15-GHz unlicensed national information infrastructure band has been demonstrated in an 0.18-/spl mu/m CMOS process. At 1.8-V power supply voltage, the power dissipation is only 5.4mW for a 2.4-GHz band and 8mW for a 5.15-GHz band. The proposed VCO features phase-noise of -135dBc/Hz at 3-MHz offset frequency away from the carrier frequency of 2.74GHz and -126dBc/Hz at 3-MHz offset frequency away from 5.49GHz. The oscillator is tuned from 2.2 to 2.85GHz in the low band (2.4-GHz band) and from 4.4 to 5.7GHz in the high band (5.15-GHz band).     

A 5.9-GHz voltage-controlled ring oscillator in 0.18-/spl mu/m CMOS

This paper presents the design of three- and nine-stage voltage-controlled ring oscillators that were fabricated in TSMC 0.18-/spl mu/m CMOS technology with oscillation frequencies up to 5.9 GHz. The circuits use a multiple-pass loop architecture and delay stages with cross-coupled FETs to aid in the switching speed and to improve the noise parameters. Measurements show that the oscillators have linear frequency-voltage characteristics over a wide tuning range, with the three- and nine-stage rings resulting in frequency ranges of 5.16-5.93 GHz and 1.1-1.86 GHz, respectively. The measured phase noise of the nine-stage ring oscillator was -105.5 dBc/Hz at a 1-MHz offset from a 1.81-GHz center frequency, whereas the value for the three-stage ring oscillator was simulated to be -99.5 dBc/Hz at a 1-MHz offset from a 5.79-GHz center frequency.     

Ultra low power 2.4-GHz 0.35-/spl mu/m CMOS dual-modulus prescaler design

This letter presents the design and implementation of a dual-modulus (64/65) prescaler based upon the phase-switching technique. Low power consumption is achieved by using one dynamic flip-flop in the full-speed divide-by-four circuit and no power-hungry synchronizing circuits to tackle the glitch problem. The proposed design is fabricated using 0.35-/spl mu/m standard CMOS process and is measured to operate from 2.08-2.66GHz with power dissipation of less than 1mW.     

A 40-GHz frequency divider in 0.18-/spl mu/m CMOS technology

An analysis of regenerative dividers predicts the required phase shift or selectivity for proper operation. A divider topology is introduced that employs resonance techniques by means of on-chip spiral inductors to tune out the device capacitances. Configured as two cascaded /spl divide/2 stages, the circuit achieves a frequency range of 2.3 GHz at 40 GHz while consuming 31 mW from a 2.5-V supply.     

A 24-GHz 3.9-dB NF low-noise amplifier using 0.18 /spl mu/m CMOS technology

A 24-GHz low-noise amplifier (LNA) was designed and fabricated in a standard 0.18-/spl mu/m CMOS technology. The LNA chip achieves a peak gain of 13.1 dB at 24 GHz and a minimum noise figure of 3.9 dB at 24.3 GHz. The supply voltage and supply current are 1 V and 14 mA, respectively. To the author's knowledge, this LNA demonstrates the lowest noise figure among the reported LNAs in standard CMOS processes above 20 GHz.     

0.18-/spl mu/m CMOS push-pull power amplifier with antenna in IC package

A novel architecture of power amplifier with antenna implemented in a ceramic ball grid array (CBGA) package is presented. The monolithic power amplifier designed in a standard 0.18- /spl mu/m CMOS technology offers 19.5 dBm maximum output power at 5.2 GHz to the antenna with the PAE of 32%. The antenna integrated in the CBGA package achieves impedance bandwidth of 3.86% and gain of 2 dBi at 5.2 GHz. Results demonstrate the feasibility of using this innovative configuration to the design of single-chip 5 GHz transmitter front-end.     

Highly linear 0.18-/spl mu/m CMOS power amplifier with deep n-Well structure

The linearity of a 0.18-/spl mu/m CMOS power amplifier (PA) is improved by adopting a deep n-well (DNW). To find the reason for the improvement, bias dependent nonlinear parameters of the test devices are extracted from a small-signal model and a Volterra series analysis for an optimized nMOS PA with a proper matching circuit is carried out. From the analysis, it is revealed that the DNW of the nMOS lowers the harmonic distortion generated from the intrinsic gate-source capacitance (C/sub gs/), which is the dominant nonlinear source, and partially from drain junction capacitance (C/sub jd/). Single-ended and differential PAs for 2.45-GHz WLAN are designed and fabricated using a 0.18-/spl mu/m standard CMOS process. The single-ended PA with the DNW improves IMD3 and IMD5 about 5 dB with identical power performances, i.e., 20 dBm of P/sub out/, 18.7 dB of power gain and 31% of power-added efficiency (PAE) at P/sub 1dB/. The IMD3 and IMD5 are below -40 dBc and -47dBc, respectively. The differential PA with the DNW also shows about 7 dB improvements of IMD3 and IMD5 with 20.2 dBm of P/sub out/, 18.9 dB of power gain and 35% of PAE at P/sub 1dB/. The IMD3 and IMD5 are below -45 dB and -57 dBc, respectively. These performances of the linear PAs are state-of-the-art results.     

A 1-V transformer-feedback low-noise amplifier for 5-GHz wireless LAN in 0.18-/spl mu/m CMOS

A low-noise amplifier (LNA) uses low-loss monolithic transformer feedback to neutralize the gate-drain overlap capacitance of a field-effect transistor (FET). A differential implementation in 0.18-/spl mu/m CMOS technology, designed for 5-GHz wireless local-area networks (LANs), achieves a measured power gain of 14.2 dB, noise figure (NF, 50 /spl Omega/) of 0.9 dB, and third-order input intercept point (IIP3) of +0.9 dBm at 5.75 GHz, while consuming 16 mW from a 1-V supply. The feedback design is benchmarked to a 5.75-GHz cascode LNA fabricated in the same technology that realizes 14.1-dB gain, 1.8-dB NF, and IIP3 of +4.2 dBm, while dissipating 21.6 mW at 1.8 V.     

A 0.3-25-GHz ultra-wideband mixer using commercial 0.18-/spl mu/m CMOS technology

An ultra-wideband mixer using standard complementary metal oxide semiconductor (CMOS) technology was first proposed in this paper. This broadband mixer achieves measured conversion gain of 11 /spl plusmn/ 1.5 dB with a bandwidth of 0.3 to 25 GHz. The mixer was fabricated in a commercial 0.18-/spl mu/m CMOS technology and demonstrated the highest frequency and bandwidth of operation. It also presented better gain-bandwidth-product performance compared with that of GaAs-based HBT technologies. The chip area is 0.8 /spl times/ 1 mm/sup 2/.     

A dual-band 5.15-5.35-GHz, 2.4-2.5-GHz 0.18-/spl mu/m CMOS transceiver for 802.11a/b/g wireless LAN

A single-chip dual-band 5.15-5.35-GHz and 2.4-2.5-GHz zero-IF transceiver for IEEE 802.11a/b/g WLAN systems is fabricated on a 0.18-/spl mu/m CMOS technology. It utilizes an innovative architecture including feedback paths that enable digital calibration to help eliminate analog circuit imperfections such as transmit and receive I/Q mismatch. The dual-band receive paths feature a 4.8-dB (3.5-dB) noise figure at 5.25 GHz (2.45 GHz). The corresponding sensitivity at 54 Mb/s operation is -76 dBm for 802.11a and -77 dBm for 802.11g, both referred at the input of the chip. The transmit chain achieves output 1-dB compression at 6 dBm (9 dBm) at 5 GHz (2.4 GHz) operation. Digital calibration helps achieve an error vector magnitude (EVM) of -33 dB (-31 dB) at 5 GHz (2.4 GHz) while transmitting -4 dBm at 54Mb/s. The die size is 19.3 mm/sup 2/ and the power consumption is 260 mW for the receiver and 320 mW (270 mW) for the transmitter at 5 GHz (2.4 GHz) operation.     

A Bluetooth radio in 0.18-/spl mu/m CMOS

This paper describes the results of an implementation of a Bluetooth radio in a 0.18-/spl mu/m CMOS process. A low-IF image-reject conversion architecture is used for the receiver. The transmitter uses direct IQ-upconversion. The VCO runs at 4.8-5.0 GHz, thus facilitating the generation of 0/spl deg/ and 90/spl deg/ signals for both the receiver and transmitter. By using an inductor-less LNA and the extensive use of mismatch simulations, the smallest silicon area for a Bluetooth radio implementation so far can be reached: 5.5 mm/sup 2/. The transceiver consumes 30 mA in receive mode and 35 mA in transmit mode from a 2.5 to 3.0-V power supply. As the radio operates on the same die as baseband and SW, the crosstalk-on-silicon is an important issue. This crosstalk problem was taken into consideration from the start of the project. Sensitivity was measured at -82 dBm.     

A 0.18-/spl mu/m CMOS bioluminescence detection lab-on-chip

The paper describes a bioluminescence detection lab-on-chip consisting of a fiber-optic faceplate with immobilized luminescent reporters/probes that is directly coupled to an optical detection and processing CMOS system-on-chip (SoC) fabricated in a 0.18-/spl mu/m process. The lab-on-chip is customized for such applications as determining gene expression using reporter gene assays, determining intracellular ATP, and sequencing DNA. The CMOS detection SoC integrates an 8 /spl times/ 16 pixel array having the same pitch as the assay site array, a 128-channel 13-bit ADC, and column-level DSP, and is fabricated in a 0.18-/spl mu/m image sensor process. The chip is capable of detecting emission rates below 10/sup -6/ lux over 30 s of integration time at room temperature. In addition to directly coupling and matching the assay site array to the photodetector array, this low light detection is achieved by a number of techniques, including the use of very low dark current photodetectors, low-noise differential circuits, high-resolution analog-to-digital conversion, background subtraction, correlated multiple sampling, and multiple digitizations and averaging to reduce read noise. Electrical and optical characterization results as well as preliminary biological testing results are reported.     

24 GHz low-noise amplifier in 0.18 /spl mu/m CMOS technology

A 24 GHz monolithic low-noise amplifier (LNA) is implemented in a standard 0.18 /spl mu/m CMOS technology. Measurements show a gain of 12.86 dB and a noise figure of 5.6 dB at 23.5 GHz. The input and output return losses are better than 11 dB and 22 dB across the 22-29 GHz span, respectively. The operation frequency of 24 GHz is believed to be the highest reported for LNA in a standard CMOS technology.     

A 3-to-8-GHz fast-hopping frequency synthesizer in 0.18-/spl mu/m CMOS technology

A frequency synthesizer incorporating one single-sideband (SSB) mixer generates seven bands of clock distributed from 3 to 8GHz with 1-ns switching time. An efficient frequency synthesizing technique producing balanced bands around one center frequency is employed, and the SSB mixer uses double degeneration topology to increase the linearity. Fabricated in 0.18-/spl mu/m CMOS technology, this circuit achieves a sideband rejection of 37 dB while consuming 48 mW from a 2.2-V supply.