An Optically Clocked Transistor Array for High-Speed Asynchronous Label Swapping: 40 Gb/s and Beyond

We describe the development of an optically clocked transistor array (OCTA) interface device for label swapping high-speed asynchronous burst optical packets. The OCTA integrates the three critical functions of serial-to-parallel (SP) conversion, parallel-to-serial (PS) conversion, and clock-pulse generation into a simple optoelectronic integrated circuit (OEIC) to create a single-chip interface between the input/output baseband optical labels and a CMOS label processor. The result is a high-performance label swapping solution which is compact and low power. In this paper, a detailed investigation of the design and optimization of the circuit is first performed, followed by testing of device stability under subsystem operating conditions. Finally, demonstrations of single-channel switching speeds allowing greater than 100-Gb/s operation, 40-Gb/s SP and PS conversion with an eight-channel OCTA, and error-free label swapping of 10-Gb/s asynchronous optical packets with a prototype label swapper module are described.     

Self-Clocked All-Optical Add/Drop Multiplexer for Asynchronous CDMA Ring Networks

In this paper, we demonstrate a novel self-clocked code-drop unit for incoherent optical code-division multiple-access (CDMA) networks. The unit is based on an all-optical thresholder with internal wavelength conversion that creates a control signal for the drop gate from the incoming data stream. This architecture does not require an external clock signal for drop operation and can be used in asynchronous ring networks. The proposed unit is experimentally demonstrated for two-dimensional time-wavelength optical CDMA codes at a bit rate of 2.5 Gbit/s with two different types of drop gates: terahertz optical asymmetric multiplexer and nonlinear fiber-based loop mirror. Error-free operation is achieved in both configurations. The development of a self-clocked add/drop multiplexer demonstrates a novel concept of asynchronous node operation in multiple access networks.      

Multirate payload switching using a swappable optical carrier suppressed label in a packet-switched DWDM optical network

Optical packets with multirate payloads have been demonstrated for optical label switching (OLS) and transport in a multihop dense wavelength-division-multiplexed (DWDM) optical network with over 200 km fiber and a low-power penalty for the first time. The key functions for label generation, swapping, and switching have been successfully realized.     

160 Gb/s variable length packet/10 Gb/s-label all-optical label switching with wavelength conversion and unicast/multicast operation

We report on the first demonstration of all-optical label switching (AOLS) with 160 Gb/s variable length packets and 10 Gb/s optical labels. This result demonstrates the transparency of AOLS techniques from previously demonstrated 2.5 Gb/s to this 160 Gb/s demonstration using a common routing and packet lookup framework. Packet forwarding/conversion, optical label erasure/re-write and signal regeneration at 160 Gb/s is achieved using a WDM Raman enhanced all-optical fiber cross-phase modulation wavelength converter. It is also experimentally shown that this technique enables packet unicast and multicast operation at 160 Gb/s. The packet bit-error-rate is measured for all optical label switched 16 /spl times/ 10 Gb/s channels and error free operation is demonstrated after both label swapping and packet forwarding.     

On-the-Fly All-Optical Contention Resolution for NRZ and RZ Data Formats Using Packet Envelope Detection and Integrated Optical Switches

We present a packet-by-packet contention resolution scheme that combines packet detection, optical space switching, and wavelength conversion performed in the optical domain by integrated optical switches. The packet detection circuit provides the control signals required to deflect and wavelength-convert the contending packets so that all the packets are forwarded to the same output without any collision or packet droppings. We demonstrate the compatibility of the scheme with both nonreturn-to-zero (NRZ) and return-to-zero (RZ) modulation formats by recording error-free operation for 10-Gb/s NRZ and 40-Gb/s RZ packet-mode traffic     

Performance of fiber delay‐line buffers in asynchronous packet‐based optical switching networks with wavelength conversion

A major challenge in asynchronous packet‐based optical networks is packet contention, which occurs when two or more packets head to the same output at the same time. To resolve contention in the optical domain, two primary approaches are wavelength conversion and fiber delay line (FDL) buffering. In wavelength conversion, a contending packet can be converted from one wavelength to another in order to avoid conflict. In FDL buffering, contending packets can be delayed for a fixed amount of time. While the performance of wavelength conversion and FDL buffering has been evaluated extensively in synchronous networks with fixed‐sized packets, in this paper, we study the performance of FDL buffers in asynchronous packet‐based optical networks with wavelength conversion. An analytical model is proposed to evaluate the performance in terms of packet loss probability and average delay. Extensive simulation and analytical results show that, with appropriate settings, FDL buffers can perform much better in switches with wavelength conversion than in switches with no conversion. Copyright © 2014 John Wiley & Sons, Ltd.     

Generalized guaranteed rate scheduling algorithms: a framework

In this paper, we define a class of generalized guaranteed rate (GR) scheduling algorithms that includes algorithms which allocate a variable rate to the packets of a flow. We define work-conserving generalized virtual clock, packet-by-packet generalized processor sharing, and self-clocked fair queueing scheduling algorithms that can allocate a variable rate to the packets of a flow. We also define scheduling algorithms suitable for servers where packet fragmentation may occur. We demonstrate that if a class of rate controllers is employed for a flow in conjunction with any scheduling algorithm in GR, then the resulting non-work-conserving algorithm also belongs to GR. This leads to the definition of several non-work-conserving algorithms. We then present a method for deriving the delay guarantee of a network of servers when: (1) different rates are allocated to packets of a flow at different servers along the path and the bottleneck server for each packet may be different, and (2) packet fragmentation and/or reassembly may occur. This delay guarantee enables a network to provide various service guarantees to flows conforming to any specification. We illustrate this by utilizing delay guarantee to derive delay bounds for flows conforming to leaky bucket, exponentially bounded burstiness, and flow specification. Our method for determining these bounds is valid in internetworks and leads to tighter results     

On wavelength-converted optical routers employing flow routing

Optical networks have been extensively investigated in recent years to provide high capacity for the Internet traffic. Among them the optical packet-switching network deploying buffering, wavelength conversion and multipath routing could be the most suitable one. It cannot only provide high capacity transport for Internet traffic but also achieve high utilization of the network resources. However due to the packet-oriented routing and switching, such a network can result in a large amount of packets out-of-order, packet loss and/or with various delays upon arriving at end systems, causing TCP flows that comprise those packets corrupted. Large amount of corrupted flows can increase the burstiness of the Internet traffic and cause higher-layer protocol to malfunction. This paper presents a novel routing and switching method for optical IP networks-flow routing. Without using a complicate control mechanism flow routing deals with packet-flows to reduce the amount of corrupted flows. The performance of the wavelength-converted optical flow router is investigated, based on a novel analytical model. A performance metric, i.e., good-throughput, is used, measuring the ratio of the amount of packets comprised in the noncorrupted flows to total amount of packets. Comparing with optical packet-switching routers, a remarkable improvement of good-throughput can be obtained by using optical flow routers. More important, using wavelength conversion can greatly improve the good-throughput of optical flow routers.     

Efficient double intracavity-contacted vertical-cavitysurface-emitting lasers with very low-threshold and low-powerdissipation designed for cryogenic applications

Efficient continuous wave operation of oxide-confined double intracavity-contacted InGaAs-GaAs vertical-cavity surface-emitting lasers (VCSEL's) with low-threshold voltage, low-threshold current and low-power dissipation has been achieved over a wide range of cryogenic temperatures (77 K-250 K). Low operating voltages were obtained by routing current through two intracavity contacts to bypass both distributed Bragg reflector (DBR) mirrors, while lower optical losses were achieved by using undoped DBR mirrors with abrupt heterointerfaces. This resulted in low operating voltages (<1.5 V), submilliampere threshold currents (I_th~0.15 mA), low-power dissipation (~0.21 mW at threshold) and a high power conversion efficiency (η _eff=31%)     

Ultrafast all-optical pattern matching using differential spin excitation and its application to bypass/drop self-routing for asynchronous optical packets

This paper presents a novel scheme for ultrafast all-optical pattern matching using the differential spin excitation in semiconductor multiple quantum wells (MQWs). In a demonstration of an all-optical pattern matching between two 100-Gb/s 16-bit optical packets, the contrast ratio of the photodiode (PD) output from the pattern matcher, between the pattern matched and the pattern-unmatched cases, was more than four for packets with a 2-dB power fluctuation. As an application of the pattern matcher to optical-packet-switched ring networks, bypass/drop self-routing is demonstrated for asynchronous 100-Gb/s 32-bit optical packets with 8-bit labels. In the experiment, a label of an incoming packet was compared to a local address (LA) given to a node in the optical domain. By changing the pattern of the LA packet instead of that of the incoming packet, the pattern matching was carried out for packets with various kinds of patterns. The contrast ratio of the PD output was more than six for all patterns.     

All-Optical 3R Burst-Mode Reception at 40 Gb/s Using Four Integrated MZI Switches

We demonstrate an all-optical retime, reshape, reamplify (3R) burst-mode receiver (BMR) operating error-free with a 40-Gb/s variable-length asynchronous optical data packets that exhibit up to 9-dB packet-to-packet power variation. The circuit is completely based upon hybrid integrated Mach-Zehnder interferometric (MZI) switches as it employs four cascaded MZIs, each one performing a different functionality. The 3R burst-mode reception is achieved with the combination of two discrete all-optical subsystems. A reshape, reamplify BMR employing a single MZI is used first to perform power equalization of the incoming bursts and provide error-free data reception. This novel approach is experimentally demonstrated to operate error-free, even for a 9-dB dynamic range of power variation between bursty data packets and for a wide range of average input power. The obtained power-equalized data packets are then fed into a 3R regenerator to improve the signal quality by reducing the phase and amplitude jitter of the incoming data. This packet-mode 3R regenerator employs three MZIs that perform wavelength conversion, clock extraction, and data regeneration for every packet separately and operates at 40 Gb/s, exhibiting rms timing jitter reduction from 4 ps at the input to 1 ps at the output and a power penalty improvement of 2.5 dB     

A 557-mW, 2.5-Gbit/s SONET/SDH regenerator-section terminating LSIchip using low-power bipolar-LSI design

A regenerator-section terminating digital large-scale-integration chip for an STM-16 (2.5-Gbit/s synchronous optical network/synchronous digital hierarchy) regenerator has been developed using low-power bipolar technologies. The high-speed performance of bipolar devices enabled four or more chips, including a demultiplexer and a multiplexer, to be integrated into a single chip. The low-power dissipation of 557 mW, only about one-tenth that of previously reported chips, was achieved through the use of four design steps: one-chip integration architecture, power management, 2.5-V emitter-coupled logic, and power optimization     

Digital-IF WCDMA handset transmitter IC in 0.25-/spl mu/m SiGe BiCMOS

Implemented in a 0.25-/spl mu/m SiGe BiCMOS process, a highly integrated low-power transmitter IC (TxIC) is developed for wideband code-division multiple-access handset applications. Based on a digital-IF heterodyne architecture, it eliminates the external IF surface acoustic wave filter by adopting a meticulous frequency plan and a special-purpose second-order-hold D/A conversion scheme. The TxIC features a low-power high-speed D/A converter designed to drive a dominantly capacitive load. For the upconversion mixer and the RF amplifier, adaptive biases are designed to minimize the quiescent power consumption and to provide current boost only when needed. The TxIC achieves <1% EVM. It consumes 180 mW (3-V supply) for the maximum output power of +5 dBm and reduces to 120 mW during power backoff.     

Demonstration of 10 Gbit Ethernet/Optical-Packet Converter for IP Over Optical Packet Switching Network

We developed novel network interfaces, for example 10 Gbit Ethernet to 80 Gbit/s optical-packet (10 GbitE–80 GbitOP) or 80 Gbit/s optical-packet to 10 Gbit Ethernet (80 GbitOP–10 GbitE) converters (collectively called as 10 GbitE/80 GbitOP converters), to connect optical packet switching (OPS) networks with IP technology-based networks. By using newly developed arrayed burst-mode optical packet transmitters/receivers together, the 10 GbitE–80 GbitOP converter at the ingress edge node of the OPS network encapsulates an IP packet into an $80(8lambdatimes 10) {rm Gbit/s}$ dense wavelength division multiplexing (DWDM)-based optical packets and generates an optical label based on a lookup table and the destination addresses of the IP packet. The 80 GbitOP–10 GbitE converter at the egress edge node decapsulates the IP packet from the optical packet and generates a 10 GbitE frame accommodating the IP packet according to a lookup table. By using these network interface devices and OPS system based on multiple optical label processing, we achieved, for the first time, 74-km single-mode fiber transmission, switching, and buffering of $80(8lambdatimes 10) {rm Gbit/s}$ DWDM-based optical packets encapsulating almost 10 Gbit/s IP packets with error-free operation (IP packet loss rate $≪ 10^{-6}$).      

Field Trial of 640-Gbit/s-Throughput, Granularity-Flexible Optical Network Using Packet-Selective ROADM Prototype

Reconfigurable optical add/drop multiplexers (ROADMs) are able to provide flexible wavelength path provisioning in wavelength division multiplexing (WDM) networks. However, the capability of conventional ROADMs is limited to handling wavelength paths, and it does not support fine granularity in add/drop multiplexing of packets. Recently, we have proposed and demonstrated a packet-selective ROADM that combines an acoustooptic wavelength-tunable filter (AOTF) and an optical packet ADM (PADM) using optical code label processing. It provides more efficient utilization of wavelengths than conventional ROADMs. However, the bit rate of the demonstration was limited up to 10 Gbit/s. In this paper, we newly develop a label-selectivity-enhanced optical en/decoder, which allows the optical label recognition with 40-Gbit/s nonreturn-to-zero (NRZ) data packets, and a wide pass-band AOTF for 40-Gbit/s signals. Furthermore, we develop 640-Gbit/s throughput, packet-selective ROADM prototype, and demonstrate a field trial of granularity-flexible 3-node optical network over 173 km. error-free packet ADMs (error rate of under 10^-12) for all 16-wavelength channels at all nodes are obtained.     

Demonstration of photonically controlled GaAs digital/MMIC for RFoptical links

We report design, fabrication, and test of a monolithic GaAs optoelectronic integrated circuit (OEIC) implementing a broad-band optically driven digital/analog radio frequency (RF) interface. The integrated circuit (IC) was fabricated using a foundry-compatible enhancement/depletion metal-semiconductor field-effect transistor (MESFET) process with no added lithography steps. A single optical fiber carries externally amplitude modulated 0.85-μm light to the on-chip GaAs metal-semiconductor-metal interdigitated photodetector. RF as well as simultaneous digital information encoded at up to 10 Mb/s using a novel waveform set is transmitted over the fiber. The serial digital data is self-clocked into on-chip registers to control the RF signal chain, which includes a three-bit digital attenuator. The circuit operates in an asynchronous mode to detect digital and RF on the single optical-fiber input, control RF level, and transmit the 2-8-GHz RF to the IC's electrical output. Measurements characterizing the RF and digital performance of the IC as well as a demonstration of the full optoelectronic mixed-mode functioning of the IC are presented     

A 0.3-mW/Ch 1.25 V Piezo-Resistance Digital ROIC for Liquid-Dispensing MEMS

A low-power multichannel CMOS digital read-out IC (ROIC) for differential piezo-resistive sensing is presented as part of the positioning system of a liquid dispensing MEMS. New very low-voltage and single-battery compatible CMOS circuits are proposed for digital gain tuning, pre-amplification, and integrating A/D conversion. Overall low-power consumption is achieved by operating the key devices in subthreshold in order to prevent from heating the fluidic MEMS. A complete quad-channel ROIC has been integrated in 0.35- $mu{hbox {m}}$ CMOS 2-polySi 4-metal technology. The reported experimental results agree with the electrical simulations.      

High-speed buffer management for 40 gb/s-based photonic packet switches

We develop a method of high-speed buffer management for output-buffered photonic packet switches. The use of optical fiber delay lines is a promising solution to constructing optical buffers. The buffer manager determines packet delays in the fiber delay line buffer before the packets arrive at the buffer. We propose a buffer management method based on a parallel and pipeline processing architecture consisting of (log/sub 2/N+1) pipeline stages, where N is the number of ports of the packet switch. This is an expansion of a simple sequential scheduling used to determine the delays of arriving packets. Since the time complexity of each processor in the pipeline stages is O(1), the throughput of this buffer management is N times larger than that of the sequential scheduling method. This method can be used for buffer management of asynchronously arriving variable-length packets. We show the feasibility of a buffer manager supporting 128 /spl times/ 40 Gb/s photonic packet switches, which provide at least eight times as much throughput as the latest electronic IP routers. The proposed method for asynchronous packets overestimates the buffer occupancy to enable parallel processing. We show through simulation experiments that the degradation in the performance of the method resulting from this overestimation is quite acceptable.     

All-optical header processing system based on time-to-wavelength conversion for pure DPSK packets

Presented is a novel asynchronous all-optical header processing system for pure DPSK packets based on time-to-wavelength conversion of the header information that requires only four optical functions independently of the number of headers. Experimental results at 12.5 Gbit/s demonstrate that four DPSK headers are distinguished at four distinct outputs. The system requires low optical power, is highly scalable, and allows for potentially high-speed operation and photonic integration in a single chip.