Analog phase measuring circuit for digital CMOS ICs

A circuit measuring the phase of incoming asynchronous signals relative to the system clock in digital signal processing is described. The system clock can be in the range from 10 to 20 MHz, as is typical for video signal processing applications. As a reference in the asynchronous signal the positive or negative slope is taken. Its phase is measured with a resolution of 1/32 of a system clock cycle (approximately 1.5 to 3 ns). Pure digital CMOS technology without precision components is used, to enable combined integration on processor chips. Timing precision (jitter) is better than 200 ps without any adjustments. One external capacitor is needed     

A 45-Mbit/s CMOS VLSI digital phase aligner

An eight-channel, 45-Mb/s digital phase aligner (DPA) has been fabricated in 2-μm CMOS. The device receives asynchronous serial data at a known average clock frequency and unknown phase, and phase-aligns it with a local clock of the same frequency for subsequent synchronous processing. The all-digital architecture of this device minimizes the need for external components and avoids reliance on analog MOS circuitry. Tracking over a phase excursion range of ±4-bit periods has been demonstrated     

Smart optical receiver with automatic decision threshold settingand retiming phase alignment

The requirements for a smart optical receiver are discussed, and a design architecture suitable for introducing ICs based on automatic decision threshold setting and retiming phase alignment using digital/analog signal processing feedback is proposed. With the proposed architecture, the decision threshold level and the retiming clock phase of received data in the decision circuit are automatically adjusted to the optimum position. This obviates the need for decision threshold level and retiming clock phase adjustments in production testing, and it reduces the power penalty (receiver sensitivity degradation) on the received optical waveform variation. The power penalty caused by temperature and supply-voltage variations and aging in installation is also reduced. The performance of the proposed architecture is estimated; the power penalty as compared with the manual optimum adjustment is less than 0.4 dB, and the robustness to avalanche photodiode multiplication factor variations and crosstalk are improved     

Clock-feedthrough compensated sample/hold circuits

A novel circuit technique is presented to eliminate the clock feedthrough effect in a sample/hold circuit. The device requirement is minimal, and thus it is quite useful for CMOS monolithic implementation of precise sampled analogue signal processing circuits. Experimental waveforms are also given to demonstrate its validity     

Ultrahigh-speed clock recovery with phase lock loop based onfour-wave mixing in a traveling-wave laser diode amplifier

A new phase lock loop (PLL) is proposed and demonstrated for clock recovery from an ultrahigh-speed time-division multiplexed (TDM) optical signal. A traveling-wave laser-diode amplifier (TW-LDA) is used as a phase detector, and the cross-correlation component between the optical signal and an optical clock pulse train is detected as a four-wave-mixing (FWM) signal generated in the TW-LDA. A timing clock from a TDM signal is extracted as a prescaled electrical clock, and this prescaled clock is directly recovered from a randomly modulated TDM optical signal. A prescaled 6.3 GHz clock is successfully extracted from a 100 Gb/s signal using the timing comparison output obtained as the cross-correlation between the optical signal and a short (<10 ps) 6.3 GHz optical clock pulse train in the generated FWM light. A comparison of the PLL phase noise with a previously reported gain modulation method is also shown, and the possibility of the Tbit/s operation of this PLL is also considered in the experiments     

Dynamically De-Skewable Clock Distribution Methodology

In a typical clock distribution scheme, a central clock signal is distributed to several sites on the integrated circuit (IC). Local regenerators at these sites buffer the clock signal for the logic in regions close to the regenerator. Minimizing the skew between the clocks at these regeneration sites is critical. In recent times, this is becoming harder due to increasing intra-die processing variations. In this paper, we describe a novel technique to distribute a clock signal from a central location to several sites on a VLSI IC. Our technique uses a buffered H-tree and includes circuitry to dynamically remove any skew that may result due to intra-die processing variations. While existing approaches to deskewing a clock tree have utilized several phase detection circuits (number of phase detectors dependent on the number of clock regenerators), our method requires only one phase detector. Also, in our approach, the resolution of the phase detector is inconsequential unlike existing techniques. Our deskewing technique can be applied dynamically, either at boot time or periodically during the operation of the IC. Using a six-level H-tree clock distribution network with process variations deliberately included, we demonstrate that our technique can reduce skews as high as 300 ps down to just 3 ps. We compare our clock tree with traditional buffered and unbuffered H-tree networks.      

A 10-Gb/s CMOS clock and data recovery circuit with a half-ratelinear phase detector

A 10-Gb/s phase-locked clock and data recovery circuit incorporates an interpolating voltage-controlled oscillator and a half-rate phase detector. The phase detector provides a linear characteristic while retiming and demultiplexing the data with no systematic phase offset. Fabricated in a 0.18-μm CMOS technology in an area of 1.1×0.9 mm², the circuit exhibits an RMS jitter of 1 ps, a peak-to-peak jitter of 14.5 ps in the recovered clock, and a bit-error rate of 1.28×10^-6, with random data input of length 2²³-1. The power dissipation is 72 mW from a 2.5-V supply     

New effective method of eliminating cyclic phase slips during double-frequency kinematic GNSS observations

Design and research results of a new effective method of processing double-frequency kinematic GPS observations with the purpose of detection, estimation and elimination of cyclic phase slips are presented. This method is based on using time increments of observation and a special procedure of joint least-square estimation for a set of informative (coordinate increments and clock divergence) and non-informative parameters (carrier cyclic phase slips). The estimation of carrier cyclic phase slips is carried out by direct enumeration in the preliminarily determined search region. Verification of the suggested method is performed using simulation and real GPS observations. It is shown that reliable detection and elimination of cyclic phase slips during complete or partial loss of data on 20 second intervals is achieved in the considered case.     

Simultaneous clock phase and frequency offset estimation

Residual frequency offsets may often result in poor functioning of a digital receiver. This is particularly true in a frequency selective environment where an adaptive equalizer may be required. In this paper, a frequency offset estimation algorithm is presented which is based on applying a nonlinear operation on the received sampled baseband signal. Tones at multiples of the clock frequency are produced and the phases of these tones provide both the desired frequency offset and clock phase information. This algorithm is intended to operate without knowledge of the pulse shape and therefore may be suitable for frequency selective environments. Additionally, the clock phase may be estimated with very little overhead. Simulations with AWGN, flat and frequency selective fading channels are included     

A 10-gb/s CMOS clock and data recovery circuit with an analog phase interpolator

This paper presents a 10-Gb/s clock and data recovery (CDR) circuit for use in multichannel applications. The module aligns the phase of a plesiochronous system clock to the incoming data by use of phase interpolation. Thus, coupling between voltage-controlled oscillators (VCOs) in adjacent channels can be avoided. The controller for the phase interpolator is realized with analog circuitry to overcome the speed and phase resolution limitations of digital implementations. Fabricated in a 0.11-/spl mu/m CMOS technology the module has a size of 0.25/spl times/1.4 mm/sup 2/. The power consumption is 220 mW from a supply voltage of 1.5 V. The CDR exceeds the SDH/SONET jitter tolerance specifications with a pseudo random bit sequence of length 2/sup 23/-1 and a bit-error rate threshold of 10/sup -12/. The re-timed and demultiplexed data has an rms jitter of 3.2 ps at a data rate of 2.7 Gb/s.     

Frequency presetting and phase error detection technique for fast-locking phase-locked loop

A frequency presetting and phase error detection technique for a fast-locking phase-locked loop (PLL) is presented. The frequency difference between the reference clock and the divided VCO output clock is detected by the frequency presetting circuit. The frequency-presetting scheme allows the control voltage to be brought close to the target voltage with small initial frequency error. The phase error detector further reduced the locking speed by increasing the bandwidth of PLL through altering the supply current in the charge pump according to the phase error between the reference clock and the divided VCO output clock. The settling time of PLL can be significantly reduced afterwards. The settling time is reduced by 86%. The proposed PLL has been implemented in a 0.35 μm CMOS process, with a supply voltage of 3.3 V.     

Radar wideband digital beamforming based on time delay and phase compensation

In conventional phased array radars, analogue time delay devices and phase shifters have been used for wideband beamforming. These methods suffer from insertion losses, gain mismatches and delay variations, and they occupy a large chip area. To solve these problems, a compact architecture of digital array antennas based on subarrays was considered. In this study, the receiving beam patterns of wideband linear frequency modulation (LFM) signals were constructed by applying analogue stretch processing via mixing with delayed reference signals at the subarray level. Subsequently, narrowband digital time delaying and phase compensation of the tone signals were implemented with reduced arithmetic complexity. Due to the differences in amplitudes, phases and time delays between channels, severe performance degradation of the beam patterns occurred without corrections. To achieve good beamforming performance, array calibration was performed in each channel to adjust the amplitude, frequency and phase of the tone signal. Using a field-programmable gate array, wideband LFM signals and finite impulse response filters with continuously adjustable time delays were implemented in a polyphase structure. Simulations and experiments verified the feasibility and effectiveness of the proposed digital beamformer.     

10 Gbit/s low-power bit synchroniser with automatic retiming phase alignment

A 10 Gbit/s bit-synchroniser circuit has been fabricated using an enhancement/depletion 0.3 mu m recessed-gate AlGaAs/GaAs/AlGaAs quantum well FET process. The differential gain of the exclusive-or phase comparator circuit is measured to be 371 mV/rad. The phase margins for monotonous phase comparison are -54/+21 degrees relative to the 'in bit cell centre' position of the negative going clock edge. The chip has a power dissipation of 160 mW when using a supply voltage of 1.90 V.<>     

10 GB/s bit-synchronizer circuit with automatic timing alignment byclock phase shifting using quantum-well AlGaAs/GaAs/AlGaAs

A bit-synchronizer circuit is presented which operated up to a bit rate of Gb/s. The circuit comprises two master-slave flip -flops for data sampling, two EXCLUSIVE-OR gates for clock phase adjustment, an active signal splitter, and an EXCLUSIVE-OR gate for data transition detection. The gain of the EXCLUSIVE-OR phase comparator circuit is measured to be 302 mV/rad for a 1010-bit sequence. The margins for monotonous phase comparison are ±54° relative to the `in bit cell center' position of the sampling clock edge. The circuit is fabricated by using an enhancement/depletion 0.3 μm recessed-gate AlGaAs/GaAs/AlGaAs quantum-well FET process. The chip has a power dissipation of 230 mW at a supply voltage of 1.90 V     

一种CCD彩色摄像系统的视频锁相同步系统

介绍一种应用于ＣＣＤ彩色摄像系统的视频锁相同步系统。基于锁相理论的视频锁相同步系统是一个二级锁相环路,包括同步信号发生电路和高频点像素时钟电路。并详细阐述了同步信号发生电路和高频点像素时钟电路的锁相原理及电路。高频点像 时钟电路的外分频电路是由现场可编门阵列实例可编程特必珂得到不同频率的高频点像素时钟。     

基于FPGA的S/PDIF接收机数据解码系统的实现

为了准确接收并提取专业音频设备所发出的S/PDIF数据信号,方便后续数字音频处理模块的信号处理工作,减少因使用专业集成电路带来的额外成本,设计了基于FPGA的通用S/PDIF接收解码电路。该电路首先利用数字鉴相方式从S/PDIF信号中恢复出采样时钟,然后根据恢复出的采样时钟对信号进行采样,获得串行数据。随后电路对其进行帧同步处理以区分不同的数据段,最终按照S/PDIF的编解码规则对其进行解码后,以并行方式输出给后续音频处理模块进行进一步处理。     

PLL design technique by a loop-trajectory analysis taking decision-circuit phase margin into account for over-10-Gb/s clock and data recovery circuits

A design technique for an over-10-Gb/s clock and data recovery (CDR) IC provides good jitter tolerance and low jitter. To design the CDR using a PLL that includes a decision circuit with a certain phase margin affecting the pull-in performance, we derived a simple expression for the pull-in range of the PLL, which we call the "limited pull-in range," and used it for the pull-in performance evaluation. The method allows us to quickly and easily compare the pull-in performance of a conventional PLL with a full-rate clock and a PLL with a half-rate clock, and we verified that the half-rate PLL is advantageous because of its wider frequency range. For verification of the method, we fabricated a half-rate CDR with a 1:16 DEMUX IC using commercially available Si bipolar technology with f/sub T/=43 GHz. The half-rate clock technique with a linear phase detector, which is adopted to avoid using the binary phase detector often used for half-rate CDR ICs, achieves good jitter characteristics. The CDR IC operates reliably up to over 15 Gb/s and achieves jitter tolerance with wide margins that surpasses the ITU-T specifications. Furthermore, the measured jitter generation is less than 0.4 ps rms, which is much lower than the ITU-T specification. In addition, the CDR IC can extract a precise clock signal under harsh conditions, such as when the bit error rate of input data is around 2/spl times/10/sup -2/ due to a low-power optical input of -24 dBm.     

Jitter and phase noise in ring oscillators

A companion analysis of clock jitter and phase noise of single-ended and differential ring oscillators is presented. The impulse sensitivity functions are used to derive expressions for the jitter and phase noise of ring oscillators. The effect of the number of stages, power dissipation, frequency of oscillation, and short-channel effects on the jitter and phase noise of ring oscillators is analyzed. Jitter and phase noise due to substrate and supply noise is discussed, and the effect of symmetry on the upconversion of 1/f noise is demonstrated. Several new design insights are given for low jitter/phase-noise design. Good agreement between theory and measurements is observed     

An accurate digital phase measurement scheme

An accurate digital phase measurement scheme based on automatic accumulation principle is proposed. It uses a signal-dependent clock frequency and thus it measures the phase accurately at any frequency. Moreover, it is economical, since it eliminates the need for a highly stable crystal oscillator.     

对噪声不敏感的视频同步分离

介绍数字视频处理中时钟发生器同步锁相的必要性。分析同步不稳对图像处理的影响。在大背景噪声下，提取同步信号的方案。实验表明，在极低估噪比下，可以使数字系统稳定同步。