Substrate noise generation in complex digital systems: efficient modeling and simulation methodology and experimental verification

More and more system-on-chip designs require the integration of analog circuits on large digital chips and will therefore suffer from substrate noise coupling. To investigate the impact of substrate noise on analog circuits, information is needed about digital substrate noise generation. In this paper, a recently proposed simulation methodology to estimate the time-domain waveform of the substrate noise is applied to an 86-Kgate CMOS ASIC on a low-ohmic epi-type substrate. These simulation results have been compared with substrate noise measurements on this ASIC and the difference between the simulated and measured substrate noise rms voltage is less than 10%. The simulated time domain waveform and frequency spectrum of the substrate noise correspond well with the measurements, indicating the validity of this simulation methodology. Both measurements and simulations have been used to analyze the substrate noise generation in more detail. It has been found that direct noise coupling from the on-chip power supply to the substrate dominates the substrate noise generation and that more than 80% of the substrate noise is generated by simultaneous switching of the core cells. By varying the parameters of the simulation model, it has been concluded that a flip-chip packaging technique can reduce the substrate noise rms voltage by two orders of magnitude when compared to traditional wirebonding.     

一种混合信号集成电路衬底耦合噪声分析方法

讨论分析了混合信号集成电路衬底噪声耦合的机理,及对模拟电路性能的影响。提出了一种混合信号集成电路衬底耦合噪声分析方法,基于TSMC 0.35μm 2P4M CMOS工艺,以14位高速电流舵D/A转换器为例,给出了混合信号集成电路衬底耦合噪声分析方法的仿真结果,并与实际测试结果进行比较,证实了分析方法的可信性。     

Modeling of Substrate Noise Generation, Isolation, and Impact for an LC-VCO and a Digital Modem on a Lightly-Doped Substrate

Substrate noise generated by the digital circuits on a mixed-signal IC can severely disturb the analog and RF circuits sharing the same substrate. Simulations at the circuit level of the substrate noise coupling in large systems-on-chip (SoCs) do not provide the necessary understanding in the problem. Analysis at a higher level of abstraction gives much more insight in the coupling mechanisms. This paper presents a physical model to estimate and understand the substrate noise generation by a digital modem, the propagation of this noise and the resulting performance degradation of LC tank VCOs. The proposed linearized model is fast to derive and to evaluate, while remaining accurate. It is validated with measurements on two test structures: a reference design and a design with a$hboxp^+ $/n-well (digital) guard ring. Both structures contain a functional 40k gate digital modem and a 0.18$muhbox m$3.5 GHz CMOS LC-VCO on a lightly-doped substrate. In both cases, the model accurately predicts the level of the spurious components appearing at the VCO output due to the digital switching activity. The error remains smaller than 3 dB. Finally, we demonstrate how the proposed model enables a systematic and controlled isolation strategy to suppress substrate noise coupling problems. As an example, the model is used to determine suitable dimensions for a digital guard ring.     

Substrate coupling in digital circuits in mixed-signal smart-power systems

This paper describes theoretical and experimental data characterizing the sensitivity of nMOS and CMOS digital circuits to substrate coupling in mixed-signal, smart-power systems. The work presented here focuses on the noise effects created by high-power analog circuits and affecting sensitive digital circuits on the same integrated circuit. The sources and mechanism of the noise behavior of such digital circuits are identified and analyzed. The results are obtained primarily from a set of dedicated test circuits specifically designed, fabricated, and evaluated for this work. The conclusions drawn from the theoretical and experimental analyses are used to develop physical and circuit design techniques to mitigate the substrate noise problems. These results provide insight into the noise immunity of digital circuits with respect to substrate coupling.     

SOI数模混合集成电路的串扰特性分析

采用二维TMA Medici模拟软件对SOI结构的串扰特性进行了分析.模拟发现随着频率的增加,SOI的埋氧化物对串扰噪声几乎不起隔离作用,同时,连接SOI结构的背衬底可以在很大程度上减小串扰的影响.还对减少串扰的沟槽隔离工艺、保护环及差分结构的有效性进行了比较分析,对一些外部寄生参数对串扰的影响也进行了研究.并给出了SOI结构厚膜和薄膜结构体掺杂浓度对噪声耦合的影响,所得到的结果对设计低噪声耦合的SOI数模混合集成电路具有指导性的作用.     

Simulation and measurement of supply and substrate noise in mixed-signal ICs

Digital noise in mixed-signal circuits is characterized using a scalable macromodel for substrate noise coupling. The noise coupling obtained through simulations is verified with measured data from a digital noise generator and noise sensitive analog circuits fabricated in the 0.35-/spl mu/m heavily doped CMOS process. The simulations and measurements also demonstrate the effectiveness of including grounded guard rings and separating bulk and supply pins in digital circuits to reduce substrate coupling.     

Measurements and analysis of PLL jitter caused by digital switchingnoise

When integrating analog and digital circuits onto a mixed-mode chip, power supply noise coupling is a major limitation on the performance of the analog circuitry. Several techniques exist for reducing the noise coupling, of which one of the cheapest is separating the power supply distribution networks for the analog and digital circuits. Noise coupling from a digital noise-generating circuit through the power supply/substrate into an analog phase-locked loop (PLL) is analyzed for three different power supply schemes. The main mechanisms for noise coupling are identified by comparing different PLLs and varying their bandwidths. It is found that the main cause of jitter strongly depends on the power supply configuration of the PLL. Measurements were done on mixed-mode designs in a standard 0.25-μm digital CMOS process with a low-resistivity substrate. The same circuits were also implemented with triple-well processing for comparisons     

SWAN: high-level simulation methodology for digital substrate noise generation

Substrate noise generated by the switching digital circuits degrades the performance of analog circuits embedded on the same substrate. It is therefore important to know the amount of noise at a certain point on the substrate. Existing transistor-level simulation approaches based on a substrate model extracted from layout information are not feasible for digital circuits of practical size. This paper presents a complete high-level methodology, which simulates a large digital standard cell-based design using a network of substrate macromodels, with one macromodel for each standard cell. Such macromodels can be constructed for both EPI-type and bulk-type substrates. Comparison of our substrate waveform analysis (SWAN) to several measurements and to several full SPICE simulations indicates that the substrate noise is simulated with our methodology within 10%-20% error in the time domain and within 2 dB relative error at the major resonance in the frequency domain. However, it is several orders of magnitude faster in CPU time than a full SPICE simulation.     

Substrate Noise Simulation Techniques for Analog-Digital Mixed LSI Design

Crosstalk from digital to analog circuits can be causative of operation fails in analog-digital mixed LSIs. This paper describes modeling techniques and simulation strategies of the substrate coupling noise. A macroscopic substrate noise model that expresses the noise as a function of logic state transition frequencies among digital blocks is proposed. A simulation system based on the model is implemented in the mixed signal simulation environment, where performance degradation of the 2nd order ADC coupled to digital noise sources is clearly simulated. These results indicate that the proposed behavioral modeling approach allows practicable full chip substrate noise simulation measures.     

Measuring and modeling the effects of substrate noise on the LNAfor a CMOS GPS receiver

The influence of substrate noise coupling on the performance of a low-noise amplifier (LNA) for a CMOS GPS receiver has been investigated both analytically and experimentally. A frequency-domain approach has been used to model both noise injection into the substrate from digital circuitry integrated on the same chip and the mechanisms by which that noise can affect analog circuit behavior. The results of this study reveal that substrate noise can modulate the LNA input signal as well as couple directly to the amplifier's output     

Analytical and experimental verification of substrate noise spectrum for mixed-signal ICs

In this paper, the most relevant characteristics of the substrate noise spectrum for mixed-signal integrated circuits (ICs) are derived using a simple analytical model. These characteristics are related to parameters of the digital circuit, the package + printed circuit board parasitics, and other elements of the mixed-signal IC. The model used to derive the substrate noise spectral characteristics includes the statistical properties of the digital switching current waveform and the coupling transfer function between the digital power supply nodes and the substrate node of the victim circuitry. The results of the work are validated experimentally on a mixed-signal prototype.     

Experimental results and modeling techniques for substrate noise inmixed-signal integrated circuits

An experimental technique is described for observing the effects of switching transients in digital MOS circuits that perturb analog circuits integrated on the same die by means of coupling through the substrate. Various approaches to reducing substrate crosstalk (the use of physical separation of analog and digital circuits, guard rings, and a low-inductance substrate bias) are evaluated experimentally for a CMOS technology with a substrate comprising an epitaxial layer grown on a heavily doped bulk wafer. Observations indicate that reducing the inductance in the substrate bias is the most effective. Device simulations are used to show how crosstalk propagates via the heavily doped bulk and to predict the nature of substrate crosstalk in CMOS technologies integrated in uniform, lightly doped bulk substrates, showing that in such cases the substrate noise is highly dependent on layout geometry. A method of including substrate effects in SPICE simulations for circuits fabricated on epitaxial, heavily doped substrates is developed     

Analysis and suppression of SSN noise coupling between power/ground plane cavities through cutouts in multilayer packages and PCBs

The authors introduced a model of simultaneous switching noise (SSN) coupling between the power/ground plane cavities through cutouts in high-speed and high-density multilayer pack-ages and printed circuit boards (PCBs). Usually, the cutouts are used in multilayer plane structures to isolate the SSN of noisy digital circuits from sensitive analog circuits or to provide multiple voltage levels. The noise-coupling model is expressed in terms of the transfer impedance. The proposed modeling and analysis results are compared with measured data up to 10 GHz to demonstrate the validity of the model. It is demonstrated that the cutout is the major gate for SSN coupling between the plane cavities, and that substantial SSN coupling occurs between the plane cavities through the cutout at the resonant frequencies of the plane cavities. The coupling mechanism and characteristics of the noise coupling, from which a method of suppression of the SSN coupling evaluated was also analyzed and discussed. Proper positioning of the cutout and the devices at each plane cavity achieves significant noise suppression at certain resonant frequencies. The suggested suppression method of the SSN coupling was successfully proved by frequency domain measurement and time domain analysis.     

A simple on-chip repetitive sampling setup for the quantification of substrate noise

The quantification of substrate noise is an important issue in mixed-signal designs, where sensitive analog circuits are embedded in a hostile digital environment. In this paper we present an experimental environment to characterize the sensitivity of embedded analog circuits to digitally generated substrate noise. Our measurement technique is based on equivalent-time substrate voltage sampling and uses a simple differential latch comparator without explicit input sample-and-hold. A surprisingly large measurement bandwidth is observed,which is explained from the detailed circuit behavior. On our 0.18-/spl mu/m CMOS test chip,we have demonstrated that our system allows to wave trace pulses as narrow as 200 ps accurately. Additionally, the extraction of precise measurement data from observations that are excessively corrupted by additive noise and timing jitter is addressed. We present simple yet very effective methods to accurately reconstruct pulse waveform features without the use of delicate deconvolution operations.     

A virtual clock enhancement method for DDS using an analog delayline

In this paper, we describe an analog delay line (DL) used for virtual clock enhancement in a direct digital synthesis (DDS). The novelty of the proposed method is the immediate application of the output signal of the phase accumulator for the generation of the desired frequency. To obtain the necessary spectral purity of the generated frequency, additional digital signal processing (DSP) based on a delay-locked loop (DLL) and noise shaping is applied. The consequences of nonlinear effects within the DL for the spectral performance of the DDS are explained     

Addressing substrate coupling in mixed-mode ICs: simulation andpower distribution synthesis

This paper describes new techniques for the simulation and power distribution synthesis of mixed analog/digital integrated circuits considering the parasitic coupling of noise through the common substrate. By spatially discretizing a simplified form of Maxwell's equations, a three-dimensional linear mesh model of the substrate is developed. For simulation, a macromodel of the fine substrate mesh is formulated and a modified version of SPICE3 is used to simulate the electrical circuit coupled with the macromodel. For synthesis, a coarse substrate mesh, and interconnect models are used to couple linear macromodels of circuit functional blocks. Asymptotic Waveform Evaluation (AWE) is used to evaluate the electrical behavior of the network at every iteration in the synthesis process. Macromodel simulations are significantly faster than device level simulations and compare accurately to measured results. Synthesis results demonstrate the critical need to constrain substrate noise and simultaneously optimize power bus geometry and pad assignment to meet performance targets     

Noise generation,propagation and effects on RF components in system-on-a-chip packaging

Substrate coupling noise effects in wireless receiver systems in terms of the crosstalk power spectral density induced from the fast switching digital circuits is the center of study in this paper. Deterioration in performance of a low noise amplifier is plotted against various values of die-attach inductance, inductance on digital ground pins, physical separation between the analog and digital circuits on-chip, number of simultaneous switching output buffers, etc. Different Ball Grid Array Packages, both the wire bonded and flip-chip attached versions have been studied. The return loss and insertion loss for paths from the on-chip wire bond pad to connect pads on the printed circuit boards have been plotted. Results show that noise reduces by a greater amount for reduction in die-attach inductance as compared to a reduction in inductance on the digital ground pin.     

Substrate model extraction using finite differences and parallel multigrid

Substrate noise in integrated circuits is one of the most important problems in high-frequency mixed-signal designs, such as communication, biomedical and analog signal processing circuits and systems. Fast-switching digital blocks inject noise into the common substrate, hindering the performance of high-precision sensible analog circuitry. Miniaturization trends require increasing the accuracy in substrate coupling simulation environments. However, model extraction and evaluation times should not increase, which demands for fast and still accurate substrate model extraction tools.

In this work, a three-dimensional finite difference extraction methodology is presented. The resulting three-dimensional mesh is efficiently reduced to a circuit-level contact-based model by means of a fast multigrid-based algorithm. Moreover, this contact-based model extraction is shown to be efficiently computed in a parallel environment, resulting in extremely useful extraction speedups. Extraction results prove the proposed method to be very efficient, providing linear time and space complexity, and a constant number of iterations, outperforming competing algorithms.     

Accurate and efficient simulation of synchronous digital switching noise in systems on a chip

A new method is presented to compress switching information in large synchronous digital circuits. This is combined with an efficient generation of digital cell library noise signatures and results in an accurate estimation of the switching noise in digital circuits. It provides a practical approach to generating the digital switching noise for simulating substrate coupling noise in mixed-signal ICs. Nearly two orders of magnitude reduction in the memory and simulation time are achieved using this approach without significant loss of accuracy.     

A tight signal-band power bound on mismatch noise in a mismatch-shaping digital-to-analog converter

Many applications employ digital-to-analog converters (DACs) to obtain the advantages of digital processing (e.g., low power and physical size, resilience to noise, etc.) to generate signals, such as voltages, that are analog in nature. Given the appropriate numerical representation of its input, the DAC ideally behaves as a linear gain element. However, as a result of inevitable component mismatches, the output of a multibit DAC (i.e., a DAC designed to output more than two analog levels) is a nonlinear function of its input. The resulting distortion, called DAC noise , limits the overall signal-to-noise ratio (SNR) and hence the obtainable accuracy of the DAC. Mismatch-shaping DACs exploit built-in redundancy to suppress the DAC noise in the input signal's frequency band. Although mismatch-shaping DACs are widely used in commercial products, little theory regarding the structure of their DAC noise has been published to date. Consequently, designers have been forced to rely upon simulations to estimate DAC noise power and behavior, which can be misleading because the DAC noise depends on the DAC input. This paper addresses this problem. It presents an analysis of the DAC noise power spectral density (PSD) in a commonly used mismatch-shaping DAC: the dithered first-order low-pass tree-structured DAC. This design ensures that its DAC noise has a spectral at dc (i.e., zero frequency) by generating digital, dc-free sequences using the same techniques that have been developed for line codes. An expression is derived for the DAC noise PSD that depends on the statistics of these sequences and is used to show various properties of the DAC noise. Specifically, an attainable bound is derived for the signal-band DAC noise power that can be used to predict worst case performance in practical circuits.