Substrate current in short n-channel MOS transistors

Tho substrain current against gate voltage characteristics or relatively short n-channel MOS transistors were examined for various substrate and drain voltages, channel length and surface doping conditions : namely without implantation, implantation for threshold voltage adjustment and implantation for depletion mode device types A, B and C, respectively. The substrate current may increase or decrease when increasing the aubstrate voltage magnitude duo to the fact that the drain current decreases and the multiplication factor increases with the substrate bias. The substrate current increases when decreasing the channel length. It increases for the devices of type B, but is lower for type C. These experimental results were qualitatively explained by using published models in which the substrate current is caused by low-level impact ionization within the pinched-off region. A simple model in which the ionization coefficient and the field derivative with respect to x wore assumed to be power-law field-dependent correctly predicts the behaviour of the substrate current.     

Impact ionization current in MOS devices

An impact ionization current flows in the substrate of an MOS device which is operated in the saturation region. This current results from hole-electron pairs created by impact ionization in the drain depletion region. This paper utilizes the transverse electric field across the depletion region and the probability of creating a hole-electron pair as a function of this field to calculate substrate current which is then compared with measured data.     

Two-dimensional energy-dependent models for the simulation ofsubstrate current in submicron MOSFET's

Two-dimensional energy-dependent substrate current models are described for NMOS and PMOS devices that have been developed using a multi-contour approach. The new models offer a significant improvement in the calculation of substrate current due to a more accurate calculation of the average energy as compared to the local-field model. The models are implemented in a post-processing manner by applying a one-dimensional energy conservation equation to each of many current contours in order to generate a two-dimensional representation of average energy and impact ionization rate, that is then integrated to calculate the substrate current. The new models have been compared to substrate current characteristics of a variety of NMOS and PMOS devices for a wide range of bias conditions and channel lengths, and very good agreement has been obtained with a single set of model parameters. An additional significance of this work is the enhancement of the standard multi-contour model by an energy-sink term that results in an improved prediction of the impact ionization process in PMOSFET's     

New experimental findings on hot carrier effects in sub-0.1 μmMOSFET's

The behaviors of the substrate current and the impact ionization rate are investigated for deep submicron devices in a wide temperature range. New important features are shown for the variations of the maximum substrate current as a function of applied biases and temperature. It is found that the gate voltage V_gmax, corresponding to the maximum impact ionization current conditions, is quasi-constant as a Function of the drain bias for sub-0.1 μm MOSFET's in the room temperature range. At low temperature, a substantial increase of V_gmax is observed when the drain voltage is reduced. It is also shown that, although a significant enhancement of hot carrier effects is observed by scaling down the devices, a strong reduction of the impact ionization rate is obtained for sub-0.1 μm MOSFET's operated at liquid nitrogen temperature in the low drain voltage range     

Inclusion of impact ionization in the backgating of GaAs FETs

It is shown that the familiar threshold behavior of the backgate current of GaAs MESFETs has hysteresis. This is associated with an S-type negative differential conductivity (S-NDC) of the semi-insulating substrate. It is difficult to account for this hysteresis using conventional trap-fill-limited (TFL) theory, and it is attributed to the impact ionization of traps in the substrate. A simple model of this ionization, involving two trap levels, is used to incorporate its effect into an existing analytical model of GaAs FETs. The result is a qualitative interpretation of the backgating characteristics of GaAs MESFETs. The calculations show that a simple combination of two ohmic elements to represent parasitic resistances, and a nonohmic one to represent impact ionization in the substrate, can imitate the observed backgating behavior     

A numerical model of avalanche breakdown in MOSFET's

An accurate numerical model of avalanche breakdown in MOSFET's is presented. Features of this model are a) use of an accurate electric-field distribution calculated by a two-dimensional numerical analysis, b) introduction of multiplication factors for a high-field path and the channel current path, and c) incorporation of the feedback effect of the excess substrate current induced by impact ionization into the two-dimensional calculation. This model is applied to normal breakdown observed in p-MOSFET's and to negative-resistance breakdown (snap-back or switchback breakdown) observed in short-channel n-MOSFET's. Excess substrate current generated from channel current by impact ionization causes a significant voltage drop across the substrate resistance in short-channel n-MOSFET's. This voltage forward-biases the source-substrate junction and increases channel current causing a positive feedback effect. This results in a decrease of the breakdown voltage and leads to negative-resistance characteristics. Current-voltage characteristics calculated by the present model agree very well with experimental results. Another model, highly simplified and convenient for device design, is also presented. It predicts some advantages of p-MOSFET's over n-MOSFET's from the standpoint of avalanche breakdown voltage, particularly in the submicrometer channel-length range.     

The effect of impact ionization induced bipolar action on n-channelhot-electron degradation

The relationship between the total impact ionization rate and the measured substrate current is analyzed, using short-channel NMOS devices. It is shown that holes that are injected into the source and turn on the parasitic source-bulk-drain bipolar may actually be a significant portion of the total impact ionization current. The authors explain how the commonly used model, which ignores this bipolar effect, can lead to incorrect predictions regarding hot-electron degradation. A related criterion for maximum source-drain voltage during accelerated stress is discussed and justified     

New experimental findings on hot carrier effects in deep submicrometer surface channel PMOS

The correlation between gate current and substrate current in surface channel(SC) PMOS with effective channel length down to 0.15 μm is investigated within the general framework of the lucky-electron model. It is found that the impact ionization rate increases, but the device degradation is not serious in deep submicrometer PMOS. To extend the lucky-electron model to deep submicrometer regime, we empirically model the effective pinch-off length as a function of the gate length and the gate bias voltage. SCIHE is suggested as the possible physical mechanism for the enhanced impact ionization and the gate current reduction.     

A model for the relation between substrate and gate currents in n-channel MOSFET's

The gate current in n-channel MOSFET's normalized to the source current is expressed as a function of the substrate current normalized to the source current by means of an impact ionization model. The ratio of the electron mean free path for impact ionization to that for optical phonon scattering, which is the most important among the various related device parameters, is determined by indirect measurement of the gate current using stacked-gate MOSFET's. The present model has been applied to interpret the experimental results obtained from samples with a variety of device dimensions. Limitation by the hot-electron emission, which is an important design constraint for submicrometer-gate MOS devices, is studied for single-gate and stacked-gate MOSFET's in comparison with other limiting factors.     

Temperature dependence of hot-electron-induced degradation in MOSFET's

The temperature dependence of MOSFET degradation due to hot-electron injection has been studied. The slower degradation rate at elevated temperature at fixed stressing bias follows the substrate current level which is reduced mainly by lower localized electric field rather than lower ionization coefficient (both are caused by enhanced phonon scattering). The actual degradation rate at the constant substrate current level is slightly higher at elevated temperatures, indicating an enhanced interface-state generation mechanism. This temperature dependence provides a simple relationship between device degradation and substrate current at various temperatures.     

Substrate current model for submicrometer MOSFETs based on meanfree path analysis

The nonequilibrium effects of hot carriers are investigated to analyze avalanche generation for submicrometer MOSFET devices. A simple analytical expression for the impact ionization utilizing the mean free path concept is developed. It is incorporated into a conventional drift-diffusion equation solver (PISCES) to obtain the substrate current in submicrometer MOSFET devices. The transconductance for high drain bias and breakdown conditions are analyzed based on the proposed impact ionization model     

A comparative analysis of substrate current generation mechanisms in tunneling MOS capacitors

This paper presents a critical analysis of the origin of majority and minority carrier substrate currents in tunneling MOS capacitors. For this purpose, a novel, physically-based model, which is comprehensive in terms of impact ionization and hot carrier photon emission and re-absorption in the substrate, is presented. The model provides a better quantitative understanding of the relative importance of different physical mechanisms on the origin of substrate currents in tunneling MOS capacitors featuring different oxide thickness. The results indicate that for thick oxides, the majority carrier substrate current is dominated by anode, hole injection, while the minority carrier current is consistent with a photon emission-absorption mechanism, at least in the range of oxide voltage and oxide thickness covered by the considered experiments. These two currents appear to be strictly correlated because of the relatively flat ratio between impact ionization and photon emission scattering rates and because of the weak dependence of hole transmission probability on oxide thickness and gate bias. Simulations also suggest that, for thinner oxides and smaller oxide voltage drop, the photon emission mechanism might become dominant in the generation of substrate holes.     

Influence of impact ionization on the drain conductance inInAs-AlSb quantum well heterostructure field-effect transistors

Using an InAs-AlSb heterostructure field-effect transistor (HFT) structure modified to incorporate an epitaxial p-type GaSb back gate, we measure the impact ionization current caused by hot electrons in the InAs channel. We show that the impact ionization current is only a small fraction of the deleterious increase in the drain current commonly observed in InAs-based transistors. Most of the drain current rise is caused by a feedback mechanism in which holes escaping into the substrate act like a positively charged parasitic back gate leading to an increase in the electron current flow in the channel by an amount that is large compared to the impact ionization current itself. Removal of the impact-generated holes by the epitaxial back gate breaks the feedback loop, and dramatically improves the DC characteristics of the devices, and increases the range of usable drain voltages     

Substrate current characterization and optimization of high voltage LDMOS transistors

A 30-V LDMOS integrated with a standard 0.15 μm CMOS process is investigated for its double-hump substrate current (I_b) characteristics. The origin of this abnormal second substrate current hump is explained by Kirk effect. The impact of this second hump of I_b on reliability and device performance is observed. An analytical expression for the second hump of I_b is established by calculating the impact ionization in the drift region according to the electric field distribution obtained by solving Poisson’s equation. The calculated results are compared against the silicon data under various gate/drain bias voltages showing excellent consistency. Additionally, based on the derived expressions for substrate current, the process parameters are optimized achieving much lower substrate current and better reliability performance.     

Modeling of substrate current in p-MOSFET's

It is shown that the substrate current characterization method and modeling approach used for n-MOSFET's is also applicable to p-MOSFET's. The impact ionization rate extracted for holes is found to be 8 × 10⁶exp (-3.7 × 10⁶/E), where E is the electric field. Based on our measurement and modeling result, roughly twice the channel electric field is required for p-MOSFET's to generate the same amount of substrate current as n-MOSFET's. The hot-carrier-induced breakdown voltage is therefore also about two times larger.     

Trench capacitor leakage in high-density DRAM's

The leakage current between trench capacitors for megabit dynamic MOS memories has been modeled and studied through simulations. The minimum substrate doping density, to limit the leakage current to 1 pA/µm, has been determined as a function of trench-trench spacing. The effect of all other relevant parameters on the required substrate doping density has also been investigated. Furthermore, the substrate doping density at which impact ionization causes avalanche breakdown at the trench capacitor junction has been estimated. It is found that, for trench spacing of 0.75 µm or more, one can always find an intermediate range of substrate doping concentrations for which both the trench-trench leakage and the junction breakdown can be avoided.     

A better understanding of substrate enhanced gate current in VLSIMOSFETs and flash cells. II. Physical analysis

For pt. I see ibid., vol. 46, no. 2 (Feb. 1999). In this work-different physical mechanisms that could lead to the direct proportionality between I_G and I_B as the signature of substrate enhanced electron injection (SEEI), are analyzed in detail. By means of experiments and simulations we substantiate the current interpretation of SEEI in terms of an impact ionization feedback process and attribute a quantitatively negligible role to both drain avalanche hot electron injection and substrate electrons generated by the photons emitted by channel hot electrons. These experiments reconcile the current explanation of SEEI with the well known phenomenon of photon assisted minority carrier injection in the substrate, whose presence is clearly detectable in our devices, but whose impact on the gate current is estimated to be orders of magnitude smaller than that of impact ionization feedback     

The reduction of backgating in GaAs MESFETs by impact ionization

The reduction of drain current due to reverse substrate bias in GaAs MESFETs fabricated on EL2-compensated substrates is recovered with the application of sufficient drain bias. The recovery is shown to be due to the compensation of the negative space charge at the channel-substrate interface by holes generated by impact ionization in the MESFET channel. Illumination raises the value of drain bias needed for current recovery due to the requirement of additional hole flux to offset the effects of optically generated electrons on EL2 occupancy. Simulation results show that the channel current becomes independent of substrate bias when the bias value is sufficient to completely delete the p-type surface layer     

Failure in CMOS circuits induced by hot carriers in multi-gatetransistors

The problem of vertical isolation in circuits fabricated using shallow n-well epitaxial CMOS technology is analyzed. Unexpectedly high substrate current resulting in circuit failure has been observed during accelerated reliability tests. The substrate current is a result of enhanced hole injection from multi-gate p-channel transistors with interdigitated source and drain. The electron current generated from impact ionization near the drain forward biases the source junctions, causing hole injection to the substrate. The current is sensitive to the supply voltage and temperature. Consequently, unanticipated failures may occur at the high voltages and temperatures encountered during burn-in. Design and process solutions are discussed     

Hot hole gate current in surface channel PMOSFETs

This paper reports the observation of a new hot hole component of the gate current of p⁺-poly gate pMOS transistors. The phenomenon is characterized as a function of drain, gate, and substrate bias on devices featuring different oxide thickness and drain engineering options. The new hole gate current component is ascribed to injection into the oxide of substrate tertiary holes, generated by an impact ionization feedback mechanism similar to that responsible of CHannel Initiated Secondary ELectron injection (CHISEL) in nMOSFETs