具有P型浮空层的新型载流子存储槽栅双极晶体管

文中提出了一种具有P型浮空层的载流子存储槽栅双极晶体管。引入P型浮空层,可以增加载流子存储层厚度和掺杂浓度,有效地提高了近发射极的电导调制作用,降低积累层电阻和扩展电阻,使得导通损耗大大减小。同时,P型浮空层改善了传统结构中的电场分布,提高器件击穿电压。仿真结果表明：新结构较传统槽栅IGBT和载流子存储槽栅双极晶体管正向导通压降分别降低约20%和17%,正向阻断电压提高了100V以上,且没有使得短路安全工作区（SCSOA）减小。     

一种带有超结浮空层的槽栅场阻IGBT

本文提出了一种带有超结浮空层的槽栅场阻IGBT,它具有高的击穿电压(>1200V),低的正向压降和快速的关断能力。高掺杂的 SJ 浮空层在阳极侧引入了电场峰的同时优化了器件内载流子分布,带来关态击穿电压提高,开态、开关态能量损耗减少等好处。在保持电荷平衡的前提下,增加 SJ 浮空层的厚度可以提高击穿电压和降低正向压降,降低 P 型阳极浓度可以减少关断损耗。与传统结构相比,新结构击穿电压提高了100V,正向压降降低了0.33V（电流密度为100A/cm2）,关断时间缩短了60%。     

具有积累层沟道的槽栅IGBT结构

提出了一种具有积累层沟道的槽栅IGBT结构。仿真结果表明：在阻断电压为1200V,集电极电流密度为100 A/cm2,温度分别为300K和400K下的情况下,积累层沟道槽栅IGBT的正向压降分别为1.5V 和2V而常规槽栅IGBT分别为1.7V和2.4V。新结构比常规槽栅IGBT具有更低的开态压降和更大的正向安全工作区。文中同时分析了积累层沟道槽栅IGBT的阻断特性和关断特性。     

4H-SiC MESFET新结构的特性研究

提出了一种具有阶梯沟道和浮空金属板的新型4H-SiC MESFET结构。在双凹型4H-SiC MESFET的栅漏之间加入浮空金属板,并引入阶梯沟道,减少了靠近漏端的栅边缘的电场积聚,提高了击穿电压。对提出的结构进行二维数值模拟,结果表明,该结构的击穿电压达到232 V,相对于双凹型4H-SiC MESFET的击穿电压103 V,提高了125%,其饱和漏电流相对提高了4.1%,截止频率为15.1 GHz,最大振荡频率为69.2 GHz。该结构在击穿电压提高125%时,没有严重降低截止频率。     

一种P-GaN栅极结合槽栅技术的增强型HEMT

为了得到高击穿电压、高阈值电压的增强型GaN器件,提出了一种P型掺杂GaN(P-GaN)栅极结合槽栅技术的AlGaN/GaN/AlGaN双异质结结构.该器件的阈值电压高达3.4 V,击穿电压达738 V.利用Sentaurus TCAD进行仿真,对比了传统P-GaN栅与P-GaN栅结合槽栅的AlGaN/GaN/AlGa...     

一种P-GaN栅结合混合帽层结构的HEMT器件

为了进一步提升P-GaN栅HEMT器件的阈值电压和击穿电压,提出了一种具有P-GaN栅结合混合掺杂帽层结构的氮化镓高电子迁移率晶体管(HEMT)。新器件利用混合掺杂帽层结构,调节整体极化效应,可以进一步耗尽混合帽层下方沟道区域的二维电子气,提升阈值电压。在反向阻断状态下,混合帽层可以调节栅极右侧电场分布,改善栅边电场集中现象,提高器件的击穿电压。利用Sentaurus TCAD进行仿真,对比普通P-GaN栅增强型器件,结果显示,新型结构器件击穿电压由593 V提升至733 V,增幅达24%,阈值电压由0.509 V提升至1.323 V。     

3300V逆导型IGBT器件仿真

基于现有仿真平台,设计一款3 300V/50A逆导型绝缘栅双极晶体管器件(逆导型IGBT或RC-IGBT),元胞采用场截止型平面栅结构,元胞设计中采用载流子增强技术(EP),元胞注入采用自对准工艺,背面P型集电极采用透明集电极技术,降低IGBT工作模式下的饱和压降。采用二维数值仿真研究了器件结构及结构参数对器件性能的影响,通过结构参数拉偏,折衷优化IGBT与内集成二极管的性能参数,仿真得到的3 300V/50A逆导型IGBT器件饱和压降为3.4V,二极管导通压降为2.3V,阈值电压为5.6V,击穿电压为4 480V,与相同电压等级的分立IGBT器件和二极管性能相当。     

一种低功耗4H-SiC IGBT的仿真研究

针对传统沟槽栅4H-SiC IGBT关断时间长且关断能量损耗高的问题,文中利用Silvaco TCAD设计并仿真了一种新型沟槽栅4H-SiC IGBT结构。通过在传统沟槽栅4H-SiC IGBT结构基础上进行改进,在N ⁺缓冲层中引入两组高掺杂浓度P区和N区,提高了N ⁺缓冲层施主浓度,折中了器件正向压降与关断能量损耗。在器件关断过程中,N ⁺缓冲层中处于反向偏置状态的PN结对N ^-漂移区中电场分布起到优化作用,加速了N ^-漂移区中电子抽取,在缩短器件关断时间和降低关断能量损耗的同时提升了击穿电压。Silvaco TCAD仿真结果显示,新型沟槽栅4H-SiC IGBT击穿电压为16 kV,在15 kV的耐压设计指标下,关断能量损耗低至4.63 mJ,相比传统结构降低了40.41%。     

带有P型埋层的新型双栅SOI MOSFET

本文提出一种超低比导通电阻(Ron,sp)可集成的SOI 双栅triple RESURF (reduced surface field)的n型MOSFET (DG T-RESURF)。这种MOSFET具有两个特点：平面栅和拓展槽栅构成的集成双栅结构(DG),以及位于n型漂移区中的P型埋层。首先, DG形成双导电通道并且缩短正向导电路径,降低了比导通电阻。DG结构在反向耐压时起到了纵向场板作用,提高了器件的击穿电压特性。其次, P型埋层形成triple RESURF结构 (T-RESURF),这不仅增加了漂移区的浓度,而且调节了器件的电场。这在降低了比导通电阻的同时提高了击穿电压。最后,与p-body区连接在一起的P埋层和拓展槽栅结构,可以显著降低击穿电压对P型埋层位置的敏感性。通过仿真,DG T-RESURF的击穿电压为325V,比导通电阻为8.6 mΩ?cm2,与平面栅single RESURF MOSFET(PG S-RESURF)相比,DG T-RESURF的比导通电阻下降了63.4%,击穿电压上升9.8%。     

一种电场调制载流子存储槽栅双极型晶体管

提出了一种性能优良的电场调制载流子存储槽栅双极型晶体管(CSTBT)。结合电场调制原理,在器件的载流子存储(CS)层引入P掺杂条,改善器件栅极下方氧化硅拐角处的电场分布,防止器件提前发生雪崩击穿,提高了器件的击穿电压。器件处于关断状态时,内部大量的空穴载流子通过CS层中未完全耗尽的P掺杂条到达发射极,抑制了CS层阻挡空穴的作用,有效提高了器件的关断速度。与传统CSTBT器件相比,改进器件的击穿电压值提高了379 V,关断时间缩短了19.1%,器件性能大幅提高。     

Trench gate IGBT structure with floating P region

A new trench gate IGBT structure with a floating P region is proposed,which introduces a floating P region into the trench accumulation layer controlled IGBT(TAC-IGBT).The new structure maintains a low on-state voltage drop and large forward biased safe operating area(FBSOA)of the TAC-IGBT structure while reduces the leakage current and improves the breakdown voltage.In addition,it enlarges the short circuit safe operating area(SCSOA)of the TAC-IGBT,and is simple in fabrication and design.Simulation results indicate that,for IGBT structures with a breakdown voltage of 1200 V, the leakage current of the new trench gate IGBT structure is one order of magnitude lower than the TAC-IGBT structure and the breakdown voltage is 150 V higher than the TAC-IGBT.     

一种积累型沟道的半超结结构绝缘栅双极型晶体管

A high performance trench insulated gate bipolar transistor which combines a semi-superjunction struc- ture and an accumulation channel （sSJTAC-IGBT） is proposed for the first time. Compared with the TAC-IGBT, the new device not only retains the advantages of the accumulation channel, but also obtains a larger breakdown voltage （BV）, a faster turn-off speed and a smaller saturation current level while keeping the on-state voltage drop lower as the TAC-IGBT does as well. Therefore, the new structure enlarges the short circuit safe operating area （SCSOA） and reduces the energy loss during the turn-off process.     

Shielding region effects on a trench gate IGBT

In this paper we introduced the shielding region concept in order to relieve the electric field concentrated on the trench bottom corner. The shielded trench gate insulated gate bipolar transistor (IGBT) is a trench gate IGBT with a P+shielding region located in the bottom of a trench gate. By simulation results, we verified that a shielding region reduced the electric fields not only in the gate oxide but also in the P-base region. Compared with conventional trench gate IGBT, about 33% increment of forward breakdown voltages are achieved, but little forward voltage drop, which causes on-state loss to be increased by about 0.06 V in the shielded trench gate IGBT.     

Insulated gate bipolar transistor with trench gate structure of accumulation channel

An accumulation channel trench gate insulated gate bipolar transistor (ACT-IGBT) is proposed. The simu-lation results show that for a blocking capability of 1200 V, the on-state voltage drops of ACT-IGBT are 1.5 and 2 V at a temperature of 300 and 400 K, respectively, at a collector current density of 100 A/cm~2. In contrast, the on-state voltage drops of a conventional trench gate IGBT (CT-IGBT) are 1.7 and 2.4 V at a temperature of 300 and 400 K,respectively. Compared to the CT-IGBT, the ACT-IGBT has a lower on-state voltage drop and a larger forward bias safe operating area. Meanwhile, the forward blocking characteristics and turn-off performance of the ACT-IGBT are also analyzed.     

A New Emitter Switched Thyristor (EST) employing Trench Segmented p-base

A new emitter switched thyristor (EST) employing trench segmented p-base, which successfully improves the forward I-V and switching characteristics with decreasing the device active area, is proposed and verified experimentally with using shallow trench process of novel junction termination extension (JTE) method. The latching current of EST is determined by the p-base resistance of upper npn transistor. Floating n+emitter of conventional EST is enlarged to obtain large base resistance. However, the proposed EST increases the p-base resistance with shorter floating n+ emitter than that of conventional one. Shallow trench in floating emitter region forms the highly resistive p-base region under the bottom of trench. The experimental results show that the shortened floating n+ emitter and lowered latching current of proposed EST decrease experimentally the forward voltage drop by 17.7% and snap-back phenomenon with small active area. The breakdown voltage of series lateral MOSFET of proposed EST is increased from 7 to 14 V due to the trench filled with oxide which results in vertical redistribution of electric field, therefore current saturation capability and forward biased safe operating area (FBSOA) of proposed EST are enhanced. The simulation results show that the switching operation is performed successfully at the blocking voltage of 600 V and Eoff of the proposed one is reduced by 3.7%. The measured inductive load switching characteristics also shows that Eoff of proposed one is improved by 7.2%.     

具有沟槽阳极短路的新型沟槽栅场截止绝缘栅双极晶体管

文章提出了一种新型的具有沟槽阳极短路的槽栅场截止型绝缘栅双极晶体管结构。通过引入沟槽短路阳极结构,器件的击穿电压得到了明显提高。仿真结果显示,相比于传统的场截止型绝缘栅双极晶体管,新结构提高了19.5 %的击穿电压,而且新结构具有更小的漏电流。在电流密度为150 A/cm2 时,新结构虽然提高了近百分之九的导通压降,但是关断时间只有传统结构的一半。此外,新结构导通时没有负阻效应。因此,新结构具有更好的关断功耗与导通压降的折中关系。     

A New SOI LDMOSFET Structure with a Trench in the Drift Region for a PDP Scan Driver IC

To improve the characteristics of breakdown voltage and specific on‐resistance, we propose a new structure for a LDMOSFET for a PDP scan driver IC based on silicon‐on‐insulator with a trench under the gate in the drift region. The trench reduces the electric field at the silicon surface under the gate edge in the drift region when the concentration of the drift region is high, and thereby increases the breakdown voltage and reduces the specific on‐resistance. The breakdown voltage and the specific on‐resistance of the fabricated device is 352 V and 18.8 m·cm² with a threshold voltage of 1.0 V. The breakdown voltage of the device in the on‐state is over 200 V and the saturation current at V_gs=5 V and V_ds=20 V is 16 mA with a gate width of 150 µm.     

Trench SJ IGBT 的仿真研究

本文对沟槽型超结绝缘栅双极晶体管(trench SJ IGBT)进行了全面的分析,并通过Sentaurus TCAD仿真软件将其与沟槽型场截止绝缘栅双极晶体管(trench FS IGBT)进行了详尽的对比,仿真结果显示,在相同的条件下与trench FS IGBT 相比,trench SJ IGBT 的击穿电压提高了100 V,饱和导通压降降低了0.2 V,关断损耗减少了50%。最后,文章研究了电荷不平衡对trench SJ IGBT 的动静态参数的影响。对各参数和它们对电荷不平衡的灵敏度之间的折中进行了讨论。