402～405 MHz CMOS低功耗射频收发机北大核心

基于0.18μm CMOS工艺设计了一种用于WBAN 402～405 MHz频段具有低功耗全数字锁频和灵敏度校准功能的超再生收发机。采用具有噪声抵消技术的巴伦低噪声放大器，以减少无源匹配器件数量和适应低压工作；超再生数控振荡器采用数字控制电容阵列实现频率调谐，以消除猝灭操作期间振荡器的频率漂移；采用全数字锁频环替代频率综合器，以降低传感器节点的功耗；灵敏度校准环路与自动幅度控制环路共享组件，以减小校准误差，并能够在不中断接收状态的情况下动态校准接收机灵敏度。仿真结果表明，在1 V电源电压下，接收机灵敏度为-90 dBm,功耗为1.89 mW,其中全数字锁频环功耗为78μW;发射机功耗为1.96 mW,效率为28%。     

应用于无线传感网的低功耗CMOS温度传感器

为了在较大的温度范围内改善传感器的线性并降低功耗,提出一种新的应用于无线传感网的频率输出温度传感器。采用了多谐振荡器电流转频率电路,主要由一个双向电流积分器组成,由电压窗口比较器驱动,由单独的1.2 V供给电压,并利用低成本的0.18 μm CMOS技术制作。实验结果表明,在?40°C到+120°C的温度范围内,该温度传感器表现出高线性的特点,实现了±1°C的误差,敏感性分别为340 Hz /°C,功耗为2.1 μW,面积为0.02 mm2,十分适合无线传感网的各种应用。     

Adaptive Low Power Listening for Wireless Sensor Networks

Most sensor networks require application-specific network-wide performance guarantees, suggesting the need for global and flexible network optimization. The dynamic and nonuniform local states of individual nodes in sensor networks complicate global optimization. Here, we present a cross-layer framework for optimizing global power consumption and balancing the load in sensor networks through greedy local decisions. Our framework enables each node to use its local and neighborhood state information to adapt its routing and MAC layer behavior. The framework employs a flexible cost function at the routing layer and adaptive duty cycles at the MAC layer in order to adapt a node's behavior to its local state. We identify three state aspects that impact energy consumption: 1) number of descendants in the routing tree, 2) radio duty cycle, and 3) role. We conduct experiments on a test-bed of 14 mica2 sensor nodes to compare the state representations and to evaluate the framework's energy benefits. The experiments show that the degree of load balancing increases for expanded state representations. The experiments also reveal that all state representations in our framework reduce global power consumption in the range of one-third for a time-driven monitoring network and in the range of one-fifth for an event-driven target tracking network.     

应用于射频收发机的低功耗频率综合器

基于0.18μm 1P6M CMOS工艺,设计并实现了一种用于工作在2.4 GHz ISM频段的射频收发机的整数型频率综合器。频率综合器采用锁相环结构,包括片上全集成的电感电容压控振荡器、正交高频分频器、数字可编程分频器、鉴频鉴相器、电荷泵、二阶环路滤波器,为接收机提供正交本地振荡信号并驱动功率放大器。通过在PCB板上绑定裸片的方法进行测试,测试结果表明,压控振荡器的频率覆盖范围为2.338～2.495 GHz;锁定频率为2.424 GHz时,频偏3 MHz处的相位噪声为-113.4 dBc/Hz,带内相位噪声为-65.9 dBc/Hz;1 MHz处的参考杂散为-45.4 dBc,满足收发机整体性能指标的要求。在1.8 V电源电压下,频率综合器整体消耗电流仅为6.98 mA。芯片总面积为0.69 mm×0.56 mm。     

用于无线局域网的CMOS射频前端发送器

介绍了一种用于802.11b无线局域网的高线性度射频前端发送器的设计与实现。该发送器采用直接转换结构,从而最大程度地减小了所需的片外和片上元件。电路采用0.18μmCMOS工艺实现。发送器包括两个低通滤波器、一个单边带混频器、一个功率预放大器和一个产生正交本振信号的除2分频器。发送器能够以3 dB一级提供12 dB的增益控制,输出1 dB压缩点为7.7 dBm,正常输出功率为2 dBm。整个发送器工作时消耗电流40 mA,工作电压1.8 V,芯片面积(不包括焊盘)为1.8 mm×1.5 mm。     

An Energy-Efficient OOK Transceiver for Wireless Sensor Networks

A 1-Mb/s 916.5-MHz on-off keying (OOK) transceiver for short-range wireless sensor networks has been designed in a 0.18-mum CMOS process. The receiver has an envelope detection based architecture with a highly scalable RF front-end. Untuned RF circuits are leveraged and optimized in the receiver to achieve superior energy efficiency compared to tuned RF circuits. The receiver power consumption scales from 0.5 mW to 2.6 mW, with an associated sensitivity of -37 dBm to -65 dBm at a BER of 10 ^-3. The transmitter consumes 3.8 mW to 9.1 mW with output power from -11.4 dBm to -2.2 dBm. The receiver achieves a startup time of 2.5 mus, allowing for efficient duty cycling     

A Fully Integrated CMOS Active Bandpass Filter for Multiband RF Front-Ends

In this paper, design techniques for an integrated RF bandpass filter are discussed. A novel wide-tuning high-$Q$ active bandpass filter utilizing the active inductors is presented. Issues of the active inductor related to $Q$-enhancement, noise, linearity, and stability are considered. The circuit has been fabricated in an 0.18-$mu$m CMOS process, and the filter occupies the active area of 150$,times,$ 200 $mu$m $^{2}$. Measurement results show that the filter centered at 3.82 GHz with about 36-MHz bandwidth (3-dB) is tunable in frequency from about 1.92 to 3.82 GHz, and it exhibits $-$ 15- to 1-dB compression point at 2.44 GHz with approximately 60-MHz bandwidth while the dc power consumes 10.8 mW.      

一种低功耗的多跳无线传感网时间同步算法

高精度低功耗的时间同步对于无线传感网络至关重要,文中重点分析了高精度时间同步算法,发现其在多跳网络时间同步过程中由于每跳范围内所有节点均要广播时间同步包,会产生大量的冗余信息。为降低同步功耗,提出了一种新方法,通过调节发射功率,筛选出每一跳范围内的周边节点,使其完成下一跳范围的时间同步,而非周边节点只接受却不发送时间同步包。最后,针对改进的算法在OMNet++上进行了仿真实验,仿真结果表明,改进后的算法能够有效地降低全网能量消耗。     

802.11b收发系统中的全集成低功耗发送机设计

基于SMIC 0.18μm CMOS工艺,设计了一个应用于IEEE 802.11b收发系统的全集成低功耗发送机.直接转换发送机包括两个Chebyshev Ⅰ型低通滤波器,两个可编程增益放大器(PGA),一个单边带混频器和一个功率预放大器.发送机以3dB为步长提供32dB增益,其最大输出功耗为-3.4dBm,EVM为6.8%.工作在1.8V电源电压,发送机的功耗仅57.6mW.发送机芯片面积为1.6mm×1.6mm.     

Low Power Downlink MAC Protocols for Infrastructure Wireless Sensor Networks

This paper addresses low power medium access control (MAC) protocols for the downlink channel of infrastructure wireless sensor networks. Access points are assumed to be energy unconstrained. The trade-off between the power consumption of the sensor nodes and the transmission delay is analyzed, focusing on low traffic. We describe WiseMAC (Wireless Sensor MAC), a new protocol for the downlink of infrastructure wireless sensor networks. Another original contribution is the presentation and analysis of PTIP (Periodic Terminal Initiated Polling). Here, polling is used in the reversed direction as compared to common polling protocols. WiseMAC and PTIP are compared with PSM (Power Save Mode), the power save protocol used in both the IEEE 802.11 and IEEE 802.15.4 ZigBee standards. Analytical expressions are derived for the power consumption and the transmission delay for each protocol, as a function of the wake-up period. It is shown that WiseMAC provides, with low bit rate radio transceivers, a significantly lower power consumption than PSM. Although less energy efficient than WiseMAC and PSM, it is shown that PTIP can, thanks to its implementation simplicity, become attractive for applications tolerating large transmission delays.Amre El-Hoiydi received the electrical engineer degree from the Swiss Federal Institute of Technology in Zurich (ETHZ), Switzerland, in 1994. In 1995, he was a teaching assistant at the Swiss Federal Institute of Technology in Lausanne (EPFL), working on mobility management for low earth orbit mobile satellite communication systems. In 1996, he joined CSEM (Neuchâtel, Switzerland). Since then, he has been working on several research and development projects dealing with various aspects of wireless communications. In the ACTS RAINBOW and FRAMES projects, he was involved with the network and air interface aspects of 3rd generation cellular systems. In the ESPRIT INFOGATE and IST OPENROUTER projects, he worked on electronic design and embedded programming of Linux based wireless LAN gateways. His current research focus is low power communication protocols for wireless sensor networks.Jean-Dominique Decotignie is head of the real-time and networking group at the Swiss Center for Electronics and Microsystems (CSEM) in Neuchâtel. He is professor at the School of Computer and Communication Sciences of EPFL (Swiss Federal Institute of Technology in Lausanne) and teaches real-time systems as well as hardware and software design. From 1977 to 1982, he has worked at EPFL and the University of Tokyo in the area of optical communications. In 1983, he joined the Industrial Computer Engineering Lab. at EPFL where he became Assistant Professor in 1992. From 1989 to 1992, he has been the head of an interdisciplinary project on Computer Integrated Manufacturing at EPFL. Since January 1997, he is with CSEM. His current research interests include industrial and real-time local area networks, distributed control systems and software engineering for real-time systems as well as real-time wireless networks.     

低电压低功耗CMOS 5Gb/s串行收发器

设计并实现了一种使用0.13μm CMOS 工艺制造的低电压低功耗串行收发器.它的核心电路工作电压为1V,工作频率范围为2.5~5GHz.发送器包括一个20:1的串行器和一个发送驱动器,其中发送驱动器采用了预加重技术来抵消传输信道对信号的衰减,降低信号的码间串扰.接收器包括一个输入信号预放大器,两个1:20的解串器以及时钟恢复电路.在输入信号预放大器中设计了一个简单新颖的电路,利用前馈均衡来进一步消除信号的码间串扰,提高接收器的灵敏度.测试表明,收发器功耗为127mW/通道.发送器输出信号均方根抖动为4ps.接收器在输入信号眼图闭合0.5UI,信号差分峰-峰值150mV条件下误码率小于10-12.     

低电压低功耗CMOS 5Gb/s串行收发器

设计并实现了一种使用0.13μm CMOS 工艺制造的低电压低功耗串行收发器.它的核心电路工作电压为1V,工作频率范围为2.5~5GHz.发送器包括一个20:1的串行器和一个发送驱动器,其中发送驱动器采用了预加重技术来抵消传输信道对信号的衰减,降低信号的码间串扰.接收器包括一个输入信号预放大器,两个1:20的解串器以及时钟恢复电路.在输入信号预放大器中设计了一个简单新颖的电路,利用前馈均衡来进一步消除信号的码间串扰,提高接收器的灵敏度.测试表明,收发器功耗为127mW/通道.发送器输出信号均方根抖动为4ps.接收器在输入信号眼图闭合0.5UI,信号差分峰-峰值150mV条件下误码率小于10-12.     

用于无线传感网络低功耗亚阈值CMOS低噪声放大器设计

设计一种工作在亚阈值区的低功耗CMOS低噪声放大器(LNA),用于无线传感网络.为了满足低功耗和高增益,设计使用共源共栅(cascode)结构并利用UMC 65nm工艺库进行仿真分析.仿真结果表明,在780MHz中心频率下,电路的增益大约34 dB,功耗仅为55μW,电源电压为1.2V.     

一种全集成CMOS数字电视调谐器射频前端

设计了一种全集成CMOS数字电视调谐器(DTV tuner)射频前端电路.该电路采用二次变频低中频结构,集成了低噪声放大器、上变频混频器、下变频混频器等模块.芯片采用0.18μm CMOS工艺实现,测试结果表明,在50～860MHz频率范围内,射频前端能够实现很好的输入阻抗匹配,并且总的增益变化范围达到20dB.其中,在最大增益模式下,电压增益为 33dB,单边带噪声系数(SSB NF)为9.6dB,输入参考三阶交调点(ⅡP3)为-11Bm;在最小增益模式下,电压增益为 14dB,单边带噪声系数为28dB,输入参考三阶交调点为 8dBm.射频前端电路面积为1.04mm×0.98mm,工作电压为1.8V,消耗电流为30mA.     

一种全集成CMOS数字电视调谐器射频前端

设计了一种全集成CMOS数字电视调谐器(DTV tuner)射频前端电路.该电路采用二次变频低中频结构,集成了低噪声放大器、上变频混频器、下变频混频器等模块.芯片采用0.18μm CMOS工艺实现,测试结果表明,在50～860MHz频率范围内,射频前端能够实现很好的输入阻抗匹配,并且总的增益变化范围达到20dB.其中,在最大增益模式下,电压增益为+33dB,单边带噪声系数(SSB NF)为9.6dB,输入参考三阶交调点(ⅡP3)为-11Bm;在最小增益模式下,电压增益为+14dB,单边带噪声系数为28dB,输入参考三阶交调点为+8dBm.射频前端电路面积为1.04mm×0.98mm,工作电压为1.8V,消耗电流为30mA.     

低功耗人体通信射频收发器的设计

Human body communication is proposed as a promising body proximal communication technology for body sensor networks. To achieve low power and small volume in the sensor nodes, a Radio Frequency (RF) application-specific integrated circuit transceiver for Human Body Communication (HBC) is presented and the characteristics of HBC are investigated. A high data rate On-Off Keying (OOK)/Frequency-Shift Keying (FSK) modulation protocol and an OOK/FSK demodulator circuit are introduced in this paper, with a data-rate-to-carrier-frequency ratio up to 70% . A low noise amplifier is proposed to handle the dynamic range problem and improve the sensitivity of the receiver path. In addition, a low power automatic-gain-control system is realized using a novel architecture, thereby rendering the peak detector circuit and loop filter unnecessary. Finally, the complete chip is fabricated. Simulation results suggest receiver sensitivity to be -75 dBm. The transceiver shows an overall power consumption of 3.2 mW when data rate is 5 Mbps, delivering a P1 dBoutput power of -30 dBm.     

A Fully Integrated UHF CMOS Power Amplifier for Spacecraft Applications

A power amplifier (PA) is designed for a surface-to-orbit proximity link microtransceiver on Mars exploration rovers, aerobots, and small networked landers and works in conjunction with a 0.2-dB loss transmit/receive switch to allow nearly the full 1 W to reach the antenna. The fully integrated UHF CMOS PA with more than 30-dBm output is reported for the first time. A differential pMOS structure with floating-bias cascode transistors and 1:3-turn ratio output transformer are chosen to overcome low breakdown voltage (V _bk) of CMOS and chip area consumption issues at UHF frequencies. The high-Q on-chip transformer on a sapphire substrate enables the differential PA to drive a single-ended antenna effectively at 400 MHz. The PA in a standard package delivers 30-dBm output with 27% power-added efficiency. No performance degradation was observed in continuous-wave operation and the design has been tested to 136% of its nominal 3.3-V supply without failure.     

A WiMedia/MBOA-Compliant CMOS RF Transceiver for UWB

A WiMedia/MBOA compliant RF transceiver for ultra-wideband data communication in the 3-5-GHz band is presented. The transceiver includes receiver, transmitter and synthesizer is completely integrated in 0.13-mum standard CMOS technology. The receiver uses a feedback-based low-noise amplifier (LNA) to obtain an RF gain of 4 to 37 dB and an overall measured noise figure of 3.6 to 4.1 dB over the 3-5-GHz band of interest. The transmitter supports an error vector magnitude (EVM) of -28 dB up to -4 dBm output power and meets the FCC and WiMedia mask specifications. The power consumption from a single supply voltage of 1.5 V is 237 mW for the receiver and 284 mW for the transmitter, both including the synthesizer     

面向多传感器模块接入的低功耗无线传感器节点

设计了一种面向多传感器模块接入的低功耗无线传感器节点。该节点基于超低功耗Zigbee单片机MC13224V设计,由射频模块、配置电路和电源系统等组成。根据无线通信系统的特点设计了系统的软硬件,详细阐述了硬件设计、软件设计及性能测试方法。测试结果证明：在3V电源供电条件下,休眠时电流小于11μA,实现了低功耗设计的目的。