Simultaneous Demodulation and Clock-Recovery of 40-Gb/s NRZ-DPSK Signals Using a Multiwavelength Gaussian Filter

We demonstrate a novel optical circuit that has the potential of simultaneous demodulation and all-optical clock-recovery of 40-Gb/s wavelength-division-multiplexing nonreturn-to-zero differential phase-shift keying (NRZ-DPSK) signals. A key device of the circuit is an ad hoc periodic fiber Bragg grating filter that simultaneously demodulates the input signals and seeds a series of clock recovery circuits. We report the complete characterization of the proposed scheme in the whole-band using a tunable transmitter. The DPSK demodulated signals show enhanced resilience to chromatic dispersion with respect to the usual NRZ _ON-OFF keying format. On the other hand, the recovered clock signals are very stable and have around 200-fs root-mean-square time jitter.     

A CMOS high-speed data recovery circuit using the matched delaysampling technique

This paper presents a scheme and circuitry for demultiplexing and synchronizing high-speed serial data using the matched delay sampling technique. By simultaneously propagating data and clock signals through two different delay taps, the sampler achieves a very fine sampling resolution which is determined by the difference between the data and clock delays. This high resolution sampling capability of the matched delay sampler can be used in the oversampling data recovery circuit. A data recovery circuit using the matched delay sampling technique has been designed and fabricated in 1.2-μm CMOS technology. The chip has been tested at 417 Mb/s [2.4 ns nonreturn to zero (NRZ)] input data and demultiplexes serial input data into four 104 Mb/s (9.6 ns NRZ) output streams with 800 mW power consumption at 4 V power supply. While recovering data, the sampling clock running at 1/4 of the data frequency is phase-tracking with the input data based on information extracted from a digital phase control circuit     

Novel broad-band bit-synchronization circuit module for optical interconnections

A novel broad-band and ultrafast bit-synchronization circuit module is proposed and fabricated for optical interconnections. In optical packet switch fabric or optical interconnection between electric circuit boards, instantaneous bit synchronization is crucial to properly retime incoming packets with a random phase and reduce the number of preamble overhead bits. The developed bit-synchronization circuit module has a new clock selection circuit, which is configured with a phase comparator and an amplitude comparator. Since device-dependent delay circuits, such as buffer amplifiers or RC phasors, are not adopted, the newly developed clock selection circuit can operate under broad-band frequencies. The bit-synchronization circuit module was fabricated with a Si-bipolar gate array and it can operate at broad-band bit rates of up to 10.5 Gb/s. It also exhibits a power sensitivity penalty as low as 3 dB for 10-Gb/s input signals. The synchronization acquisition time of less than 9 b over the entire 360/spl deg/ phase range was confirmed by experiment.     

All-Optical 3R Burst-Mode Reception at 40 Gb/s Using Four Integrated MZI Switches

We demonstrate an all-optical retime, reshape, reamplify (3R) burst-mode receiver (BMR) operating error-free with a 40-Gb/s variable-length asynchronous optical data packets that exhibit up to 9-dB packet-to-packet power variation. The circuit is completely based upon hybrid integrated Mach-Zehnder interferometric (MZI) switches as it employs four cascaded MZIs, each one performing a different functionality. The 3R burst-mode reception is achieved with the combination of two discrete all-optical subsystems. A reshape, reamplify BMR employing a single MZI is used first to perform power equalization of the incoming bursts and provide error-free data reception. This novel approach is experimentally demonstrated to operate error-free, even for a 9-dB dynamic range of power variation between bursty data packets and for a wide range of average input power. The obtained power-equalized data packets are then fed into a 3R regenerator to improve the signal quality by reducing the phase and amplitude jitter of the incoming data. This packet-mode 3R regenerator employs three MZIs that perform wavelength conversion, clock extraction, and data regeneration for every packet separately and operates at 40 Gb/s, exhibiting rms timing jitter reduction from 4 ps at the input to 1 ps at the output and a power penalty improvement of 2.5 dB     

一种适用于SoC的时钟复位管理电路设计

给出了一套适用于SoC芯片的时钟和复位管理电路设计范例,详细介绍了SoC芯片中的时钟和复位管理电路的实现方案。其中时钟管理电路支持输入时钟可选、PLL动态变频、时钟门控管理和时钟状态查询功能,能够灵活的控制各模块输入时钟开启或关闭,很好的支持SoC芯片低功耗工作模式。复位管理电路支持复位输入控制功能和复位状态查询功能。复位输入控制可以选择使能或不使能复位源触发系统复位。     

钟控准静态能量回收逻辑电路

钟控准静态能量回收逻辑 (clocked quasi- static energy recovery logic,CQSERL)只在输入信号导致输出状态发生变化的情况下才对电路节点充电 (或者回收 ) ,不需要在每个功率时钟周期循环充电和回收操作 ;CQSERL是单端输入输出逻辑 ,减小了电路实现代价 .设计了 4位 QSERL 串行进位加法器 (RCA)电路 ,和相应的 CMOS电路进行了功耗比较 .功率时钟为 10 MHz时 ,CQSERL 电路功耗是对应 CMOS电路的 35 % .流片实现了一个简单结构的正弦功率时钟产生电路 ,功率时钟的频率和相位与外接系统时钟相同     

Low power flip-flop with clock gating on master and slave latches

A new flip-flop is presented in which power dissipation is reduced by deactivating the clock signal on both the master and slave latches when there are no data transitions. The new circuit overcomes the clock duty-cycle constraints of previously proposed gated flip-flops. The power consumption of the presented circuit is significantly lower than that of a conventional flip-flop when the D input has a reduced switching activity     

基于门控多路环形振荡器的时间数据转换器

A gated ring oscillator(GRO) based time-to-digital converter(TDC) is presented.To enhance the resolution of the TDC,a multi-path structure for the GRO is used to achieve a higher oscillation frequency and an input stage is also presented to equivalently amplify the input time difference with a gain of 2.The GRO based TDC circuit is fabricated in TSMC 65 nm CMOS technology and the core area is about 0.02 mm~2.According to the measurement results,the effective resolution of this circuit is better than 4.22 ps under a 50 MHz clock frequency. With a 1 ns input range,the maximum clock frequency of this circuit is larger than 200 MHz.Under a 1 V power supply,with a 200-800 ps input time difference,the measured power consumption is 1.24 to 1.72 mW at 50 MHz clock frequency and 1.73 to 2.20 mW at 200 MHz clock frequency.     

一种用于高速流水线ADC的时钟管理器

文章设计了一种用于高速流水线ADC的时钟管理器,该电路以延迟锁相环(DLL)电路为核心,由偏置电路、时钟输入电路、50%占空比稳定电路和无交叠时钟电路构成。该电路用0.35μmBiCMOS工艺条件下cadence spectre仿真。由测量结果可知,时钟管理器可以实现70MHz~300MHz有效输出。在250MHz典型频率下测得峰值抖动为16ps,占空比为50%,功耗为47mW。仿真结果表明该时钟管理器具有高速度、高精度、低功耗的特点,适用于高速流水线ADC。     

Packet-format and network-traffic transparent optical signal processing

In this paper, we demonstrate optical transparency in packet formatting and network traffic offered by all-optical switching devices. Exploiting the bitwise processing capabilities of these "optical transistors," simple optical circuits are designed verifying the independency to packet length, synchronization and packet-to-packet power fluctuations. Devices with these attributes are key elements for achieving network flexibility, fine granularity and efficient bandwidth-on-demand use. To this end, a header/payload separation circuit operating with IP-like packets, a clock and data recovery circuit handling asynchronous packets and a burst-mode receiver for bursty traffic are presented. These network subsystems can find application in future high capacity data-centric photonic packet switched networks.     

基于DSP开发系统设计与实现

为了设计一个性能稳定的DSP开发系统,利用TI公司最新推出的TMS320F28335作为微处理器,该芯片为32位浮点型DSP。在采用浮点DSP设计系统时,不需要考虑处理的动态范围和精度,比定点DSP在软件编写方面更容易,更适合采用高级语言编程。外围电路主要包含电源电路、RAM扩展电路、晶振电路和复位电路,用来辅助DSP的工作。利用电源管理芯片设计电源电路,可以有效解决其他型号的DSP对上电顺序的要求;扩展的外部RAM可以使程序的调试与下载更加方便。利用外部时钟源作为时钟输入,使其输入时钟更加稳定的同时,也可为具有相同时钟的多个DSP使用。利用三端监控芯片来实现系统的手动复位和自动复位,使系统的稳定性大大提高。     

Variable Length Optical Packet Synchronizer

Synchronization of asynchronously arriving variable length Internet Protocol packets to a local clock is demonstrated using a fiber-based optical synchronizer. The synchronizer is a four-stage feed-forward design with a resolution of 853 ps and a dynamic tuning range of 12.8 ns. The arrival time of packets is determined on a per packet basis using a payload envelope detection technique. The synchronizer state is dynamically configured on a per packet basis determined from the arrival time. Layer-1 (bit-error-rate) measurements are presented with power penalties 0.5 dB and an input power dynamic range 15 dB. Layer-2 (packet recovery) measurements are presented with power penalties 1.5 dB.     

一款基于解调信号相位矫正技术的低噪声微陀螺接口电路芯片

该文针对设计了一款基于解调信号相位矫正技术的低噪声微陀螺接口电路芯片。读出电路采用全差分跨阻放大器结构优化噪声性能,获得了0.63 aF/\sqrt{Hz}的等效输入电容噪声。检测通路中采用双通道正交解调技术和解调信号相位矫正技术,完全消除了机械正交信号的干扰。芯片在0.35m CMOS工艺下实现,与电容式微陀螺的联合测试表明,微陀螺系统的输入等效噪声为0.01/s/\sqrt{Hz},在8.5 mV//s标度因子和5 V供电电压条件下,陀螺量程达到了200/s,线性度为2 。     

Dynamics of all-optical clock recovery using two-section index- and gain-coupled DFB lasers

The dynamics of coherent clock recovery (CR) using self-pulsing two-section distributed feedback (TS-DFB) lasers have been investigated. Both simulation and experimental results indicate fast lockup and walk-off of the clock-recovery process on the order of nanoseconds. Phase stability of the recovered clock from a pseudorandom bit sequence (PRBS) signal can be achieved by limiting the detuning between the frequency of free-running self-pulsation and the input bit rate. The simulation results show that all-optical clock recovery using TS-DFB lasers can maintain a better than 5% clock phase stability for large variations in power, bit rate, and optical carrier frequency of the input data and therefore is suitable for applications in optical packet switching.     

一种新型超高速高精度时钟占空比校准电路

设计了一种超高速高精度时钟占空比校准电路。采用一种新的脉冲宽度校准单元,通过控制电压调整时钟上升、下降时间来实现占空比调整。同时,设计了一种时钟放大模块,降低了占空比校准单元对输入时钟幅度的要求,提高了占空比校准精度。分析了各电路模块的作用以及对整体性能的影响。采用SMIC 65 nm CMOS工艺,在1.8 V电源电压下对各模块以及整体电路进行仿真验证。仿真结果表明,该时钟占空比校准电路能对输入频率为1～4 GHz、占空比为20%～80%的时钟进行精确校准,校准后的占空比为(50±1)%,系统稳定时间为200个输入时钟周期,功耗为10 mW。     

An analog PLL-based clock and data recovery circuit with high inputjitter tolerance

A clock and data recovery circuit for a T1 network is described. A fully integrated phase-locked loop (PLL) extracts the carrier signal embedded in the data. Two trimming DACs simultaneously bring the VCO center frequency and the PLL closed-loop bandwidth to their specified values. A triple sampler captures the jittering data and aligns them with the recovered clock. The input jitter of this circuit is three times more than previously reported PLL-based circuits     

一种高动态范围、低功耗UHF RFID标签解调器的设计

本文对传统的解调电路进行了改进,设计了一种能解调高动态范围RF输入信号的电路。该电路结构简单,易于集成,并具有低功耗、高动态范围、高稳定性的特点。电路采用SMIC 0.18μm CMOS工艺进行设计,在spectre环境下的仿真结果表明该电路符合ISO/IEC 18000-6C标准能解调的的ASK信号动态范围为250mV-5V,静态功耗<1μW。     

基于AD9208的高速采集电路设计

针对大带宽采样需求,设计了基于AD9208的高速采集电路,通过分析时钟抖动,噪声等因素对采集电路的影响,设计了相关电路,包括低抖动时钟电路、模拟信号输入电路、电源电路,并测试了在不同输入频率下,AD9208的无杂散动态范围.     

A multibitrate burst-mode CDR circuit with bit-rate discriminationfunction from 52 to 1244 Mb/s

We fabricate and assess a clock and data recovery (CDR) circuit with a bit-rate discrimination (BRD) function that can receive burst-mode signals containing packets of different bit rates. The clock recovery circuit in the CDR circuit consists of gated oscillators (GOs) for handling the burst-mode signals, whose bit rates vary with each packet. Moreover, we improve the performance of the clock recovery circuit based on GOs against the bit rate unevenness around each bit rate. By combining an agile clock recovery circuit and a digital BRD circuit, the CDR circuit can handle multiplexed bit rates. Tests show that the circuit offers excellent performance for the multiplexed bit rates of nonreturn-to-zero 52, 155, 622, and 1244 Mb/s     

基于数据驱动动态逻辑电路的桶形移位器设计

介绍了一种新型数据驱动的动态逻辑电路。该电路去除了时钟信号,利用适当的输入数据来保持电路正确的逻辑操作。基于数字驱动的动态逻辑电路,设计了一种新型低功耗、高性能的8位桶形移位器。仿真结果表明,在相同的工作频率下,与基于传统动态逻辑电路的8位桶形移位器相比,新型8位桶形移位器的版图面积减少了40%,速度提高了17%,功耗-延迟积减少了14%。