彩色PDP发光效率的计算

提高发光效率是目前彩色PDP发展所面临的亟待解决的重要课题之一。为了正确计算该参数，本文经过适当简化，证明了计算彩色PDP发光效率的数学表达式。     

107cm彩色PDP显示屏及模块的研究开发

建成大屏蔽彩色PDP显示屏试验线,开发了部分关键设备,建立全套自主开发的适合批量生产的彩色PDP显示屏制作工艺,开发了采色PDP显示模块电路。     

彩色等离子体显示器自动功率控制方法研究

为降低彩色等离子体显示器(PDP)的功耗,提高图像质量,在分析了寻址功耗和图像数据在各子场列方向上的变化率有关的基础上,根据自动功率控制(APC)的原理提出了自动功率控制的方法,该方法的主要内容包括:图像最小残像工作模式,图像信号的平均强度和维持脉冲数的关系,图像负载率和亮度及功耗的关系等.根据以上APC的原理和方法研制的107cm(42英寸)彩色PDP电路在功耗和图像质量方面均达到设计目标.     

LCD的RGBY四像素技术和画质（下）

二、LCD的功率损耗 LCD作为光阀器件需要光源配合支持才能显像。微功耗（0．2w／m2）LCD器件选择优秀的CCFL／LED光源,CCFL发光效率为70lm／w,是PDP器件的20倍以上。LED的流明效率更高,而且其发展遵守摩尔定律,20个月亮度翻一倍。从调光器件与被调光源分离独立的角度看,没有人会质疑LCD显示技术的节能性,但专门研究机构测试的数据表明LCD的发光效率约8％,其余92％的能量在成像过程中白白损耗掉了。     

彩色PDP放电单元参数设置分析

本文对三电极表面放电反射结构彩色PDP放电单元进行了等效和分析,利用一实验验证及计算机模拟的结果,研究了放电单元的一些参数变化对单元亮度、功耗以及发光效益的影响,为彩色PDP的单元设计提供了一定的参考。     

新型高发光效率等离子体显示技术

对PDP面临的技术瓶颈和发光效率进行了分析,重点介绍了基于纳米多孔多晶硅电子源的新型高发光效率PDP显示技术,简要讨论了无放电气体激发发光技术对PDP未来发展可能产生的影响。     

高分辨率彩色等离子体显示屏及模块的开发

在完成了107 cm WVGA彩色等离子体显示(PDP)屏及模块研究和开发的基础上,又进行了对角线为64 cm、单元节距为0.63 mm×0.63 mm、分辨率为SVGA(800×600)的彩色PDP显示屏的工艺及模块电路的研究和开发.在适合高分辨显示的彩色PDP显示屏和模块电路方面进行了努力,开发出具有SVGA物理分辨率的64 cm彩色PDP显示屏和模块.     

PDP技术的新发展

彩色等离子体显示板(PDP)是20世纪90年代中期开始量产的新型平板显示器件。由于它工作在全数字化模式，易于制成大屏幕显示，是数字化彩电、高清晰度电视和多媒体终端理想的显示器件，在102～153cm范围内具有极强的竞争力，是CRT更新换代的产品。目前PDP面临的两个关键技术问题，一是发光效率不高，二是生产成本高。本文就提高PDP性能的方法进行了描述。     

等离子显示技术的新进展

介绍了等离子显示屏的单元结构、放电机理、驱动技术以及图像处理技术等方面的研究内容和重要进展,对等离子显示器发光效率达到5 lm/W和10 lm/W时,PDP可能的单元结构以及引起的亮度、功耗、驱动电路系统架构的变化进行了分析,特别是对PDP成本的变化趋势进行了预测.     

高分辨率彩色AC PDP

一、前言人们为实现信息终端机的小型化和轻量化而采用多种平板显示器。其中,单色等离子体显示板(PDP)和液晶显示板(LCD)正在膝上计算机中使用。LCD 虽耗电少,用干电池即可驱动,但视角小,响应速度慢,故在高级膝上计算机中,现在使用的是 PDP。PDP 有 AC 型和 DC 型两种,由于 DC 型的驱动电路便宜,而成为当前的主流。但是,个人计算机用的软件大部分是彩色的,因此,PDP 的彩色化是一个重要课题。对于彩色显示,就亮度和寿命而言,用 AC PDP 较好。在 AC PDP 中,面放电型 AC PDP 具有记忆机能,无闪烁、亮度高、发光效率高且结构简单。因此,面放电 AC PDP 是实现 PDP 彩色化最有希望的器件。     

Color plasma displays

After decades of research and development, plasma displays are finally beginning to appear in the commercial and consumer markets. Following a short review on the basic principles of direct and alternating current plasma displays, we present a summary of the status of color plasma displays. Plasma display panels (PDPs) have finally achieved luminance and efficiency values on par with hi-definition cathode ray tube monitors. Additional improvements in performance will open up a new world of large PDP displays. Ultimately, what will drive the PDP market will be continued improvements in the performance of color PDPs themselves. PDP makers are working on reducing power consumption through improved luminous efficiency and improved component materials and manufacturing methods of color PDPs. With improvements in the cell structure and driving methods, there is a good prospect of achieving a luminous efficiency of 2-3 lm/W and a power consumption of about 200 W for 50-in diagonal size     

Tunable high-frequency Gm-C filters

We consider known, modified, and new transistor circuits for transconductors and some theory on their application in integrated tunable Gm-C or transconductor-eapacitor filters for high frequencies. The circuits are balanced and mostly complementary. They use bipolar (NPN and VPNP) and/or CMOS transistors. The low delay and low input capacitance of the newer circuits makes them particularly suitable for very high frequencies, in the hundreds of megahertz. The relatively high power efficiency and low noise lead to a low power consumption in combination with a high signal-to-noise ratio. Their simplicity results in a small chip area and hence in low cost. The partly new theory is on noise, sensitivities, quality factors, linearization, power and power efficiencies     

锂离子电池的保护芯片设计

设计了一种基于CMOS工艺的锂离子电池保护芯片,采用工作在亚阈值区的电路结构,使电路具有高效低耗的特点,能够防止电池在工作过程中出现过充电、过放电、过电流和短路等异常状态。模拟结果表明,该芯片实现了基本保护功能并在功耗方面达到了设计目标。     

High performance low power CMOS dynamic logic for arithmetic circuits

This paper presents the design of high performance and low power arithmetic circuits using a new CMOS dynamic logic family, and analyzes its sensitivity against technology parameters for practical applications. The proposed dynamic logic family allows for a partial evaluation in a computational block before its input signals are valid, and quickly performs a final evaluation as soon as the inputs arrive. The proposed dynamic logic family is well suited to arithmetic circuits where the critical path is made of a large cascade of inverting gates. Furthermore, circuits based on the proposed concept perform better in high fanout and high switching frequencies due to both lower delay and dynamic power consumption. Experimental results, for practical circuits, demonstrate that low power feature of the propose dynamic logic provides for smaller propagation time delay (3.5 times), lower energy consumption (55%), and similar combined delay, power consumption and active area product (only 8% higher), while exhibiting lower sensitivity to power supply, temperature, capacitive load and process variations than the dynamic domino CMOS technologies.     

Efficient synthesis algorithm for low-power ASIC design

The authors propose an efficient synthesis algorithm for the synthesis of RT-level hardware with low power consumption. The proposed algorithm minimises the overall power consumption of generated datapath by reducing spurious operations. Experimental results for several benchmark circuits under various synthesis constraints show the efficiency of the proposed algorithm     

LFSR Reseeding-Oriented Low-Power Test-Compression Architecture for Scan Designs

Massive test data volume and excessive test power consumption have become two strict challenges for very large scale integrated circuit testing. In BIST architecture, the unspecified bits are randomly filled by LFSR reseeding-based test compression scheme, which produces enormous switching activities during circuit testing, thereby causing high test power consumption for scan design. To solve the above thorny problem, LFSR reseeding-oriented low-power test-compression architecture is developed, and an optimized encoding algorithm is involved in conjunction with any LFSR-reseeding scheme to effectively reduce test storage and power consumption, it includes test cube-based block processing, dividing into hold partition sets and updating hold partition sets. The main contributions is to decrease logic transitions in scan chains and reduce specified bit in test cubes generated via LFSR reseeding. Experimental results demonstrate that the proposed scheme achieves a high test compression efficiency than the existing methods while significantly reduces test power consumption with acceptable area overhead for most Benchmark circuits.     

High‐Performance Low‐Power FFT Cores

Recently, the power consumption of integrated circuits has been attracting increasing attention. Many techniques have been studied to improve the power efficiency of digital signal processing units such as fast Fourier transform (FFT) processors, which are popularly employed in both traditional research fields, such as satellite communications, and thriving consumer electronics, such as wireless communications. This paper presents solutions based on parallel architectures for high throughput and power efficient FFT cores. Different combinations of hybrid low‐power techniques are exploited to reduce power consumption, such as multiplierless units which replace the complex multipliers in FFTs, low‐power commutators based on an advanced interconnection, and parallel‐pipelined architectures. A number of FFT cores are implemented and evaluated for their power/area performance. The results show that up to 38% and 55% power savings can be achieved by the proposed pipelined FFTs and parallel‐pipelined FFTs respectively, compared to the conventional pipelined FFT processor architectures.     

High-Voltage Analog System for a Mobile NAND Flash

High-voltage analog circuits, including a novel high-voltage regulation scheme, are presented with emphasis on low supply voltage, low power consumption, low area overhead, and low noise, which are key design metrics for implementing NAND Flash memory in a mobile handset. Regulated high voltage generation at low supply voltage is achieved with optimized oscillator, high-voltage charge pump, and voltage regulator circuits. We developed a design methodology for a high-voltage charge pump to minimize silicon area, noise, and power consumption of the circuit without degrading the high-voltage output drive capability. Novel circuit techniques are proposed for low supply voltage operation. Both the oscillator and the regulator circuits achieve 1.5 V operation, while the regulator includes a ripple suppression circuit that is simple and robust. Through the paper, theoretical analysis of the proposed circuits is provided along with Spice simulations. A mobile NAND Flash device is realized with an advanced 63 nm technology to verify the operation of the proposed circuits. Extensive measurements show agreement with the results predicted by both analysis and simulation.     

（英）亚毫米波波段波束功率合成方法

对于亚毫米波或太赫兹系统而言,关键问题是功率源的输出功率非常小。 功率合成技术是增加输出功率的有效方法。 然而,在微波和毫米波段中使用的常规功率合成方法（例如电路级合成或波导内空间合成）在亚毫米波波段因损耗高及难以加工等因素而受到制约。 本文提出了一种基于准光学技术的波束功率合成方法。 它具有损耗低,合成效率高,相对容易制造的优点。本文给出了分析,仿真和实验结果,并得到高的输出合成效率。     

大功率数码管驱动电路的优化设计

对大功率数码管（LED）的功耗进行了分析和计算,指出大功率LED不能简单地用七段译码器进行驱动,而必须进行专门设计。以5英寸数码管为例,对其译码驱动电路进行了对比研究,指出在各种驱动电路中,基于数字芯片MC1413的驱动电路是最优设计。设计了实验电路,实验结果验证了理论分析的正确性和所提出方法的可行性。