线性同余交织器的FPGA实现

首先介绍了线性同余交织器的基本原理,然后讨论了其FPGA实现方法.在Quartus Ⅱ软件平台下,利用FPGA器件提供的嵌入式双端口存储器资源,运用VHDL语言进行模块设计,最后实现了线性同余交织器.     

一种用于交织多址系统中的低复杂度的交织方法

针对传统交织多址（IDMA）系统中的交织器问题,提出了一种低复杂度的二维交织方法。该方法基于二维扩频的思想,分别在时域和频域对数据进行交织处理。同时,该方法对所有用户按照时域扩频码进行分组,用户组间采用不同的时域交织器,用户组内采用不同的频域交织器。仿真结果表明,该方法不但可以降低交织器的数量和长度,还可以降低IFFT／FFT操作和频域检测的复杂度。     

一种适合于并行译码的Turbo交织器的设计

高数据率的通信系统要求有高吞吐量的译码器,而并行译码是高吞吐量的译码器的一种有效实现方法。对于采用并行译码的Turbo码,交织器的设计是决定其性能和译码器吞吐量的关键因素。本文在A.Giuliett提出的没有读写冲突的并行交织器的设计原则基础上,给出了一种新型的交织器设计方法。该方法在保证Turbo优越性能的前提下,使得高并行度的译码成为可能。译码性能的仿真结果验证了设计方案的良好译码性能,通过FPGA的硬件实现验证了译码器吞吐量的极大提高。该设计方案可用于Beyond3G系统。     

利用FPGA技术实现数字通信中的交织器和解交织器

介绍用FPGA实现数字通信中的交、解交织器的一种比较通用的方案,详细说明了设计中的一些问题及解决办法.还介绍了一种实现FPGA中信号延时的方法.     

伪随机交织器设计的改进

文章在给出Ｔｕｒｂｏ码系统中交织器设计要求的基础上分析了伪随机交织器的工作原理,并针地其存在的缺点,通过对其随机数的产生加入一定的约束条件,得到一种改进形式的我织器,通过理论分析和数值仿真验 这种改进是有效的。同时给出了降低交织器复杂性的方法。     

Turbo码快速交织算法的性能仿真及其FPGA实现

针对目前交织器存在的时延大的缺陷,设计了一种基于短时延伪随机序列的Turbo码快速交织算法,给出了基于FPGA的硬件实现方案,在时延和性能之间取得较好的折衷。仿真结果表明,该交织算法在不增加Turbo码编译码复杂度的情况下,一次迭代过程交织模块即能减少20%的时间延迟。     

基于ARM和FPGA的全彩独立视频LED系统

提出一种基于ARM FPGA架构的独立视频源方案.系统以ARM9实现通信接口、视频播放等功能,以FPGA实现逐点校正、数据分发等功能,将320行的数据分为3组发送到由6个LED控制器组成的控制器阵列上.LED控制器主要由FPGA实现,完成数据接收、Gamma校正和交织以及LED扫描控制等功能.系统接口丰富、结构灵活、功能强,可以实现全彩色超大屏(三基色各12位灰度级,320×240像素,像素还可根据数据源扩展)的功能.此外,逐点校正功能可以极大地降低LED屏的成本.     

TURBO码实时交织器的FPGA实现

介绍交织技术在Turbo码中的作用及原理,按照螺旋交织器设计的要求,提出了一种交织器电路的设计方案。根据此设计思路得出交织器系统框图,用硬件描述语言进行编程设计了交织器的电路,详细说明了设计内容,并给出了仿真结果。     

一种改进的基于FPGA的32位对数变换器的设计与实现

对数变换器是对数乘法器的重要组成部分,它们以精度换取更快的速度.设计并实现了一种基于FPGA的32位二进制对数变换器,主要由先导"1"检测电路、移位逻辑和误差校正电路组成,通过有效的误差校正算法提高了计算精度;给出了一种新的4位、16位和32位的基于FPGA的并行先导"1"检测电路PLOD,在保持低延时的同时,减小了先导"1"检测电路的功耗和面积;改进了现有的6-域校正算法,在提高精度的同时保持了硬件电路的规整性,降低了系统复杂度及面积和功耗开销;分两站流水实现校正操作,提高了系统的吞吐率;改进后的校正电路将对数操作的最大误差由30%降低到20%,区域1的平均误差大幅度降低.     

一种新型的长度可变的S-随机交织器的设计*

为了优化Turbo码编码系统中的存储,提出了一种新型的长度可变的S-随机交织器的设计方法,此方法在每次增加交织器长度的迭代中,选择出有助于增加交织器扩展特性的元素及其插入位置,此来获得高扩展特性的交织器。本算法的优点是只需存储一张长度小的交织表,即可以获得任意长度的S-随机交织器,而且时间复杂度低。通过仿真得出,该方法设计的交织器的性能并不比普通的S-随机交织器差。     

Reconfigurable address generator for multi-standard interleaver

This paper presents low-complex and novel techniques for designing reconfigurable architectures for multi-standard address generator and interleaver. The emphasis of this work is on hardware re-use, but it also focuses on optimizing the hardware to support multiple standards. A low-cost reconfigurable architecture for address generator and interleaver is proposed which operates in WLAN (802.11a/b/g and 802.11n), WiMAX (802.16e) and 3GPP LTE standards. A simple algorithm and a reconfigurable architecture that eliminates the computationally intricate mod function for LTE, and floor as well as mod function for WLAN/WiMAX, are proposed to reduce the hardware cost as well as implementation complexity. Novel architectures are also proposed to select the increment values for 16-QAM and 64-QAM schemes. A unique configurable subtracting sub-block for each modulation scheme is also presented. Software simulation is carried out to authenticate the functionality of the algorithm. The proposed reconfigurable architectures are realized on FPGA and tested on board. Synthesis results on Spartan-3 FPGA display 66% reduction in FPGA resource utilization and 74% increase in operating frequency compared to the cited address generators. Implementation results on Kintex UltraScale FPGA display a reduction of 34% in resource utilization and 20% in total on-chip power compared to the cited interleavers. This design is also implemented using 45 nm CMOS standard cell technology, and ASIC synthesis results of the reconfigurable address generator exhibit 76.4% improvement in data rate and 52.23% decrease in latency compared to the state-of-the-art address generators. The proposed multimode interleaver also exhibit 60.28% reduction in hardware complexity.     

基于混沌交织的比特交织编码调制及迭代译码系统性能分析

比特交织编码调制及迭代译码(BICM-ID)是适合下一代移动通信系统的一种高效数据传输方式.交织器的设计是影响BICM-ID系统卓越性能的一个关键因素.为了进一步提高BICM-ID系统性能,本文研究了混沌理论在交织器设计中的应用,提出一种新的混沌交织算法,与伪随机交织器相比该方案具有更低的系统时延和更高的传输效率.加性...     

基于累积频数统计的FPGA互连资源时序库

为提高现场可编程门阵列(FPGA)静态时序分析模块的仿真精度,提出一种累积频数仿真输入方法,基于此建立FPGA互连资源时序库,采用统计分析的方法对跳变时间进行累积频数分析。实验结果表明,该方法创建的互连资源时序库能够有效减小线性误差,提高仿真精度,并且与传统的均匀仿真输入方法相比,其仿真误差降至8.23%。     

滑动DCT-LMS自适应算法研究与FPGA实现

研究一种改进的低复杂度复数滑动离散余弦变换(DCT)最小均方(LMS)自适应算法,并设计该算法的FPGA实现结构。在常规LMS算法的输入端前添加改进的滑动DCT,降低输入信号之间的关联性,提高自适应算法收敛速度。改进的滑动DCT算法针对硬件实现进行了优化,提高其在硬件实现中稳定性和精度。给出算法在FPGA实现框图、结果和Matlab仿真结果的对比,以及算法在FPGA中的资源使用。算法已经在实际工程中应用,效果远优于常规LMS自适应算法。     

基于软启动技术的车身控制器设计与应用

针对大功率感性车身电器启停期间的瞬间电流过大的问题,建立一种基于软启动技术的车身控制器。该控制器充分利用单片机(MCU)的控制资源和大规模可编程逻辑门阵列(FPGA)的可扩展优势,实现了对多路开关量信号的快速采样和脉冲宽度调试信号(PWM)信号的输出。在控制软件设计方面,采用结构化模块设计方法,有效地完成了车身控制器的功能和要求。测试结果表明,该系统有效地改善了整车电磁干扰(EMI)并实现了对大功率感性负载软启动,减少了负载的瞬间启动电流的40%以上,同时完成了无人驾驶电动车的车身控制所需的功能。     

基于现场可编程门阵列的新型可编程逻辑控制器在线调试技术

针对基于现场可编程门阵列(FPGA)的新型可编程逻辑控制器(FPGA based PLC)的在线监控问题,提出了泛化的基于FPGA技术对嵌入式片上系统(SoC)进行在线监控的方法。该方法设计了一个FPGA片上通信系统,系统内部固化基于UART的ModBus通信协议栈,通过串口与计算机上位机进行通信;采用双口RAM(DRAM)作为与监控对象间共享的数据缓存区,通过中断机制实现缓存数据的同步交换。性能分析结果表明,该方法将SoC处理监控通信的时间百分比降低至0.002%,确保了监控数据传送的实时性,且使SoC能够获得更佳控制性能。在Altera的cycloneⅡ系列芯片开发板上验证了方案的可行性。     

Generating synthetic benchmark circuits for accelerated life testing of field programmable gate arrays using genetic algorithm and particle swarm optimization

Accelerated life testing (ALT) of a field programmable gate array (FPGA) requires it to be configured with a circuit that satisfies multiple criteria. Hand-crafting such a circuit is a herculean task as many components of the criteria are orthogonal to each other demanding a complex multivariate optimization. This paper presents an evolutionary algorithm aided by particle swarm optimization methodology to generate synthetic benchmark circuits (SBC) that can be used for ALT of FPGAs. The proposed algorithm was used to generate a SBC for ALT of a commercial FPGA. The generated SBC when compared with a hand-crafted one, demonstrated to be more suitable for ALT, measured in terms of meeting the multiple criteria. The SBC generated by the proposed technique utilizes 8.37% more resources; operates at a maximum frequency which is 40% higher; and has 7.75% higher switching activity than the hand-crafted one reported in the literature. The hand-crafted circuit is very specific to the particular device of that family of FPGAs, whereas the proposed algorithm is device-independent. In addition, it took several man months to hand-craft the SBC, whereas the proposed algorithm took less than half-a-day.     

基于XC7V690T的在轨抗单粒子翻转系统设计

针对核心工业级SRAM型FPGA芯片XC7V690T抗辐照能力较弱、在轨运行期间存在较高单粒子翻转风险的问题,为了提高XC7V690T在轨抗单粒子翻转的能力及配置文件注数修改的灵活性,设计了一种基于XC7V690T的在轨抗单粒子翻转系统架构。其硬件架构主要由XC7V690T SRAM型FPGA芯片、AX500反熔丝型FPGA芯片以及多片FLASH组成;软件架构主要包括AX500反熔丝型FPGA对XC7V690T进行配置管理及监控管理,对XC7V690T进行在轨重构管理,XC7V690T通过调用内部SEM IP核实现对配置RAM资源的自主监控和维护。在轨实验结果表明,采用工业级SRAM型FPGA芯片XC7V690T的某航天器通信机在轨测试过程中成功进行了SEM纠错,通信机在轨工作正常,通信链路稳定,满足使用要求,表明该系统架构可以有效提升XC7V690T抗单粒子翻转能力,可以为其他SRAM型FPGA抗单粒子翻转设计提供借鉴与参考。     

A parametric-based performance evaluation and design trade-offs for interconnect architectures using FPGAs for networks-on-chip

Network-on-Chip (NoC) interconnect fabrics are categorized according to trade-offs among latency, throughput, speed, and silicon area, and the correctness and performance of these fabrics in Field-Programmable Gate Array (FPGA) applications are assessed through experimentation and simulation. In this paper, we propose a consistent parametric method for evaluating the FPGA performance of three common on-chip interconnect architectures namely, the Mesh, Torus and Fat-tree architectures. We also investigate how NoC architectures are affected by interconnect and routing parameters, and demonstrate their flexibility and performance through FPGA synthesis and testing of 392 different NoC configurations. In this process, we found that the Flit Data Width (FDW) and Flit Buffer Depth (FBD) parameters have the heaviest impact on FPGA resources, and that these parameters, along with the number of Virtual Channels (VCs), significantly affect reassembly buffering and routing and logic requirements at NoC endpoints. Applying our evaluation technique to a detailed and flexible cycle accurate simulation, we drive the three NoC architectures using benign (Nearest Neighbor and Uniform) and adversarial (Tornado and Random Permutation) traffic patterns with different numbers of VCs, producing a set of load–delay curves. The results show that by strategically tuning the router and interconnect parameters, the Fat-tree network produces the best utilization of FPGA resources in terms of silicon area, clock frequency, critical path delays, network cost, saturation throughput, and latency, whereas the Mesh and Torus networks showed comparatively high resource costs and poor performance under adversarial traffic patterns. From our findings it is clear that the Fat-tree network proved to be more efficient in terms of FPGA resource utilization and is compliant with the current Xilinx FPGA devices. This approach will assist engineers and architects in establishing an early decision in the choice of right interconnects and router parameters for large and complex NoCs. We demonstrate that our approach substantially improves performance under a large variety of experimentation and simulation which confirm its suitability for real systems.