一种高速LVDS接收电路的设计

提出了一种内置失效保护功能的高速低压差分信号(Low Voltage Differential Signaling,LVDS)接收电路。该电路不仅解决了传统电路结构在电源电压3 V或更低时不能满足LVDS标准规定的输入共模电压范围内(0.05~2.35 V)稳定工作的问题,而且还可以直接作为LVDS接口电路的输入级使用,节省了外接保护电路。基于SMIC 0.18μm CMOS工艺模型库,用spectre进行仿真,在输入共模电压范围内工作稳定,传输速率达到1 Gbps。     

0.5μm CMOS 622Mb·s-1 LVDS驱动器芯片设计

文中采用0.5μm CMOS工艺设计并实现了LVDS驱动电路,整个电路由单端输入-差分输出转换电路、偏置电路、驱动输出电路和共模反馈电路组成。该电路芯片面积仅为0.47mm×0.35mm,测试结果表明,采用5V电源供电时直流功耗为30mW,输出电压摆幅及输出共模电平都满足TIA/EIA-644-A标准,电路最高工作速率高于622Mb·s~(-1),可以应用于LVDS传输系统。     

基于SOI CMOS工艺的LVDS驱动器设计

基于绝缘体硅(SOI)0.35μm工艺实现了一款满足IEEE 1596.3和ANSI/TIA/EIA-644工业标准的低压差分信号(LVDS)驱动器芯片。全芯片分为预驱动模块、输出驱动模块、共模反馈模块、使能模块和偏置模块。提出了一种具有低输入电容输出驱动模块电路结构,经仿真验证可有效降低LVDS预驱动模块30%的功耗,同时降低29%的信号延时。芯片利用共模反馈机制控制输出信号的共模电平范围,通过环路补偿保证共模反馈电路的环路稳定性。芯片使用3.3 V供电电压,经Spice仿真并流片测试,输出信号共模电平1.23 V,差分输出电压347 mV,在400 Mbit/s数据传输速率下单路动态功耗为22 mW。     

一个1.12Gb/s 11.3mW LVDS发射器设计

这篇文章提出了基于0.18μm混合信号CMOS工艺,工作在1.8V电源电压下的1.12Gb/s 11.3mW的发射器。该发射器采用了LVDS技术实现了高速传输,输出共模为1.2V。MUX和LVDS驱动电路对于发射器实现高速数据传输而言是很重要的。这篇文章提出了一个高能效的单级14:1 MUX和一个可调LVDS驱动电路,该驱动电路能够驱动不同的负载而仅增加很少的功耗。该发射器的芯片面积为970μm×560μm,实现了低功耗和可调驱动能力。     

高速LVDS收发芯片的设计

本文设计了一种新型低功耗LVDS（Low Voltage Differential Signaling）收发电路。对比于传统的发射电路,本次设计片内集成了共模反馈控制,同时为了提高该电路的工作速度,还设计了一个电流补偿电路来改善输出的时延特性,使得其最高工作速率能达到622Mb/s;而在接收电路方面,该设计解决了传统LVDS接收电路在共模信号输入范围大时性能不能满足要求的问题。另外,此接收电路还支持失效保护功能。该收发一体芯片已采用华润上华科技有限公司（CSMC)0.5µm CMOS工艺流片。测试结果表明,发送电路的最高工作速率超过622Mb/s,5V电源电压下静态工作电流仅为6mA。接收电路在宽的共模输入电压范围（0.1～2.4V）及低达100mV的差模输入信号条件下均能稳定工作。在400 Mb/s的最高工作频率下,静态工作电流仅为1.2mA。芯片满足TIA/EIA-644-A标准,可以应用于LVDS收发系统。     

应用于红外大面阵数据传输的接口电路设计

红外大面阵(2560×2048)数字读出电路对芯片数据接口有高速、低功耗、强驱动能力的需求。采用0.18■m互补金属氧化物半导体(Complementary Metal Oxide Semiconductor, CMOS)工艺设计了4∶1并串转换电路、电平转换电路以及采用预加重技术的低压差分信号(Low Voltage Differential Signal, LVDS)驱动器电路。并串转换电路采用双沿采样的树形结构降低时钟频率,电平转换电路采用正反馈结构提升速度,LVDS驱动电路采用可编程电流大小的预加重副通路对主通路进行高频分量补偿,以保证驱动能力和提升高速信号的完整性。接口的数据传输速率可达到1 Gbit/s。当负载电容为2 pF时,一个通道的功耗为15.8 mW@1 Gbit/s;当负载电容为8 pF且打开预加重时,一个通道的功耗为19 mW@1Gbit/s,输出电压摆幅为350 mV,输出共模电平为1.21 V,LVDS驱动电路的所有参数均满足标准协议。     

一种高速LVDS驱动电路的设计

介绍了一种采用0.18μm CMOS工艺制作的高速(500MHz)LVDS驱动电路.分析了开关时序和共模反馈对电路的影响,采用开关控制信号整形电路和基于"主-从"结构的共模设置电路,得到适当的开关时序和较好的共模电平设置,使LVDS输出电路具有更小的过冲电压和更稳定的共模电平.该LVDS驱动电路用于1GHz 14位高速D/A转换器芯片.样品电路测试结果表明,输出速率在500MHz时,LVDS驱动电路的指标满足IEEE-1596 reduced range link标准.     

一种高性能CMOS LVDS接收电路的设计

提出了一种符合IEEE Std 1596.3-1996[1]标准,适用于芯片间高速数据传输的低电压差分信号(LVDS)接收电路;有效地解决了传统电路结构在电源电压降至3.3 V或更低以后不能稳定工作在标准规定的整个输入共模电平范围内的问题,电路能在符合标准的0.05~2.35 V输入共模电平范围内稳定工作,传输速率可达1.6 Gb/s,平均功耗1.18 mW。设计基于HJTC(和舰科技)Logic 0.18μm 1.8 V/3.3 V CMOS工艺,使用3.3 V厚栅MOS管和1.8 V薄栅MOS管。     

一种用于平板显示系统的LVDS接口驱动电路的设计

LVDS接口电路已成为平板显示系统信号传输的首选,被广泛应用于数字视频高速传输系统。本文设计了一个LVDS接口驱动电路,该驱动电路采用共模反馈环路使输出LVDS信号的共模电平稳定。在输入信号为800MHz情况下应用1stSilicon0.35μm CMOS混合信号工艺在Cadence Spectre环境下对驱动器电路进行了仿真,结果表明所设计的驱动电路各项技术参数完全符合LVDS标准。     

一种应用于高速数据通信的LVDS接收器设计

提出了一种应用于高速数据通讯的低电压差分信号(LVDS)接收器电路设计,符合IEEEStd.1596.3-1996(LVDS)标准,有效地解决了传统电路在低电源电压下不能满足标准对宽共模范围的要求以及系统的高速低功耗要求。电路采用65nm 1P9M CMOS Logic工艺设计实现,仿真结果表明该接收器电路能在符合标准的0V-2.4V的宽输入共模电平下稳定工作,在电源电压为2.5V的工作条件下,数据传输速率可以达到2Gbps,平均功耗仅为3mW。     

Design of high speed LVDS transceiver ICs

The design of low-power LVDS(low voltage differential signaling) transceiver ICs is presented.The LVDS transmitter integrates a common-mode feedback control on chip,while a specially designed pre-charge circuit is proposed to improve the speed of the circuit,making the highest data rate up to 622 Mb/s.For the LVDS receiver design, the performance degradation issues are solved when handling the large input common mode voltages of the conventional LVDS receivers.In addition,the LVDS receiver also supports ...     

LVDS I/O interface for Gb/s-per-pin operation in 0.35-μm CMOS

This paper presents the design and the implementation of input/output (I/O) interface circuits for Gb/s-per-pin operation, fully compatible with low-voltage differential signaling (LVDS) standard. Due to the differential transmission technique and the low voltage swing, LVDS allows high transmission speeds and low power consumption at the same time. In the proposed transmitter, the required tolerance on the dc output levels was achieved over process, temperature, and supply voltage variations with neither external components nor trimming procedures, by means of a closed-loop control circuit and an internal voltage reference. The proposed receiver implements a dual-gain-stage folded-cascode architecture which allows a 1.2-Gb/s transmission speed with the minimum common-mode and differential voltage at the input. The circuits were implemented in a 3.3-V 0.35-μm CMOS technology in a couple of test chips. Transmission operations up to 1.2 Gb/s with random data patterns and up to 2 Gb/s in asynchronous mode were demonstrated. The transmitter and receiver pad cells exhibit a power consumption of 43 and 33 mW, respectively     

一个0.18μm高速低功耗的发送和接收电路

提出了一种高速低功耗的低压差分接口电路,它可以应用于CPU,LCD,FPGA等需要高速接口的芯片中.在发送端,一个稳定的参考电压和共模反馈电路被应用于低压差分电路中,它使得发送端能够克服电源、温度以及工艺引起的波形变化.在接收端采用了轨到轨的放大器结构,它町以工作到1.6Gb/s.芯片设计加工采用的是0.18μm CMOS工艺,芯片测试结果表明,整个发送接收端数据传输速率可以达到1.6Gb/s,同时发送和接收端的功耗分别是35和6mW.     

基于65nm工艺的3Gb/s多通道收发器*

采用 65nm工艺,实现了一款16位并行收发器的IP核,它在5pf的负载及HBM 2000V的ESD保护下,其速率为3Gb/s。为了减小延时,均衡器、时钟数据恢复电路、CRC检测电路以及8b/10b编码电路在设计中均没有使用,所以整个电路在没有电缆的情况的延时为7ns。根据收发器在工艺、电压和温度下的鲁棒特性,在设计中采用了自动频率校正的锁相环电路,低偏移的差分时钟树及具有共模反馈的稳定电流模驱动器电路。该收发器在3Gbps速度下误码率小于10^-15,可以在不同的工艺角和极端温度下正常工作,并且能够容忍20%电压的偏差变化,在100nm下的具有低延时和高稳定性的高性能处理器中能够得到很好的应用。     

一个0.18μm高速低功耗的发送和接收电路

提出了一种高速低功耗的低压差分接口电路,它可以应用于CPU,LCD,FPGA等需要高速接口的芯片中.在发送端,一个稳定的参考电压和共模反馈电路被应用于低压差分电路中,它使得发送端能够克服电源、温度以及工艺引起的波形变化.在接收端采用了轨到轨的放大器结构,它町以工作到1.6Gb/s.芯片设计加工采用的是0.18μm CMOS工艺,芯片测试结果表明,整个发送接收端数据传输速率可以达到1.6Gb/s,同时发送和接收端的功耗分别是35和6mW.     

A 6 Gbps/pin Low‐Power Half‐Duplex Active Cross‐Coupled LVDS Transceiver with Switched Termination

A novel linear switched termination active cross‐coupled low‐voltage differential signaling (LVDS) transceiver operating at 1.5 GHz clock frequency is presented. On the transmitter side, an active cross‐coupled linear output driver and a switched termination scheme are applied to achieve high speed with low current. On the receiver side, a shared preamplifier scheme is employed to reduce power consumption. The proposed LVDS transceiver implemented in an 80 nm CMOS process is successfully demonstrated to provide a data rate of 6 Gbps/pin, an output data window of 147 ps peak‐to‐peak, and a data swing of 196 mV. The power consumption is measured to be 4.2 mW/pin at 1.2 V.     

High-bit-rate, high-input-sensitivity decision circuit using Sibipolar technology

We have designed and fabricated a high-bit-rate, high-input-sensitivity decision circuit for future optical communication systems using an advanced super self-aligned Si bipolar process technology (SST-1C). The SST-1C transistors are fabricated by 0.5-μm photolithography. The peak cut-off frequency of a typical transistor is 31 GHz at a collector-emitter voltage of 3 V. The circuit design involves the optimization of individual transistor sizes to boost the speed and the adoption of a wide-band preamplifier to enhance input sensitivity. The circuit operates at up to 15 Gb/s with an input sensitivity of 40 mV_p-p. An extremely high input sensitivity of 15 mV_p-p and a wide phase margin of 260° at 10 Gb/s are achieved     

用于LVDS传输系统的高速对称电缆的研制

目前LVDS(低电压差分信号)传输模式在高速数字传输领域得到了广泛应用。介绍了一种用于传输高速LVDS的对称电缆的研制,通过合理的结构及材料设计和有效的工艺措施,降低了电缆的衰减,使电缆可在2Gb/s的传输速率下进行数据传输。该电缆具有外径小、重量轻、耐高温等特点,尤其适用于航空航天领域。     

2.5Gb/Scmos光接收机跨阻前置放大器

给出了一种利用0.35μm CMOS工艺实现的2.5Gb/s跨阻前置放大器。此跨阻放大器的增益为59 dB*Ω,3dB带宽为2GHz,2GHz处的等效输入电流噪声为0.8×10-22 A2/Hz。在标准的5V电源电压下,功耗为250mW。PCML单端输出信号电压摆幅为200mVp-p。整个芯片面积为1.0mm×1.1mm。     

Optical preamplifier using optical modulation of amplified spontaneous emission in saturated semiconductor optical amplifier

This paper demonstrates a novel optical preamplifier using optical modulation of amplified spontaneous emission (ASE) emitted from a saturated semiconductor optical amplifier (SOA). Requirements on optical alignments and antireflection coating for SOAs can be relaxed and the elimination of an optical filter gives us a large tolerance of an input light wavelength in the proposed optical preamplifier. A small-signal gain of a fabricated preamplifier was over 13.5 dB for an input power of below -20 dBm. An optical gain bandwidth was over 60 nm. We measured the small-signal response of the optically modulated ASE. The 3 dB bandwidths at SOA bias currents of 200, 300, and 400 mA were 5.8, 12.6, and 16.5 GHz, respectively. We also investigated improvements in receiver sensitivities with the proposed optical preamplifier. Our calculation shows a possibility of 10 dB improvement in receiver sensitivities by using the optical preamplifier at 10 Gb/s. The measured receiver sensitivity was -22.7 dBm at 10 Gb/s with the optical preamplifier, which is corresponding to an improvement of 2.5 dB in the receiver sensitivity. Further improvements of the receiver sensitivity can be expected by optimizing the structure of SOAs for saturating ASE.