一种新颖的对称式,双比特位,分栅闪存结构单元

A fully self-aligned symmetrical split-gate cell structure for 2-bit per cell flash memory with a very competitive bit size is presented. One common select gate is located between two floating gates and a pair of source/drain junctions are shared by the 2 bits. The fabrication method utilized here to create a self-aligned structure is to form a spacer against the prior layer without any additional mask. Although the cell consists of three channels in a series, the attributes from conventional split gate flash are still preserved with appropriate bias conditions. Program and erase operation is performed by using a source side injection （SSI） and a poly-to-poly tunneling mechanism respectively.     

A low-voltage sense amplifier for high-performance embedded flash memory

This paper presents a sense amplifier scheme for low-voltage embedded flash(eFlash)memory applications.The topology of the sense amplifier is based on current mode comparison.Moreover,an offset-voltage elimination technique is employed to improve the sensing performance under a small memory cell current.The proposed sense amplifier is designed based on a GSMC 130 nm eFlash process,and the sense time is 0.43 ns at 1.5 V,corresponding to a46% improvement over the conventional technologies.     

一种适应于高性能嵌入式闪存的低压灵敏放大器

本文提出了一种适应于高性能嵌入式闪存的低压灵敏放大器,通过采用电流比较技术和自动消失调技术,该灵敏放大器在低电源电压下获得了很好的性能,改善了低电流阈值窗口存储器的读取速度。基于上海宏力半导体制造公司130nm的嵌入式闪存工艺,该灵敏放大器的感应时间在1.5V的电源电压下达到了0.43ns,其感应速度比传统的灵敏放大器提高了46%     

A high efficiency all-PMOS charge pump for 3D NAND flash memory

For 3D vertical NAND flash memory, the charge pump output load is much larger than that of the planar NAND, resulting in the performance degradation of the conventional Dickson charge pump. Therefore, a novel all PMOS charge pump with high voltage boosting efficiency, large driving capability and high power efficiency for 3D V-NAND has been proposed. In this circuit, the Pelliconi structure is used to enhance the driving capability, two auxiliary substrate bias PMOS transistors are added to mitigate the body effect, and the degradation of the output voltage and boost efficiency caused by the threshold voltage drop is eliminated by dynamic gate control structure. Simulated results show that the proposed charge pump circuit can achieve the maximum boost efficiency of 86% and power efficiency of 50%. The output voltage of the proposed 9 stages charge pump can exceed 2 V under 2 MHz clock frequency in 2X nm 3D V-NAND technology. Our results provide guidance for the peripheral circuit design of high density 3D V-NAND integration.     

一种LTPS-TFT AMOLED像素电路的理论研究

本文对一种LTPS-TFT AMOLED电压型阈值电压(V_(th))补偿像素电路进行了理论研究,分析了影响V_(th)补偿效果的主要因素。电路的补偿效果主要由驱动TFTV_(th)的获取精度和随后的保持精度决定。在V_(th)获取过程中,相关误差主要由驱动TFT转移特性电流对存储电容充电的充电率不足产生;在显示信号与V_(th)叠加过程中,与V_(th)保持节点连接的电容增量等因素会造成V_(th)保持精度的损失。根据分析的结果,本文解释了高分辨率像素电路补偿效果下降的原因。     

Temperature self-adaptive program algorithm on 65 nm MLC NOR flash memory

tive programming to 1.4 MByte/s with the proposed method at room temperature. This represents a 30% improvement and is 70 times faster than the program throughput in Ref. [1].     

65nM MLC NOR型闪存温度自适应编程算法

本文根据沟道热电子(CHE)的温度特性提出了提高MLC NOR型闪存编程吞吐率的方案。用Lucky 电子模型对CHE 编程电流 与温度的关系进行了分析,提出了温度自适应编程算法,即根据片上的温度来改变纵向电场和 提高编程吞吐率。实验测得,室温下编程吞吐率从原来1.1Mbyte/S提高到采用温度自适应算法后1.4Mbyte/S,编程吞吐率有了近30%的提高,相比文献[5],本文编程吞吐率有了70倍的提高。     

一种新型大驱动、低功耗和高精度的电荷泵电路

提出一种适用于NOR结构快闪存储器应用的,具有大驱动能力、低功耗和高精度特性的电荷泵系统。它通过对八个子电荷泵的并联来提高电荷泵的驱动能力,并采用电容分离法来动态地自洽改变每个子电荷泵的驱动能力,仿真结果表明,在擦除模式、一位编程模式和八位编程模式工作下,其瞬态平均电流分别约为2.5mA、4 mA和12 mA,电荷泵的输出高压精度可达±2.3%以下,达到了节省功耗和提高输出高压精度的目的。     

A novel charge pump drive circuit for power MOSFETs

Novel improved power metal oxide semiconductor field effect transistor (MOSFET) drive circuits are introduced. An anti-deadlock block is used in the P-channel power MOSFET drive circuit to avoid deadlocks and improve the transient response. An additional charging path is added to the N-channel power MOSFET drive circuit to enhance its drive capability and improve the transient response. The entire circuit is designed in a 0.6 μm BCD process and simulated with Cadence Spectre. Compared with traditional power MOSFET drive circuits, the simulation results show that improved P-channel power MOSFET drive circuit makes the rise time reduced from 60 to 14 ns, the fall time reduced from 240 to 30 ns, and its power dissipation reduced from 2 to 1 mW, while the improved N-channel power MOSFET drive circuit makes the rise time reduced from 360 to 27 ns and its power dissipation reduced from 1.1 to 0.8 mW.     

一款新型电荷泵功率管驱动电路

提出了一款新型功率管驱动电路。P沟道功率管驱动电路加入了防死锁模块防止了死锁的出现,提高了瞬态响应;N沟道功率管驱动电路加入了附加的充电支路,提高了驱动能力和瞬态响应。整个电路基于0.6μm BCD工艺,在Cadence Spectre下仿真。和传统的功率管驱动电路相比,新的P沟道功率管驱动电路的上升时间由60ns减少到14ns,下降时间由240ns减少到30ns,并且功耗从2mW减少到1mW;新的N沟道功率管驱动电路的上升时间由360ns减少到27ns,功耗从1.1mW减少到0.8mW。     

A low-voltage sense amplifier with two-stage operational amplifier clamping for flash memory

A low-voltage sense amplifier with reference current generator utilizing two-stage operational amplifier clamp structure for flash memory is presented in this paper, capable of operating with minimum supply voltage at 1 V. A new reference current generation circuit composed of a reference cell and a two-stage operational amplifier clamping the drain pole of the reference cell is used to generate the reference current, which avoids the threshold limitation caused by current mirror transistor in the traditional sense amplifier. A novel reference voltage generation circuit using dummy bit-line structure without pull-down current is also adopted, which not only improves the sense window enhancing read precision but also saves power consumption. The sense amplifier was implemented in a flash realized in 90 nm flash technology. Experimental results show the access time is 14.7 ns with power supply of 1.2 V and slow corner at 125 ℃.     

一种适应于flash memory的超低压和高速的感应放大器设计

A new low-voltage and high-speed sense amplifier is presented, based on a very simple direct current-mode comparison. It adopts low-voltage reference current extraction and a dynamic output method to realize its performance indicators such as low voltage, low power and high precision. The proposed amplifier can sense a 0.5 μ A current gap and work with a lowest voltage of 1 V. In addition, the current power of a single amplifier is optimized by 15%.     

A new low-voltage and high-speed sense amplifier for flash memory

A new low-voltage and high-speed sense amplifier is presented,based on a very simple direct current-mode comparison.It adopts low-voltage reference current extraction and a dynamic output method to realize its performance indicators such as low voltage,low power and high precision.The proposed amplifier can sense a 0.5μA current gap and work with a lowest voltage of 1V.In addition,the current power of a single amplifier is optimized by 15%.     

A novel high voltage start up circuit for an integrated switched mode power supply

A novel high voltage start up circuit for providing an initial bias voltage to an integrated switched mode power supply(SMPS) is presented.An enhanced mode VDMOS transistor,the gate of which is biased by a floating pisland, is used to provide start up current and sustain high voltage.An NMOS transistor having a high source to ground breakdown voltage is included to extend the bias voltage range to the SMPS.Simulation results indicate that the high voltage start up circuit can start and restart as designe...     

一种新型的用于开关电源的高压启动电路

文章提出了一种给集成开关电源提供初始电压的高压启动电路。一个增强型的VDMOS晶体管被用来提供启动电流和承受高压。VDMOS的栅被一个浮空P岛偏置。启动电路用了一个具有高的源对地击穿电压的NMOS来获得大的偏置电压范围。仿真结果表明高压启动电路能够按照设计正常的启动和重启动。本文提出的结构比起其它方案来更节能,成本更低。     

基于DS3501的APD偏压温度补偿电路设计

介绍了DS3501的工作原理,针对APD偏置电压需要进行精确温度补偿的要求,设计了一种高精度、宽动态范围的APD偏压自动补偿电路。经实验测试,APD偏压相对误差小于0.25%。将该补偿电路应用于荧光法溶解氧测量系统中,显著提高了系统测量精度,测量结果相对误差小于1%。     

一种用于3D NAND存储器的高压生成电路

设计了一种应用于3D NAND 存储器的高压生成电路,包括振荡器、时钟生成电路、新型电荷泵及反馈环路。与传统的电荷泵相比,新型电荷泵消除了阈值电压损失与衬底偏置效应,提高了升压效率。通过控制时钟的电压幅度来调节输出电压,减小了输出电压纹波。电路在0.32 μm CMOS工艺模型下进行了仿真验证。结果表明,在3.3 V工作电压下,该电路稳定输出15 V的高压,上升时间为3.4 μs,纹波大小为82 mV,最大升压效率可达到76%。该高压生成电路在各项性能指标之间取得了平衡,其突出的综合性能能满足3D NAND存储器的工作需求。     

A novel CMOS charge-pump circuit with current mode control 110 mA at 2.7 V for telecommunication systems

This paper presents a novel organization of switch capacitor charge pump circuits based on voltage doubler structures. Each voltage doubler takes a dc input and outputs a doubled dc voltage. By cascading voltage doublers the output voltage increases up to 2 times. A two-phase voltage doubler and a multiphase voltage doubler structures are discussed and design considerations are presented. A simulator working in the Q-V realm was used for simplified circuit level simulation. In order to evaluate the power delivered by a charge pump, a resistive load is attached to the output of the charge pump and an equivalent capacitance is evaluated. To avoid the short circuit during switching, a clock pairs generator is used to achieve multi-phase non-overlapping clock pairs. This paper also identifies optimum loading conditions for different configurations of the charge pumps. The proposed charge-pump circuit is designed and simulated by spice with TSMC 0.35-μm CMOS technology and operates with a 2.7 V to 3.6 V supply voltage. It has an area of 0.4 mm2; it was designed with a frequency regulation of 1 MHz and internal current mode to reduce power consumption.     

A novel CMOS charge-pump circuit with current mode control 110 mA at 2.7 V for telecommunication systems

This paper presents a novel organization of switch capacitor charge pump circuits based on voltage doubler structures. Each voltage doubler takes a DC input and outputs a doubled DC voltage. By cascading voltage doublers the output voltage increases up to 2 times. A two-phase voltage doubler and a multiphase voltage doubler structures are discussed and design considerations are presented. A simulator working in the Q-V realm was used for simplified circuit level simulation. In order to evaluate the power delivered by a charge pump, a resistive load is attached to the output of the charge pump and an equivalent capacitance is evaluated. To avoid the short circuit during switching, a clock pair generator is used to achieve multi-phase non-overlapping clock pairs. This paper also identifies optimum loading conditions for different configurations of the charge pumps. The proposed charge-pump circuit is designed and simulated by SPICE with TSMC 0.35-μm CMOS technology and operates with a 2.7 to 3.6 V supply voltage. It has an area of 0.4 mm2; it was designed with a frequency regulation of 1 MHz and internal current mode to reduce power consumption.     

一种支持OLED亮度补偿的电流型PWM像素驱动电路

OLED(organic light-emitting diode,OLED)微显示器长时间工作在高对比度、高亮度的状态下,OLED像素衰退不一致,发光亮度衰退也不一致,会产生残影现象。因此,提出了一种改进的电流型PWM像素驱动电路,保持了对OLED像素衰退补偿效果,同时可以读出OLED阳极电压,计算得到OLED衰退信息,以便于对OLED亮度衰退进行有效的补偿。文章中分析了改进的电流型PWM驱动电路结构,及其对OLED衰退补偿和亮度补偿的原理。通过模拟仿真,得到几个影响OLED衰退补偿效果的关键参数。当OLED像素衰退电阻R_oled小于40 MΩ时,该电流型PWM驱动电路电流衰退度与传统2T1C驱动电路相比,只为其衰退度的50%。