Development of 17 kV 4H-SiC PiN diode

The design, fabrication, and electrical characteristics of a 4H-SiC PiN diode with breakdown voltage higher than 17 kV are presented. The three-zone JTE has been used in the fabrication. Numerical simulations have been performed to optimize the parameters of the edge termination technique. The epilayer properties of the N-type are 175 μm with a doping of 2×10¹⁴cm^-3. With the three-zone JTE, a typical breakdown voltage of 17 kV has been achieved.     

基于一种可靠非均匀场限环终端结构的1.4kV 4H型碳化硅PiN二极管

This paper presents the design and fabrication of an effective, robust and process-tolerant floating guard ring termination on high voltage 4H-SiC PiN diodes. Different design factors were studied by numerical simulations and evaluated by device fabrication and measurement. The device fabrication was based on a 12 μm thick drift layer with an N-type doping concentration of 8 × 10^15 cm^-3. P^＋ regions in the termination structure and anode layer were formed by multiple aluminum implantations. The fabricated devices present a highest breakdown voltage of 1.4 kV, which is higher than the simulated value. For the fabricated 15 diodes in one chip, all of them exceeded the breakdown voltage of 1 kV and six of them reached the desired breakdown value of 1.2 kV.     

Unified Breakdown Model of SOI RESURF Device with Uniform/Step/Linear Doping Profile

A unified breakdown model of SOI RESURF device with uniform,step，or linear drift region doping profile is firstly proposed.By the model,the electric field distribution and breakdown voltage are researched in detail for the step numbers from 0 to infinity.The critic electric field as the function of the geometry parameters and doping profile is derived.For the thick film device,linear doping profile can be replaced by a single or two steps doping profile in the drift region due to a considerable uniformly lateral electric field,almost ideal breakdown voltage,and simplified design and fabrication.The availability of the proposed model is verified by the good accordance among the analytical results,numerical simulations,and reported experiments.     

Characterization of vanadyl phthalocyanine based surface-type capacitive humidity sensors

This study presents the fabrication and characterization of a novel surface-type capacitive humidity sensors using Vanadyl Phthalocyanine (VOPc) as an active material. The devices comprising three different thicknesses have been fabricated using thermal evaporator. Thin film of VOPc is deposited on thoroughly cleaned glass substrates with pre-patterned Ag electrodes. The capacitive effect of the samples under humidity has been investigated. Comparison of the samples with different thicknesses reveals the fact that the device with lesser thickness seems more sensitive towards humidity. The humidity dependent capacitance properties of the sensor make it beneficial for use in commercial hygrometers.     

Study of hybrid orientation structure wafer

Two types of 5μm thick hybrid orientation structure wafers,which were integrated by（110）or（100） orientation silicon wafers as the substrate,have been investigated for 15-40 V voltage ICs and MEMS sensor applications.They have been obtained mainly by SOI wafer bonding and a non-selective epitaxy technique,and have been presented in China for the first time.The thickness of BOX SiO₂ buried in wafer is 220 nm.It has been found that the quality of hybrid orientation structure with（100）wafer substrate is better than that with（110）wafer substrate by"Sirtl defect etching of HOSW".     

InAs/InAsSb Avalanche Photodiode （APD） for applicaions in long-wavelength infrared region

A generic numerical model of a long-wavelength Avalanche Photodiode (APD) based on narrow bandgap semiconductor InAsSb on InAs substrate is reported for the first time. This model has been applied for theoretical characterization of a proposed N InAS/P-InAsSb avalanche photodiode structure for possible application in 2-5 μm wavelength region. The parameters such as gain,excess noise factor and their trade-off with variation of doping concentration and bias voltage have been estimated for the APD taking into account history-dependent theory of avalanche multiplication process. The LWIR APD is expected to find application in optical gas sensor and in future generation of optical communication system.     

Recombination Efficiency and Width in Bilayer Organic Light-emitting Devices

A bilayer model with ohmic anode contact and injection limited cathode contact has been proposed to calculate the recombination efficiency and recombination zone width of the device. The effects of the thickness of hole transport layer and the barriers of organic/organic interface on the combination efficiency and recombination width have been discussed. It is found that： （1） When the electrons are blocked fully and the holes are not blocked significantly at the organic/organic interface, for a given Lh/L, the recombination efficiency increases with increasing the applied voltage, but at a higher applied voltage, the recombination efficiency decreases with increasing Lh/L; （2） The recombination efficiency increases with increasing applied voltage and Hh＇, and when applied voltage and Hh＇ exceed some value, the recombination efficiency appears as a plateau; （3） The recombination width decreases with increasing the applied voltage and Lh/L. This model might explain the relative experiment phenomena.     

InAs/InAsSb Avalanche Photodiode （APD） for applicaions in long-wavelength infrared region

A generic numerical model of a long-wavelength Avalanche Photodiode （APD） based on narrow bandgap semiconductor InAsSb on InAs substrate is reported for the first time. This model has been applied for theoretical characterization of a proposed N^＋ InAS/P-InAsSb avalanche photodiode structure for possible application in 2-5 μm wavelength region. The parameters such as gain, excess noise factor and their trade-off with variation of doping concentration and bias voltage have been estimated for the APD taking into account history-dependent theory of avalanche multiplication process, The LWIR APD is expected to fred application in optical gas sensor and in future generation of optical communication system.     

CMOS图像传感器钳位光敏二极管夹断电压模型研究

A novel analytical model of pinch-off voltage for CMOS image pixels with a pinned photodiode structure is proposed. The derived model takes account of the gradient doping distributions in the N buried layer due to the impurity compensation formed by manufacturing processes; the impurity distribution characteristics of two boundary PN junctions located in the region for particular spectrum response of a pinned photodiode are quantitative analyzed. By solving Poisson＇s equation in vertical barrier regions, the relationships between the pinch-off voltage and the corresponding process parameters such as peak doping concentration, N type width and doping concentration gradient of the N buried layer are established. Test results have shown that the derived model features the variations of the pinch-off voltage versus the process implant conditions more accurately than the traditional model. The research conclusions in this paper provide theoretical evidence for evaluating the pinch-off voltage design.     

Si/SiC-based DD hetero-structure IMPATTs as MM-wave power-source: a generalized large-signal analysis

A full-scale, self-consistent, non-linear, large-signal model of double-drift hetero-structure IMPATT diode with general doping profile is derived. This newly developed model, for the first time, has been used to analyze the large-signal characteristics of hexagonal SiC-based double-drift IMPATT diode. Considering the fabrication feasibility, the authors have studied the large-signal characteristics of Si/SiC-based hetero-structure devices. Under small-voltage modulation (～ 2%, i.e. small-signal conditions) results are in good agreement with calculations done using a linearised small-signal model. The large-signal values of the diode's negative conductance (5 × 10⁶S/m²), susceptance (10.4 × 10⁷ S/m^2}), average breakdown voltage (207.6 V), and power generating efficiency (15%, RF power: 25.0 W at 94 GHz) are obtained as a function of oscillation amplitude (50% of DC breakdown voltage) for a fixed average current density. The large-signal calculations exhibit power and efficiency saturation for large-signal (> 50%) voltage modulation and thereafter decrease gradually with further increasing voltage-modulation. This generalized large-signal formulation is applicable for all types of IMPATT structures with distributed and narrow avalanche zones. The simulator is made more realistic by incorporating the space-charge effects, realistic field and temperature dependent material parameters in Si and SiC. The electric field snap-shots and the large-signal impedance and admittance of the diode with current excitation are expressed in closed loop form. This study will act as a guide for researchers to fabricate a high-power Si/SiC-based IMPATT for possible application in high-power MM-wave communication systems.     

Ranking Potential Reply-Providers in Community Question Answering System

Community Question Answering （CQA） websites have greatly facilitated users＇ lives, with an increasing number of people seeking help and exchanging ideas on the Internet. This newlymerged community features two characteristics： social relations and an ask-reply mechanism. As users＇ behaviours and social statuses play a more important role in CQA services than traditional answer retrieving websites, researchers＇ concerns have shifted from the need to passively find existing answers to actively seeking potential reply providers that may give answers in the near future. We analyse datasets derived from an online CQA system named ＂Quora＂, and observed that compared with traditional question answering services, users tend to contribute replies rather than questions for help in the CQA system. Inspired by the findings, we seek ways to evaluate the users＇ ability to offer prompt and reliable help, taking into account activity, authority and social reputation char- acteristics. We propose a hybrid method that is based on a Question-User network and social network using optimised PageRank algorithm. Experimental results show the efficiency of the proposed method for ranking potential answer-providers.     

一个全差分可编程的多通道神经信号记录芯片

A multi-channel,fully differential programmable chip for neural recording application is presented.The integrated circuit incorporates eight neural recording amplifiers with tunable bandwidth and gain,eight 4thorder Bessel switch capacitor filters,an 8-to-1 analog time-division multiplexer,a fully differential successive approximation register analog-to-digital converter(SAR ADC),and a serial peripheral interface for communication.The neural recording amplifier presents a programmable gain from 53 dB to 68 dB,a tunable low cut-off frequency from 0.1 Hz to 300 Hz,and 3.77 μVrms input-referred noise over a 5 kHz bandwidth.The SAR ADC digitizes signals at maximum sampling rate of 20 kS/s per channel and achieves an ENOB of 7.4.The integrated circuit is designed and fabricated in 0.18-μm CMOS mix-signal process.We successfully performed a multi-channel in-vivo recording experiment from a rat cortex using the neural recording chip.     

A power-efficient 12-bit analog-to-digital converter with a novel constant-resistance CMOS input sampling switch

Apower-efficient 12-bit40-MS/spipelineanalog-to-digitalconverter（ADC）implementedina0.13 μm CMOS technology is presented. A novel CMOS bootstrapping switch, which offers a constant on-resistance over the entire input signal range, is used at the sample-and-hold front-end to enhance the dynamic performance of the pipelined ADC. By implementing with 2.5-bit-per-stage and a simplified amplifier sharing architecture between two successive pipeline stages, a very competitive power consumption and small die area can be achieved. Meanwhile, the substrate-biasing-effect attenuated T-type switches are introduced to reduce the crosstalk between the two op- amp sharing successive stages. Moreover, a two-stage gain boosted recycling folded cascode （RFC） amplifier with hybrid frequency compensation is developed to further reduce the power consumption and maintain the ADC＇s performance simultaneously. The measured results imply that the ADC achieves a spurious-free dynamic range （SFDR） of 75.7 dB and a signal-to-noise-plus-distortion ratio （SNDR） of 62.74 dB with a 4.3 MHz input signal; the SNDR maintains over 58.25 dB for input signals up to 19.3MHz. The measured differential nonlinearity （DNL） and integral nonlinearity （INL） are -0.43 to ＋0.48 LSB and -1.62 to ＋ 1.89 LSB respectively. The prototype ADC consumes 28.4 mW under a 1.2-V nominal power supply and 40 MHz sampling rate, transferring to a figure- of-merit （FOM） of 0.63 pJ per conversion-step.     

Low power high gain gain-controlled LNA and mixer for GNSS receivers Wei Binbin(魏斌斌)1, Jiang Jinguang(江金光)1,2,3*

A low power high gain gain-controlled LNA ＋ mixer for GNSS receivers is reported. The high gain LNA is realized with a current source load. Its gain-controlled ability is achieved using a programmable bias circuit. Taking advantage of the high gain LNA, a high noise figure passive mixer is adopted. With the passive mixer, low power consumption and high voltage gain of the LNA ＋ mixer are achieved. To fully investigate the performance of this circuit, comparisons between a conventional LNA ＋ mixer, a previous low power LNA ＋ mixer, and the proposed LNA ＋ mixer are presented. The circuit is implemented in 0.18 #m mixed-signal CMOS technology. A 3.8 dB noise figure, an overall 45 dB converge gain and a 10 dB controlled gain range of the two stages are measured. The chip occupies 0.24 mm2 and consumes 2 mA current under 1.8 V supply.     

一种应用于GPS接收机的高线性度SiGe HBT低噪声放大器

A high linearity 1.575 GHz SiGe：HBT low noise amplifier （LNA） for global positioning system applications is described. The bipolar cascoded with an MOSFET LNA was fabricated in a commercial 0.18 μm SiGe BiCMOS process, A resistor bias feed circuit with a feedback resistor was designed for the LNA input transistor to improve its intermodulation and compression performance. The packaged chip tested on board has displayed a noise figure of 1. I 1 dB, a power gain of 18 dB, an output 1 dB compression point of ＋7.8 dBm and an input third-order intercept point of ＋1.8 dBm. The chip occupies a 500 × 560μm^2 area and consumes 3.6 mA from a 2.85 V power supply.     

一种应用于GNSS接收机的低噪声和低杂散频率综合器

A low phase noise and low spur phase locked loop （PLL） frequency synthesizer for use in global navigation satellite system （GNSS） receivers is proposed. To get a low spur, the symmetrical structure of the phase frequency detector （PFD） produces four control signals, which can reach the charge pump （CP） simultaneously, and an improved CP is realized to minimize the charge sharing and the charge injection and make the current matched. Additionally, the delay is controllable owing to the programmable PFD, so the dead zone of the CP can be eliminated. The output frequency of the VCO can be adjusted continuously and precisely by using a programmable LC-TANK. The phase noise of the VCO is lowered by using appropriate MOS sizes. The proposed PLL frequency synthesizer is fabricated in a 0.18 μm mixed-signal CMOS process. The measured phase noise at 1 MHz offset from the center frequency is -127.65 dBc/Hz and the reference spur is -73.58 dBc.     

用于U波段移动数字电视的宽带大动态范围高线性度射频前端

A wideband large dynamic range and high linearity U-band RF front-end for mobile DTV is introduced,and includes a noise-cancelling low-noise amplifier(LNA),an RF programmable gain amplifier(RFPGA) and a current communicating passive mixer.The noise/distortion cancelling structure and RC post-distortion compensation are employed to improve the linearity of the LNA.An RFPGA with five stages provides large dynamic range and fine gain resolution.A simple resistor voltage network in the passive mixer decreases the gate bias voltage of the mixing transistor,and optimum linearity and symmetrical mixing is obtained at the same time.The RF front-end is implemented in a 0.25 μm CMOS process.Tests show that it achieves an ⅡP3(third-order intercept point) of –17 dBm,a conversion gain of 39 dB,and a noise figure of 5.8 dB.The RFPGA achieves a dynamic range of –36.2 to 23.5 dB with a resolution of 0.32 dB.     

一种电流复用共栅低噪声放大器的低功耗433/915-MHz射频前端的设计

This paper presents a wideband RF front-end with novel current-reuse wide band low noise amplifier(LNA),current-reuse V –I converter,active double balanced mixer and transimpedance amplifier for short range device(SRD) applications.With the proposed current-reuse LNA,the DC consumption of the front-end reduces considerably while maintaining sufficient performance needed by SRD devices.The RF front-end was fabricated in 0.18 μm RFCMOS process and occupies a silicon area of just 0.11 mm2.Operating in 433 MHz band,the measurement results show the RF front-end achieves a conversion gain of 29.7 dB,a double side band noise figure of 9.7 dB,an input referenced third intercept point of –24.9 dBm with only 1.44 mA power consumption from 1.8 V supply.Compared to other reported front-ends,it has an advantage in power consumption.     

一种基于低中频接收相位选择发射结构的工作在2.4GHz面向WPAN应用的超低功耗收发机

This paper presents a 2.4 GHz CMOS transceiver for the wireless personal area network （WPAN） inte- grated in 0.18/zm CMOS technology. This transceiver adopts a low-IF receiver, a MUX based transmitter and a fast-setting fractional-N frequency synthesizer. For achieving low cost and low power consumption, an inductor- less receiver front-end, an adaptive analog baseband, a low power MUX and a current-reused phase-locked loop （PLL） have been proposed in this work. Measured results show that the receiver achieves-8 dBrn of lIP3 and 31 dB of image rejection. The transmitter delivers 0 dBm output power at a data rate of 2 Mbps. The current consumption is 7.2 mA in the receiving mode and 6.9 mA in the transmitting mode, respectively.