640 Gbit/s (32×20 Gbit/s) WDM transmission with 0.4(bit/s)/Hz spectral efficiency using short-period dispersion-managedfibre

640 Gbit/s (32 channel×20 Gbit/s) WDM transmission with 0.4 (bit/s)/Hz spectral efficiency is demonstrated using short-period dispersion-managed fibre (Perfect Cable^TM). The average Q-factor was measured to be better than 18 dB after transmission over 280 km     

2.56 Tbit/s (32×80 Gbit/s) polarisation-bit-interleavedtransmission over 120 km NDSF with 0.8 bit/s/Hz spectral efficiency

Experimental results of 32×80 Gbit/s polarisation-bit-interleaved carrier-suppressed RZ transmission over 120 km of NDSF with 0.8 bit/s/Hz spectral efficiency are reported. System Q values between 6.1 and 8 (2³¹-1 pattern) were achieved with the use of distributed Raman amplification and polarisation demultiplexing     

1.28 Tbit/s (32×40 Gbit/s) WDM transmission over 2400 km ofTeraLightTM/Reverse TeraLight(C) fibres using distributedall-Raman amplification

1.28 Tbit/s capacity transmission of 32×40 Gbit/s, 100 GHz-spaced channels is demonstrated over 2400 km using distributed all-Raman amplification and electrical-TDM equipment over an optimised TeraLight^TM/Reverse TeraLight(C) dispersion map     

1.6 Tbit/s (40 × 42.7 Gbit/s) WDM transmission over 2400 kmof fibre with 100 km dispersion-managed spans

Transmission of 40 × 42.7 Gbit/s WDM channels is demonstrated over 2400 km of fibre with 100 km amplifier spacing and 100 GHz channel spacing. Dispersion-managed fibre spans, carrier-suppressed return-to-zero modulation format and hybrid Raman/erbium-doped fibre inline amplifiers were employed to achieve a record 40 Gbit/s, WDM transmission distance with 100 km terrestrial span lengths     

DPSK 32×10 Gb/s transmission modeling on 5×90 kmterrestrial system

Reduction of DWDM nonlinear fiber penalties by the use of DPSK modulation and an optically preamplified self-homodyning receiver is discussed. Maintaining a constant instantaneous channel power by phase shift keying, we can anticipate reduction of cross-phase modulation penalties. Our modeling results show 0.9-dB benefit in Q performance for 50-GHz spaced, 32×10 Gb/s transmissions with nonzero dispersion shifted fiber     

100 GHz-spaced 8×43 Gbit/s DWDM unrepeatered transmissionover 163 km using duobinary-carrier-suppressed return-to-zeroformat

A novel modulation format. the duobinary carrier-suppressed return-to-zero format, is proposed, its bandwidth is less than 100 GHz at 43 Gbit/s. 100 GHz-spaced DWDM unrepeatered transmission is demonstrated over 163 km at +10 dBm/channel with a crosstalk penalty under 1 dB     

2 Tbit/s (200×10 Gbit/s) over 9240 km transmission experimentwith 0.15 nm channel spacing using VSB format

2 Tbit/s (200 WDM×10 Gbit/s) transmission over 9240 km using only a C-band erbium-doped fibre amplifier is demonstrated. A vestigial sideband modulation scheme was adopted to realise 0.15 nm channel separation. Ultra-high spectral efficiency of 53% was achieved. All channels showed better than 9 dB Q-factor, which can be corrected to less than 10^-9 BER after OSW Super forward error correction     

16×20-Gb/s, 400-km WDM transmission over NZDSF using aslope-compensating fiber-grating module

We demonstrate 16-channel wavelength-division multiplexing transmission over nonzero dispersion-shifted fiber at a per-channel rate of 20 Gb/s. A broad-band dispersion-compensating grating module is used for compensation of dispersion and dispersion slope     

2×10 Gbit/s WDM 1310-nm optical transmission over 63.5-kmstandard single-mode fiber using optical preamplifiers

Twenty Gbit/s transmission over 63.5 km SMF at 1310 nm is reported by using two channel 10 Gbit/s wavelength (de)multiplexing (Δλ=1.5 nm). Two 1310 nm SL-MQW semiconductor optical amplifiers are utilized for loss compensation and sensitivity improvement. For the 1310 nm wavelength domain, a record bitrate x distance product of 1.27 Tbit/s.km has been obtained. Crosstalk penalties are identified, and the feasibility of an extension up to at least four, 10 Gbit/s channels is discussed     

A GaAs HBT 16×16 10-Gb/s/channel crosspoint switch

A 16×16 crosspoint switch IC has been designed and implemented in a 2-μm GaAs heterojunction bipolar transistor (HBT) technology. The IC is a strictly nonblocking switch with broadcast capability and asynchronous data paths. The IC has fully differential internal circuitry and is packaged in a custom high-speed assembly. Test results confirmed that the IC achieves a 10-Gb/s/channel (or 160-Gb/s aggregate) capacity, the highest reported to date for a 16×16 crosspoint switch IC     

Demonstration of 9×200 Mbit/s wavelength division multiplexedtransmitter

A multifrequency laser capable of generating 200 Mbit/s data rates simultaneously at nine different wavelengths is demonstrated. The laser is based on the monolithic integration of a waveguide grating router with semiconductor optical amplifiers and thus provides automatic alignment of the optical channel wavelengths. This multifrequency laser may have important applications for local access WDM networks     

800 Gbit/s (80×10.66 Gbit/s) transmission over 3200 km ofnon-zero dispersion shifted fibre with 100 km amplified spans employingdistributed Raman amplification

80×10.66 Gbit/s wavelength division multiplexing transmission over 3200 km fibre with 100 km amplifier spacing and 50 GHz channel spacing is demonstrated. Error-free transmission of all 80 channels is achieved by employing distributed Raman amplification, forward error correction and low dispersion slope TrueWave^R fibre     

40-Gb/s OTDM to 4×10 Gb/s WDM conversion in monolithic InPMach-Zehnder interferometer module

Transformation of high bit-rate optical time-domain multiplexed (OTDM) signals into a multitude of lower bit-rate wavelength-division-multiplexed (WDM) channels is demonstrated by means of a single monolithically integrated indium phosphide Mach-Zehnder interferometer with semiconductor optical amplifiers in its arms. Full demultiplexing of 10-Gb/s OTDM signals into 4×10-Gb/s WDM channels is demonstrated. Bit-error-rate penalties are below 1.5 dB for polarization independent signal conversion throughout the 1.55-μm wavelength range     

A 10-Gb/s high-isolation, 16×16 crosspoint switch implementedwith AlGaAs/GaAs HBT's

A high-isolation, 16×16 crosspoint switch is reported, capable of aggregate data throughput of 160 Gb/s with low crosstalk and output jitter. Each of the 16 fully asynchronous channels can transmit data at rates up to 10 Gb/s with a worst case r.m.s. output jitter of 4 ps. Single channel operation output jitter below 2.8 ps r.m.s. has been demonstrated. The high-isolation circuitry allows for inter-channel crosstalk isolation of more than 40 dB with all channels operative. The circuit is based on AlGaAs/GaAs heterojunction bipolar transistor technology     

A 250-Mb/s 32×32 CMOS crosspoint LSI for ATM switchingsystems

A 32×32 crosspoint LSI and a time-slot controlled asynchronous-transfer-mode (ATM) switch architecture utilizing the LSI are presented. The ATM switch, which is classified as an input-buffer-type ATM switch, enables 99% throughput and broadcasting capability. The crosspoint LSI is characterized by the bit-map oriented and pipelined connection control method which can switch and broadcast 160-Mb/s ATM cells, 32×32 switch cells which have less parasitic capacitance, and emitter-coupled-logic (ECL) compatible interfaces which are compatible with a 160-MHz broadband ISDN data rate. The LSI has been fabricated by a 1-μm CMOS process. The chip size is 7.4 mm×7.4 mm. According to the evaluation, operation at 250 Mb/s is confirmed. 1.2-W power consumption is observed at 160-Mb/s operating condition     

An experimental 5-Gb/s 16×16 Si-bipolar crosspoint switch

An experimental 16×16, nonblocking, asynchronous crosspoint switch with a data rate of 5-Gb/s per channel is presented. Implemented in a 0.8-μm, double-poly, self-aligned Si-bipolar ECL technology, the 3-mm×3-mm chip, featuring a multiplexer-type architecture with a three-device crosspoint cell, demonstrates a nominal data path delay of 420 ps with 12.5-ps RMS jitter and a setup time of 1 ns and dissipates about 4.6 W     

All-Raman transmission of 80 × 10 Gbit/s WDM signals with 50GHz spacing over 4160 km of dispersion-managed fibre

All-distributed-Raman amplification in backward-pumped 80 km spans is employed to transmit 80 × 10 Gbit/s non-return to zero (NRZ) wavelength division multiplexed (WDM) signals over 4160 km of a symmetrically-configured dispersion-managed fibre with no forward error correction. At the received bit error rate levels below 10^-9, this is a record capacity-distance product for terrestrial all-Raman systems     

A 70-Mbit/s (RZ) 16×16 crosspoint switch for ternary-encodedsignals

An experimental 16×16 crosspoint switch that can switch ternary signals and handle data rates of up to 70 Mb/s return-to-zero (RZ) (equivalent to 140-Mb/s nonreturn-to-zero (NRZ)) per channel is described. Ternary signals, in particular, alternate mark inversion (AMI) encoded signals, are widely used in telephone interoffice digital-transmission systems. This chip could be used in an asynchronous cross-connection system at the DS3 (44.736-Mb/s) signal level. This crosspoint chip has 16 input and 16 output channels. Any input can be connected to any output or outputs without blocking. The architecture allows for paralleling many chips to increase the size of the crosspoint array and also for cascading them to provide multistage switching capability. The switch can be addressed in the same way as a memory chip, and the cross-connection map can be written to and read back from the device. The chip is fabricated using a standard 2-μm CMOS technology, and the die size is 20.16 mm² (177.2×176.4 mil), containing about 11000 transistors     

A 622-Mb/s 8×8 ATM switch chip set with shared multibufferarchitecture

An asynchronous transfer mode (ATM) switch chip set, which employs a shared multibuffer architecture, and its control method are described. This switch architecture features multiple-buffer memories located between two crosspoint switches. By controlling the input-side crosspoint switch so as to equalize the number of stored ATM cells in each buffer memory, these buffer memories can be treated as a single large shared buffer memory. Thus, buffers are used efficiently and the cell loss ratio is reduced to a minimum. Furthermore, no multiplexing or demultiplexing is required to store and restore the ATM cells by virtue of parallel access to the buffer memories via the crosspoint switches. Access time for the buffer memory is thus greatly reduced. This feature enables high-speed switch operation. A three-VLSI chip set using 0.8-μm BiCMOS process technology has been developed. Four aligner LSIs, nine bit-sliced buffer-switch LSIs, and one control LSI are combined to create a 622-Mb/s 8×8 ATM switching system that operates at 78 MHz. In the switch fabric, 155-Mb/s ATM cells can also be switched on the 622-Mb/s port using time-division multiplexing     

A 40–44 Gb/s 3× Oversampling CMOS CDR/1:16 DEMUX

A CMOS CDR and 1:16 DEMUX fabricated in a low-cost 90 nm bulk CMOS process operates at 40-44 Gb/s and dissipates 910 mW. A quarter-rate hybrid phase-tracking/3times blind-oversampling architecture is used to improve jitter tolerance, reduce the need for high-power CML circuits, and enable frequency acquisition without a reference clock. Input data are sampled using a 24-phase distributed VCO, and a digital CDR recovers 16 bits and a 2.5 GHz clock from 48 demultiplexed samples spanning 16 UI. Conformance to the ITU-T G.8251 jitter tolerance mask (BER <10^-12 with a 2³¹-1 PRBS source) is demonstrated using both an on-chip and an external BERT.