High-speed and low-power repeater for VLSI interconnects

This paper proposes a repeater for boosting the speed of interconnects with low power dissipation. We have designed and implemented at 45 and 32 nm technology nodes. Delay and power dissipation performances are analyzed for various voltage levels at these technology nodes using Spice simulations. A significant reduction in delay and power dissipation are observed compared to a conventional repeater. The results show that the proposed high-speed low-power repeater has a reduced delay for higher load capacitance. The proposed repeater is also compared with LPTG CMOS repeater, and the results shows that the proposed repeater has reduced delay. The proposed repeater can be suitable for high-speed global interconnects and has the capacity to drive large loads.     

Optimization and scaling of CMOS-bipolar drivers for VLSI interconnects

In this paper, rules are presented for the optimized design of CMOS-bipolar drivers for large capacitive loads typical of VLSI interconnects. Simulations and closed-form solutions show that the n-p-n bipolar transistors have to be operated in the high-level injection mode, and that their sizes have to be tailored to the two-thirds power of the load, and it scales with the two-thirds power of the base width of the n-p-n transistor and with the one-third power of the channel length of the MOS transistor. For comparison, the CMOS cascade with a tailored second stage is shown to have competitive potential at the expense of an area being approximately 2.5 times larger than that of a CMOS-bipolar stage.     

Time-domain macromodel for lossy VLSI interconnects

A new time-domain model that enables loss effects on the input impedance of on-chip transmission lines during switching transients to be accurately taken into account is presented. The model has been specifically developed for use in conjunction with MOS macromodels to predict the electrical behaviour of matched CMOS buffers. It solves the problem of mixed frequency/time domain analysis by replacing the lines with a lumped time-varying resistor     

Architectural strategies for low-power VLSI turbo decoders

The use of "turbo codes" has been proposed for several applications, including the development of wireless systems, where highly reliable transmission is required at very low signal-to-noise ratios (SNR). The problem of extracting the best coding gains from these kind of codes has been deeply investigated in the last years. Also the hardware implementation of turbo codes is a very challenging topic, mainly due to the iterative nature of the decoding process, which demands an operating frequency much higher than the data rate; in the case of wireless applications, the design constraints became even more strict due to the low-cost and low-power requirements. This paper first presents a new architecture for the decoder core with improved area and power dissipation properties; then partitioning techniques are proposed to reduce the power consumption of the decoder memories. It is proven that most of the power is dissipated by the large RAM units required by the decoder, so the described technique is very efficient: an average power saving of 70% with an area overhead of 23% has been obtained on a set of analyzed architectures.     

Complementary ferroelectric-capacitor logic for low-power logic-in-memory VLSI

A novel nonvolatile logic style, called complementary ferroelectric-capacitor (CFC) logic, is proposed for low-power logic-in-memory VLSI, in which storage elements are distributed over the logic-circuit plane. Standby currents in distributed storage elements can be cut off by using ferroelectric-based nonvolatile storage elements, and the standby power dissipation can be greatly reduced. Since the nonvolatile storage and the switching functions are merged into ferroelectric capacitors by the capacitive coupling effect, reduction of active device counts can be achieved. The use of complementary stored data in coupled ferroelectric capacitors makes it possible to perform a switching operation with small degradation of the nonvolatile charge at a low supply voltage. The restore operation can be performed by only applying the small bias across the ferroelectric capacitor, which reduces the dynamic power dissipation. Applying the proposed circuitry in a fully parallel 32-bit content-addressable memory results in about 2/3 dynamic power reduction and 1/7700 static power reduction with chip size of 1/3, compared to a CMOS implementation using 0.6-/spl mu/m ferroelectric/CMOS.     

VLSI circuits for low-power high-speed asynchronous addition

This paper presents a new low-power high-speed fully static CMOS variable-time adder. The VLSI implementation proposed here is based on the statistical carry look-ahead addition technique. The new circuit takes advantage of an innovative way of using a composition of propagate signals and of appropriately designed overlapped execution modules to reduce average addition time, layout area, and power dissipation. A 56-bit adder designed as described here and realized using AMS 0.35-/spl mu/m CMOS standard cells at 3.3V supply voltage shows an average addition time of about 4.3 ns and a maximum power dissipation of only 50 mW at 200-MHz repetitive frequency using a silicon area of less than 0.23 mm/sup 2/.     

VLSI architecture for a low-power video codec system

In this paper, the design of a very large scale integration (VLSI) architecture for low-power H.263/MPEG-4 video codec is addressed. Starting from a high-level system modelling, a profiling analysis indicates a hardware–software (HW–SW) partitioning assuming power consumption, flexibility and circuit complexity as main cost functions. The architecture is based on a reduced instruction set computer engine, enhanced by dedicated hardware processing, with a memory hierarchy organisation and direct memory access-based data transfers. To reduce the system power consumption two main strategies have been adopted. The first consists in the design of a low-power high-efficiency motion estimator specifically targeted to low bit-rate applications. Exploiting the correlation of video motion field it attains the same high coding efficiency of the full-search approach for a computational burden lower than about two orders of magnitude. Combining the decreased algorithm complexity with low-power VLSI design techniques the motion estimator power consumption is scaled down to few mW. The second consists in the implementation of a proper buffer hierarchy to reduce memory and bus power consumption in the HW–SW communication. The effectiveness of the proposed architecture has been validated through performance measurements on a prototyping platform.     

High-current failure model for VLSI interconnects under short-pulsestress conditions

Short-time high joule heating causing thermal breakdown of metal interconnects in ESD/EOS protection circuits and I/O buffers has become a reliability concern. Such failures occur frequently during testing for latchup robustness and during ESD/EOS type events. In this work, heating and failure of passivated TiN/AlCu/TiN integrated circuit interconnects in a quadruple level metallization system of a sub-0.5 μm CMOS technology has been characterized under high-current pulse conditions. A model incorporating the heating of the layered metal system and the oxide surrounding it has been developed which relates the maximum allowable current density to the pulse width. The model is shown to be in excellent agreement with experimental results and is applied to generate design guidelines for ESD/EOS and I/O buffer interconnects     

A low-power correlation-derivative CMOS VLSI circuit for bearing estimation

We present a CMOS integrated circuit (IC) for bearing estimation in the low-audio range that performs a correlation derivative approach in a 0.35-/spl mu/m technology. The IC calculates the bearing angle of a sound source with a mean variance of one degree in a 360/spl deg/ range using four microphones: one pair is used to produce the indication and the other to define the quadrant. An adaptive algorithm decides which pair to use depending on the direction of the incoming signal, in such a way to obtain the best estimate. The IC contains two blocks with 104 stages each. Every stage has a delay unit, a block to reduce the clock speed, and a 10-bit UP/DN counter. The IC measures 2 mm by 2.4 mm, and dissipates 600 /spl mu/W at 3.3 V and 200 kHz. It is purely digital and uses a one-bit quantization of the input signals.     

Shape effect on electromigration in VLSI interconnects

The influence of the shape of VLSI interconnects on the lifetime due to electromigration is investigated. Simulations and experiments indicate that, in some cases, the right angle corners of the metal lines, widely interconnections layout of VLSI circuits, reduce the lifetime of such interconnects. Substitutions by more gradual, smaller angled corners improve electromigration lifetimes.     

Inter-CNT capacitance in mixed CNT bundle interconnects for VLSI circuits

This article presents a realistic inter-carbon nanotube (CNT) electrostatic coupling capacitance and tunnelling conductance model for a mixed CNT bundle. The change of potential across such a bundle necessitates the need to consider the inter-CNT capacitance in the equivalent circuit of CNT interconnects for very large scale integration circuits. The equivalent transmission line circuit model of a unit bundle containing one single-walled CNT (SWCNT) and one multi-walled CNT (MWCNT) has been shown. This new model is then used to calculate the delay induced by the inter-CNT capacitance and tunnelling conductance, which predicts the relative positioning of MW/SWCNTs in mixed CNT bundle.     

An analog VLSI low-power envelope periodicity detector

The low-power, low-cost detection of voices or engine rumble is a desirable function in many different applications. Typical approaches involving frequency-domain computation are quite computationally intensive and require a significant power budget. In an effort to construct a very low-power detector capable of acting as a wake-up signal for other systems, we have designed a low-power (less than 1.8-/spl mu/W) subthreshold analog very large-scale integration circuit that detects periodicity in the time-domain envelope of the acoustic signal. The circuit was fabricated in a commercially available 2-poly 1.5-/spl mu/m CMOS process and occupies an area of about 0.242 mm/sup 2/.     

Rapidly annealed Mo-Polycide For VLSI gates and interconnects

In this paper, the results of an investigation on the formation of Mo-polycide by sputtering from a composite target followed by rapid thermal annealing (RTA) is presented. The influences of target stoichiometry and other deposition parameters including cathode power, Ar-pressure, dc bias and substrate temperature were investigated before and after an RTA cycle. The deposition at high substrate temperature resulted in high oxygen content and high film stress. On the other hand, dc bias and Ar pressure have been found to have insignificant effect on film properties. A final MoSi₂ film resistivity of 72 μΩ cm was achieved by sputtering from a MoSi_2.1 target at ambient temperature followed by RTA at 1100° C for 10 s. This RTA cycle was compatible with that required for implant activation and glass reflow. NMOS FETs having Mo-polycide gates were fabricated using RTA to simultaneously activate implanted dopants and to reflow PSG. Excellent I-V characteristics of these devices indicate that no damage to gate oxide was induced by using rapidly annealed Mo-polycide.     

Isolation effects in single- and dual-plane VLSI interconnects

The issue of interline coupling in high-speed VLSI interconnects is addressed. A full-wave-based technique is used to numerically solve for the modes and hence the line voltages and currents for multiconductor microstrip. The accuracy of these results is compared with time-domain experimental data. Isolation lines placed between signal lines and grounded at both ends are considered as a means of significantly reducing crosstalk. It is shown that the performance of such lines depends on several factors such as relative mode velocities, signal rise and fall times, and line length. These points are illuminated by considering the effects of isolation lines in two geometries of interest in high-speed integrated circuits. On the basis of these results one can determine the usefulness of isolation lines for a given geometry     

VLSI implementation of low-power high-quality color interpolation processor for CCD camera

This paper presents a color interpolation technique for a single-chip charge-coupled device with color-filter-array format. We propose edge-direction weighting and the local gain approach to reconstruct missing color components. Simulations show that the proposed method can achieve better quality-complexity tradeoff than other algorithms. For real-time implementation, a cost-effective architecture consisting of a pipeline schedule is designed based on our new algorithm. With the time-sharing method, the VLSI architecture can interpolate various colors using a common computational kernel, reducing the circuit complexity. The prototype of the color interpolation processor has been successfully verified with a field-programmable gate array device. The chip only uses about 10K gates and two line buffers.     

A set of analytic formulas for capacitance of VLSI interconnects oftrapezium shape

In VLSI timing analysis, a quick and accurate extraction of interconnect line to line and line to ground capacitance is very important. This paper presents a set of analytic formulas for the capacitance of one, two, and three trapezium interconnect lines over a ground plane which show better than 7% agreement with the capacitance values from the numerical simulation     

A circuit model of a system of VLSI interconnects for time responsecomputation

A novel computational model based on the spectral-domain approach for the characterization of a dispersive multiconductor system is developed for time response computation. The model consists of two identical impedance networks and equivalent voltage-controlled voltage sources, and it is particularly suitable for timing analysis. Since the model is constructed based on full-wave analysis, the hybrid nature of the VLSI interconnects is taken care of, and thus the model is valid at high frequencies when the longitudinal field components are no longer negligible. Signal distortions due to the dispersive nature of a multiconductor system are demonstrated by an example     

A novel dimension-reduction technique for the capacitanceextraction of 3-D VLSI interconnects

In this paper, a new capacitance extraction method called the dimension-reduction technique (DRT) is presented for three-dimensional (3-D) very large-scale integration (VLSI) interconnects. The DRT converts a complex 3-D problem into a series of cascading simple two-dimensional (2-D) problems. Each 2-D problem is solved separately, thus we can choose the most efficient method according to the arrangement of conductors. We have used the DRT to extract the capacitance matrix of multilayered and multiconductor crossovers, bends, vias with signal lines, and open-end. The results are in close agreement with those of Ansoft's SPICELINK and the Massachusetts Institute of Technology's (MIT) FastCap, but the computing time and memory size used by the DRT are several (even ten) times less than those used by SPICELINK and FastCap     

An efficient and reliable MRF-based methodology for designing low-power VLSI circuits

Noise-interference is one of the major concerns in low-power VLSI circuits. Due to power supply downscaling, these circuits have an extremely limited noise margin that is inadequate for dealing with intrinsic and extrinsic noise. The MRF-based design has been accepted as a highly effective method for designing noise-tolerant low-power circuits. However, the MRF-based circuits suffer from a complex structure and the methods which tried to simplify the structure always sacrificed the noise immunity for hardware simplicity. In this paper, we propose a novel MRF-based method for designing efficient and reliable low-power VLSI circuits. For the first time, an innovative reliability boosting mechanism based on maximum conditional correct probability is incorporated into an efficient MRF-based structure which leads to highly reliable circuits with considerably low cost, delay, and power consumption. The proposed method demonstrates the best performance among all of the previously reported methods. Moreover, the Monte Carlo simulations confirm that the proposed method can preserve its superior noise immunity even under serious process, voltage, and temperature variations.