Leveraging bandwidth improvements to web servers through enhanced network interfaces

Markets nowadays demand applications that require high communication throughputs to reach their adequate levels of performance. Although the bandwidth of the network links has increased allowing multiple gigabits per second, taking advantage of these links accounts for a high communication overhead, and thus a lot of processor cycles are used for communication tasks, diminishing the processor cycles that remain available for the application. In this paper, we evaluate the performance in web applications of a network interface that as it is distributed among the processors currently available in the node takes advantage of both the hardware (multiprocessor nodes and multicore architectures, as well as programmable network interface cards) and software elements present in the system, thus improving not only the effective communication throughputs and latencies, but also the capacity of the nodes to satisfy the requirements of the applications. Here, the usefulness of this distributed network interface to improve the performance of either static or dynamic web servers is shown. The ubiquity and the different computation/communication rates that can be found in web applications make the analysis of web servers interesting, as it could provide relevant conclusions about the efficiency of the different approaches to the design of high-performance network interfaces.     

基于区块链的物联网可伸缩管理机制

为了解决大规模物联网（IoT）设备集中式管理的安全性和可伸缩性问题,提出一种基于区块链技术的轻量级物联网设备可伸缩管理框架。该框架采用区块链网络,在网络中部署智能合约为设备管理提供操作接口,利用设备管理器将轻量级物联网设备独立于区块链网络之外,并改进了区块链中拜占庭容错算法（PBFT）的一致性协议,增加了动态选举机制。仿真实验分别对改进共识算法的性能和机制的可伸缩性进行验证,结果表明,该机制具有良好的伸缩性,设备管理器每秒能响应约1 000次的请求。与传统PBFT算法相比,改进算法提高了交易吞吐量,缩短了交易延时,并减少了通信开销。     

Client-server computing on Shrimp

Technological advances in network and processor speeds do not lead to equally large improvements in the performance of client-server systems. For instance, hardware performance improvements do not translate into faster user applications. This is primarily because software overhead dominates communication. The Shrimp project at Princeton University seeks solutions to this problem. Shrimp (Scalable High-Performance Really Inexpensive Multiprocessor) supports protected user-level communication between processes by mapping memory pages between virtual address spaces. This virtual memory-mapped network interface has several advantages, including flexible user-level communication and very low overhead for initiating data transfers. Here, we examine two remote procedure call (RPC) protocols and one socket implementation for Shrimp that deliver almost undiminished hardware performance to user applications     

数据传输模式对用户态通信的性能影响分析

用户态通信允许应用程序从应用层直接访问网络接口，主机与网络接口之间的数据传输模式对协议性能有重要影响．有效的数据传输模式可以减少数据拷贝次数，降低数据传输开销，尽可能将网络硬件的高性能反映到用户层．本文详细分析了通信系统开销来源，讨论了Myrinet网络环境下不同数据传输模式的实现与特点，测试并分析了不同数据传输模式对用户态通信性能的影响，并给出了相应的适用环境．     

系统域网中用户级通信库的实现

在系统域网环境中,网络硬件具备非常优良的性能,然而传统的通信库存在大量不必的要软件开销,大幅度地降低了通信性能。通过允许用户进程直接访问网络设备并减少收发过程中的内存拷贝,可以避免由操作系统带来的开销,从而实现用户级通信,降低延迟并提高带宽。经过对用户级通信库的性能分析,可以发现用户级通信库具有更好的性能。     

VIA(Virtual Interface Architecture)上的软件DSM系统实现和性能

在由高性能PC搭建的Linux机群系统上，传统的网络接口体系结构引入了巨大的软件处理开销，无法满足虚拟共享存储并行应用对通信带宽、延迟和进程间同步的需求．用户级网络接口标准——虚拟接口体系结构(Vilxual Interface Architecture，VIA)与传统的网络接口体系结构相比，在软件协议开销、通信关键路径上操作系统的干预程度、通信和计算的重叠程度以及实现零拷贝等方面，具有明显的优势．通过在传统网络通信接口和VIA通信接口上虚拟共享存储系统的性能对比，采用VIA网络接口体系结构可有效地提高虚拟共享存储系统的性能和可扩展性．     

Coding for high availability of a distributed-parallel storagesystem

We have developed a distributed parallel storage system that employs the aggregate bandwidth of multiple data servers connected by a high-speed wide-area network to achieve scalability and high data throughput. This paper studies different schemes to enhance the reliability and availability of such network-based distributed storage systems. The general approach of this paper employs “erasure” error-correcting codes that can be used to reconstruct missing information caused by hardware, software, or human faults. The paper describes the approach and develops optimized algorithms for the encoding and decoding operations. Moreover, the paper presents techniques for reducing the communication and computation overhead incurred while reconstructing missing data from the redundant information. These techniques include clustering, multidimensional coding, and the full two-dimensional parity schemes. The paper considers trade-offs between redundancy, fault tolerance, and complexity of error recovery     

VI architecture communication features and performance on the Giganet cluster LAN

The virtual interface (VI) architecture standard was developed to satisfy the need for a high throughput, low latency communication system required for cluster computing. VI architecture aims to close the performance gap between the bandwidths and latencies provided by the communication hardware and visible to the application, respectively, by minimizing the software overhead on the critical path of the communication. This paper presents the results of a performance study of one VI architecture hardware implementation, the Giganet cLAN (cluster LAN). The focus of the study is to assess and compare the performance of different VI architecture data transfer modes and specific features that are available to higher-level communication software like MPI in order to aid the implementor to decide which VI architecture options to employ for various communication scenarios. Examples of such options include the use of send/receive vs. RDMA data transfers, polling vs. blocking to check completion of communication operations, multiple VIs, completion queues and scatter capabilities of VI architecture.     

基于嵌入式技术的远程抄电表系统的开发研究

论述了基于嵌入式技术的远程抄电表系统结构由服务器、通信控制模块和电表接口三部分组成。服务器端的软件负责对通信控制模块的管理、数据的收发与处理。系统嵌入通信控制模块实现抄表数据通过以太网络进行数据传输。给出了嵌入式通信控制模块的硬件结构和软件结构的设计过程。     

User-level network interface protocols

Modern high speed local area networks offer great potential for communication intensive applications, but their performance is limited by the use of traditional communication protocols, such as TCP/IP. In most cases, these protocols require that all network access be through the operating system, which adds significant overhead to both the transmission path (typically a system call and data copy) and the receive path (typically an interrupt, a system call, and a data copy). To address this performance problem, several user level communication architectures have been developed that remove the operating system from the critical communication path. The article describes six important issues to consider in designing communication protocols for user level architectures. The issues discussed focus on the performance and semantics of a communication system. These issues include data transfer, address translation, protection, and control transfer mechanisms, as well as the issues of reliability and multicast. To provide a basis for analyzing these issues, the authors present a simple network interface protocol for Myricom's Myrinet network, which has a programmable network interface. Researchers can thus explore many protocol design options, and several groups have designed communication systems for Myrinet. The authors refer to 11 such systems, all of which differ significantly in how they resolve these design issues but all of which aim for high performance and provide a lean, low level, and more or less generic communication facility     

Notification and multicast networks for synchronization and coherence

This paper presents two different multistage interconnection network designs for shared-memory multiprocessors that provide unrestricted multicast and notification capabilities. The networks allow efficient synchronization and communication because they conserve network bandwidth by eliminating polling and by performing multicast to multiple recipient processors, as opposed to broadcast or individual messages per recipient processor. Simulation results show that the use of these networks not only decreases synchronization overhead, but also increases network performance for nonsynchronization traffic. The hardware complexity of these schemes is reasonable, making them practical for real systems. Their use in supporting efficient directory-based update or invalidate cache coherence is also discussed.     

The Network Architecture of the Connection Machine CM-5

The Connection Machine Model CM-5 Supercomputer is a massively parallel computer system designed to offer performance in the range of 1 teraflops (10¹²floating-point operations per second). The CM-5 obtains its high performance while offering ease of programming, flexibility, and reliability. The machine contains three communication networks: a data network, a control network, and a diagnostic network. This paper describes the organization of these three networks and how they contribute to the design goals of the CM-5.     

高速网络流采集系统的设计与实现

针对基于软件的网络流采集系统不能高效处理高速网络流量,以及为了提高采集效率需要同时对多种网络流进行采集的问题,提出一种基于软硬件结合的高速网络流采集框架,探讨在NetFPGA-10G平台实现高速网络流采集系统,称之为HSNTCS。该系统在硬件上通过精确串匹配引擎或正则表达式匹配引擎过滤、分类出所需的多种网络流后,将其传至内核驱动层对应的数据缓冲区,然后直接拷贝至用户空间并存储至对应的数据库。经实验测试,在精确串匹配情况下,用硬件方式实现的高速网络流采集系统的用户数据报协议(UDP)、传输控制协议(TCP)吞吐率都达到1.2Gb/s,约是用软件方式实现的3倍;在正则表达式匹配情况下,用硬件方式实现的高速网络流采集系统的UDP、TCP吞吐率都达到640Mb/s,约是用软件方式实现的3倍。结果表明,相对于软件实现方式,硬件实现具有更高的采集性能。     

基于FPGA的软件定义协议无关解析器

随着信息技术的繁荣发展,各种功能的异构网络层出不穷,异构融合网络成为下一代网络发展的必然趋势。实现异构网络之间的通信,网络转发设备必不可少。传统的转发设备仅支持固定的协议配置,缺乏可扩展性,无法支持新的网络协议。针对这种情况,提出了一种基于FPGA的软件定义协议无关解析器,通过软件定义解析流程,给予解析器灵活可编程的特性,无须对硬件设备进行更改即可完成对多种协议数据包的解析并提取出数据包转发所需的关键信息。通过高性能FPGA平台对解析器进行了实现,并进行了硬件资源开销和性能的评估。实验结果表明,可以完成多种异构网络协议的快速解析,得到完整的解析数据。     

High performance network virtualization with SR-IOV

Virtualization poses new challenges to I/O performance. The single-root I/O virtualization (SR-IOV) standard allows an I/O device to be shared by multiple Virtual Machines (VMs), without losing performance. We propose a generic virtualization architecture for SR-IOV-capable devices, which can be implemented on multiple Virtual Machine Monitors (VMMs). With the support of our architecture, the SR-IOV-capable device driver is highly portable and agnostic of the underlying VMM. Because the Virtual Function (VF) driver with SR-IOV architecture sticks to hardware and poses a challenge to VM migration, we also propose a dynamic network interface switching (DNIS) scheme to address the migration challenge. Based on our first implementation of the network device driver, we deployed several optimizations to reduce virtualization overhead. Then, we conducted comprehensive experiments to evaluate SR-IOV performance. The results show that SR-IOV can achieve a line rate throughput (9.48 Gbps) and scale network up to 60 VMs, at the cost of only 1.76% additional CPU overhead per VM, without sacrificing throughput and migration.     

一个基于386EX的高速串行通信接口

描述了一个基于嵌入式微处理器386EX的高速串行通信接口的设计与实现,利用386EX所集成的外围部件和双端口存储器,实现工业网络的高速可靠通讯,并支持嵌入式软件的开发。     

一种基于方向天线和时间同步机制的多信道无线网状网MAC协议

在城市小区和广阔的农村建立低成本的无线网状网,为无线终端用户提供高速的接入服务,是一项极具现实意义的工作.设计了一种适合于此类网络的MAC层协议称为Mesh-MAC,该协议建立在已有的IEEE 802.11硬件产品基础上,每两个节点之间的通信是由一对方向天线完成,通过一种全新的时间同步方案,可以实现M ESH网内高效的数据转发.仿真结果表明,与IEEE 802.11及2P协议相比,Mesh-MAC协议在吞吐量和端到端传输延时等方面,都有明显的改善.     

Exploiting the capabilities of the interconnection network on Dawning-1000

On Dawning-1000,the two-dimension mesh interconnection network enables low-latency,high-bandwidth communication,however,these capabilities have not been realized because of the high processing overhead imposed by existing communication software.Active Messages provide an efficient communication mechanism with small overhead,which may expose the raw capabilities of the underlying hardware.In addition,one of the most promising techniques,use-level communication,is often used to improve the performance of the traditional protocols such as TCP and UDP,and is also adopted in implementing the novel abstractions like Active Messages.Thus a user-level Active Messages model is designed and implemented on Dawning-1000.Preliminary experiments show that the combination of Active Messages mechanism and user-level communication technique is quite efficient in reducing software overhead associated with sending and receiving messages,and in exploiting the capabilities of the interconnection network.     

Factors influencing ATM adapter throughput

Analytical and experimental evaluations show that ATM adapters can perform quite close to their designed limits, provided that they are used in a properly configured environment with series resources capable of sustaining the desired throughputs. While the media speed may be 155, 100 or 25 Mbps, there are a number of factors that will determine the final achieved maximum throughput observed by a user of a ATM adapter. One is the overhead inherent to ATM, such as the 5 byte ATM header that accompanies every 48 bytes of data sent. Others are inherent in the protocol used in the communication layers above ATM (e.g., pacing and retransmission associated with TCP/IP). Still others are dependent upon the processor speed and operating system used by the adapter host system. This paper discusses those parameters that, based on our experience, can have a considerable impact on the throughput of an ATM adapter. Turboways¹ 25, 100 and 155 ATM adapter measurements illustrate these issues. These represent end-to-end (application layer-to-application layer) throughput measurements, involving all supporting hardware (workstations, 8260 ATM hub/switch, 8282 ATM concentrator, etc.) and all protocol layers, operating system, etc.This work was supported in part through the 1994 and 1995 IBM SUR grants, the IBM-NCSU ATM partnership effort and NSF award ACS-9418960.     

高速网络环境下的入侵检测技术研究综述*

高速网的普及应用对入侵检测技术提出了更高要求,传统的方法已难以适应处理大流量的网络数据。对入侵检测过程进行分析,指出高速网络环境下制约入侵检测效果的不利因素和难点,强调应从数据包捕获、模式匹配、负载均衡、系统架构等方面入手,充分利用软件的灵活性、专用硬件的并行性和快速性来提高入侵检测系统的性能,以适应高速的网络环境。