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本文结构3GPP W-CDMA的最新协议,介绍了W-CDMA系统的两次扩频结构,讨论了其中使用的OVSF码与扰码的主要特性及其在W-CDMA系统中的应用,文章的最后讨论了在工程实际中实时产生扩频码的方法。 相似文献
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本文考虑加性白噪声环境中的同步CDMA通信系统,给出了一种新的线性非相干解调接收机,同时给出了这种抗多址干扰接收机的误码率及渐近效率。结果表明,对于使用Gold码作特征码的CDMA系统,当用户数不大于特征码长度时,这种接收机的最小渐近效率是0.5 相似文献
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码分多址(CDMA)技术已作为第三代数字移动通信及个人通信系统的无线接入技术进行广泛的研究和应用。而CDMA系统中扩频序列问题一直是CDMA技术中的关键问题。文献4给出了S-CDMA系统中的扩频序列实数加编码的新方法,但对构造具有纠错能力的扩序列至今尚未发现。本文给了了S-CDMA系统中具有纠错能力的一类新的扩频序列和它的译码算法。 相似文献
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AD6121为3V接收机中频子系统,带有集成电压调节器,片内I/Q解调器可提供差分正交基带输出,并可与CDMA基带转换器接口,AD6121可用于CDMA、W-CDMA、AMPS和TACS应用系统中的接收机和AQPSK接收机,文中介绍了AD6121的原理和特点,并给出了典型的应用电路。 相似文献
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A linear decentralized receiver capable of suppressing multiple-access interference (MAI) for asynchronous direct-sequence code-division multiple-access (DS-CDMA) systems with aperiodic random signature sequences is proposed. Performance bounds on this receiver are also obtained. Using them as performance measures, the problem of chip waveform selection in DS-CDMA systems with the proposed receiver under the near-far scenario is investigated. In particular, the performance of several practical chip waveforms is compared. An LMS-type adaptive algorithm is developed to obtain the parameters needed in the receiver, which only requires the signature sequence and coarse timing information of the desired user 相似文献
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Chung B.-Y. Chien C. Samueli H. Jain R. 《Selected Areas in Communications, IEEE Journal on》1993,11(7):1096-1107
A VLSI architecture for an all-digital binary phase shift keying (BPSK) direct-sequence (DS) spread spectrum (SS) intermediate frequency (IF) receiver is presented, and an in-depth performance analysis is given. The all-digital architecture incorporates a Costas loop for carrier recovery and a delay-locked loop for clock recovery. For the pseudorandom noise (PN) acquisition block, a robust energy detection scheme is proposed to reduce false PN locks over a broad range of signal-to-noise ratios. The proposed architecture is intended for use in the 902-928 MHz unlicensed spread spectrum radio band. A 100 kbs information rate and a 12.7 Mchips/second PN code rate are assumed. The IF center frequency is 12.7 MHz and the IF sampling rate is 50.8 Msamples/second, which is the Nyquist rate for the 25.4 MHz bandwidth signal. Finite wordlength effects have been simulated to optimize the architecture, thereby minimizing the chip area, and results of the finite wordlength simulations demonstrate that the chip architecture achieves a bit error rate performance within 1 dB of theory in an additive white Gaussian noise channel 相似文献
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Migration towards a full-digital implementation of modems is currently one of the main trends in transmission systems design. The authors describe a noncoherent all-digital delay lock loop (DDLL) suited for chip timing synchronization in band-limited direct sequence spread spectrum (DS/SS) systems, and they thoroughly analyze its performance. The key features of this novel scheme are represented by its low-complexity processing section together with its good tracking capability. Analytical expressions for the DDLL S-curve and steady-state timing jitter are derived and confirmed by a time-domain computer simulation. Furthermore, the Mean Time to Lose Lock (MTLL) of the loop is evaluated and some numerical results are reported. The proposed chip timing synchronization scheme reveals also an improved tracking performance when compared to the traditional analog DLL for rectangular chip DS/SS signals 相似文献
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中频数字化直接序列扩频接收机的实现 总被引:1,自引:1,他引:0
给出了统一信道直接序列扩频通信系统的中频数字化接收机的实现方案。采用该方案所实现的直接序列扩频通信系统的载波与伪随机码的捕获分别采用了FFT辅助捕获技术,载波的跟踪采用了数字CPAFC环路牵引,数字COST-AS环路精确跟踪技术,伪码跟踪采用的是数字DLL环路实现。系统中I通道采用可编程GOLD扩频,Q通道采用截断m序列直扩,并置截断m序列与GOLD码具有相同速率、倍周期的关系,以简化系统伪码的同步电路设计。最后,讨论了该系统应用于扩频测距时,测量数据的"置中值"处理方法。 相似文献
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A digital communication receiver, called a third-generation receiver, has been developed. This receiver takes samples of the direct-sequence spread signal at a nonzero intermediate frequency (IF) instead of the zero IF (baseband), and quantizes the samples by employing a 1-b analog-to-digital (A/D) converter at the receiver front end. These 1-b samples are digitally processed for pseudonoise (PN) code, carrier, bit synchronization, and bit decision with the use of an application-specific integrated circuit. The effects of the IF sampling and 1-b A/D conversion on PN code synchronization are analyzed for a PN spread-spectrum communication system with oversampling rate, e.g., 12 samples per chip. In addition, the bit-error rate (BER) degradation due to the 1-b A/D conversion is studied by assuming perfect PN code, carrier, and bit synchronization. It is observed that the BER degradation due to the 1-b A/D is significant, e.g., 2.4 dB, when decimation is made after IF sampling such that only one sample per chip is used for bit decision. These analyzed BER results agree well with the simulated results. However, if no decimation is made and oversampling is used for bit decision, BER degradation due to 2-b A/D conversion is insignificant, e.g., 0.6 dB 相似文献
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Jen-Shi Wu Ming-Luen Liou Hsi-Pin Ma Tzi-Dar Chiueh 《Solid-State Circuits, IEEE Journal of》1997,32(10):1499-1510
In this paper, an all-digital differentially encoded quaternary phase shift keying (DEQPSK) direct sequence spread-spectrum (DSSS) transceiver is proposed. The transceiver consists of two parts: a baseband/IF spread-spectrum transmitter and a coherent intermediate frequency (IF) receiver. The center frequency of this IF receiver is 11 MHz and the sampling rate is 44 Msamples/s. Modulation/demodulation, carrier recovery, PN acquisition, and differential coding are all provided within a single chip. Functional optimization and architecture design were performed before layout implementation. The 0.8-μm N-well CMOS chip has a complexity of 56000 transistors with a core area of 3.5×3.5 mm2. Power dissipation is 92 and 145 mW at 2.6 and 3.3 V, respectively 相似文献
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Davis M. Monk A. Milstein L.B. 《Selected Areas in Communications, IEEE Journal on》1996,14(8):1488-1499
Several practical methods are proposed for the implementation of linear filters that reject multiple-access noise in direct sequence code-division multiple-access (DS-CDMA) receivers. These methods rely on taking advantage of variations in the received chip spectrum, and do not require locking and despreading multiple signals. The resulting structures are simple, and some can operate at a high chip rate. Adaptive structures are also proposed. It is shown that a close relationship exists between noise whitening and chip-equalization for a DS-CDMA receiver. System issues affecting the choice of the chip spectrum, and thus the applicability of these methods, are described 相似文献
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Software defined radio (SDR) is a technology that allows a single terminal to support various kinds of wireless systems by changing its software to reconfigure itself. A general purpose processor (GPP) based SDR receiver platform named Sora has been recently developed by Microsoft. In the GPP based SDR receiver, timing synchronization of an OFDM signal consumes a significant amount of computational resources in the GPP. In this paper, a timing synchronization scheme which uses delayed correlation and matched filtering for the GPP based SDR platform is evaluated. The two stage timing synchronization scheme reduces the computational complexity by limiting the timing range of matched filtering. The proposed scheme reduces the amount of data transmission between the memory and the GPP of the SDR platform. It is shown through an experiment that the proposed scheme reduces the number of cycles for timing synchronization by up to 30 %. 相似文献