WH-m/M相乘复合码扩频系统的互扰统计特性

本文建立了复合码ＤＳ－ＣＤＭＡ扩频系统的数学模型,推导了多址干扰的数学表示,定义了用户之间的互扰因子,并进行了计算,研究发现,在扩频比相同的上,若ＰＮ序列周期大小扩频比,且序列的伪随机性产好,则采用ＷＨ－ｍ／Ｍ复合序列与采用ｍ－Ｍ序列的扩频系统,其互扰因子均呈高斯分布,且数字特征相同,当ＰＮ序列周期等于扩频比时,互扰因子不具有高斯分布特性,该结论不要求扩频比足够大,而且对同步和异步ＤＳ－ＣＤＭＡ通     

3@—W—CDMA系统的扩频结构与扩频码

本文结构３ＧＰＰ Ｗ－ＣＤＭＡ的最新协议,介绍了Ｗ－ＣＤＭＡ系统的两次扩频结构,讨论了其中使用的ＯＶＳＦ码与扰码的主要特性及其在Ｗ－ＣＤＭＡ系统中的应用,文章的最后讨论了在工程实际中实时产生扩频码的方法。     

差分相干同步CDMA信道中的一种新的抗多址干扰接收机

本文考虑加性白噪声环境中的同步ＣＤＭＡ通信系统，给出了一种新的线性非相干解调接收机，同时给出了这种抗多址干扰接收机的误码率及渐近效率。结果表明，对于使用Ｇｏｌｄ码作特征码的ＣＤＭＡ系统，当用户数不大于特征码长度时，这种接收机的最小渐近效率是０．５     

威迪森进军W-CDMA无线接入芯片市场

深圳威迪森（ＷＩＲＥＬＥＳＳ　ＤＩＧＩＴＡＬ ＣＥＮＴＥＲ）通信技术有限公司,是国内专业从事无线扩频通信产品开发及生产的高科技公司、继推出“ＷＤＣ无线数字扩频平台”产品后,该公司又将研发第二代改良产品。从第一代的模块转向第二代的ＡＳＩＣ,并实现性能上升级。这片 ＡＳＩＣ现定位于Ｗ－ＣＤＭＡ,主要应用面向第三代移动通信Ｗ－ＣＤＭＡ无线 威迪森公司总经理董涛表示。威迪森是根据市场需求研发这片ＡＳＩＣ的,是公司现有“ＷＤＣ无线数字扩频平台”产品的改良和升级。另外,第三代移动通信的技术基础是扩频;而威迪森 …     

一种基于带通RAKE接收机的多载波解调方法

ＣＤＭＡ２０００采用多载波和直接序列扩频两种方式来达到提供宽带数据业务的目的。针对ＣＤＭＡ２０００前向信道的三载波调制方式,提出了一种基于带通ＲＡＫＥ接收机的多载波解调方法。这种方法避开了设计多比特的基带数字滤波器,从而大大降低了实现的复杂度。文章首先分析了三载波的调制结构。根据ＲＡＫＥ接收机的原理,推导出相应的带通ＲＡＫＥ接收机模型并给出解调结构,最后,用ＳＰＷ软件对此模型进行仿真并给出了传真结     

双正交多码CDMA系统在衰落信道的性能分析

在直接序列扩频通信（ＤＳ／ＣＤＭＡ）系统中,为了有效地实现用户高数据率的传输,以适应宽带ＣＤＭＡ技术发展的要求,本文提出了一种双正交多码ＣＤＭＡ系统（称为ＢＭＣ－ＣＤＭＡ）。相似于多载波调制,传输的高数据泫首先进行串－并转换,然后对变换后的低数据流用双正交码进行扩频调制。不同于多载波调制,各支路扩频信号用同一载波进行调制。并对此系统在衰落信道性能进行了计算,还对数值结果进行了分析。     

正交序列扩频多码CDMA系统在AWGN信道的性能分析

在直接序列扩频通信（ＤＳ－ＣＤＭＡ）系统中，为了有效地实现用户高数据率的传输，本文提出了一种正交扩频多码ＣＤＭＡ系统（称为ＯＭＣ－ＣＤＭＡ）。相似于多载波调制，传输的高数据率首先进行串－并转换，然后对转换后的低数据流用正交序列进行扩频调制。不同于多载波调制，各支路扩频信号用同一载波进行调制。这里，我们对此系统在ＡＷＧＮ信道的性能进行了计算，并对数值结果进行了分析。     

同步CDMA系统中一类新的扩频序列

码分多址（ＣＤＭＡ）技术已作为第三代数字移动通信及个人通信系统的无线接入技术进行广泛的研究和应用。而ＣＤＭＡ系统中扩频序列问题一直是ＣＤＭＡ技术中的关键问题。文献４给出了Ｓ－ＣＤＭＡ系统中的扩频序列实数加编码的新方法,但对构造具有纠错能力的扩序列至今尚未发现。本文给了了Ｓ－ＣＤＭＡ系统中具有纠错能力的一类新的扩频序列和它的译码算法。     

带有集成电压调节器的CDMA接收机中频子系统芯片AD6121

ＡＤ６１２１为３Ｖ接收机中频子系统,带有集成电压调节器,片内Ｉ／Ｑ解调器可提供差分正交基带输出,并可与ＣＤＭＡ基带转换器接口,ＡＤ６１２１可用于ＣＤＭＡ、Ｗ－ＣＤＭＡ、ＡＭＰＳ和ＴＡＣＳ应用系统中的接收机和ＡＱＰＳＫ接收机,文中介绍了ＡＤ６１２１的原理和特点,并给出了典型的应用电路。     

采用多重TCM的室内无线DS／SSMA系统性能分析

本文将多重ＴＣＭ技术应用于室内慢衰落信道下的直接序列扩频多址（ＤＳ／ＳＳＭＡ）系统中，提出了一种发射端和接收端分别采用多重伪码扩频和多重相关接收的ＤＳ／ＳＳＭＡ系统模型及其理论分析方法。在系统用户数、用户信源比特速率和伪码周期相同的条件下，模拟结果表明采用多重ＴＣＭ的ＤＳ／ＳＳＭＡ系统性能显著优于一重ＴＣＭＤＳ／ＳＳＭＡ系统的性能     

Asynchronous multiple-access interference suppression and chipwaveform selection with aperiodic random sequences

A linear decentralized receiver capable of suppressing multiple-access interference (MAI) for asynchronous direct-sequence code-division multiple-access (DS-CDMA) systems with aperiodic random signature sequences is proposed. Performance bounds on this receiver are also obtained. Using them as performance measures, the problem of chip waveform selection in DS-CDMA systems with the proposed receiver under the near-far scenario is investigated. In particular, the performance of several practical chip waveforms is compared. An LMS-type adaptive algorithm is developed to obtain the parameters needed in the receiver, which only requires the signature sequence and coarse timing information of the desired user     

Performance analysis of an all-digital BPSK direct-sequencespread-spectrum IF receiver architecture

A VLSI architecture for an all-digital binary phase shift keying (BPSK) direct-sequence (DS) spread spectrum (SS) intermediate frequency (IF) receiver is presented, and an in-depth performance analysis is given. The all-digital architecture incorporates a Costas loop for carrier recovery and a delay-locked loop for clock recovery. For the pseudorandom noise (PN) acquisition block, a robust energy detection scheme is proposed to reduce false PN locks over a broad range of signal-to-noise ratios. The proposed architecture is intended for use in the 902-928 MHz unlicensed spread spectrum radio band. A 100 kbs information rate and a 12.7 Mchips/second PN code rate are assumed. The IF center frequency is 12.7 MHz and the IF sampling rate is 50.8 Msamples/second, which is the Nyquist rate for the 25.4 MHz bandwidth signal. Finite wordlength effects have been simulated to optimize the architecture, thereby minimizing the chip area, and results of the finite wordlength simulations demonstrate that the chip architecture achieves a bit error rate performance within 1 dB of theory in an additive white Gaussian noise channel     

A digital chip timing recovery loop for band-limiteddirect-sequence spread-spectrum signals

Migration towards a full-digital implementation of modems is currently one of the main trends in transmission systems design. The authors describe a noncoherent all-digital delay lock loop (DDLL) suited for chip timing synchronization in band-limited direct sequence spread spectrum (DS/SS) systems, and they thoroughly analyze its performance. The key features of this novel scheme are represented by its low-complexity processing section together with its good tracking capability. Analytical expressions for the DDLL S-curve and steady-state timing jitter are derived and confirmed by a time-domain computer simulation. Furthermore, the Mean Time to Lose Lock (MTLL) of the loop is evaluated and some numerical results are reported. The proposed chip timing synchronization scheme reveals also an improved tracking performance when compared to the traditional analog DLL for rectangular chip DS/SS signals     

一种改进型PN码定时跟踪环

该文提出和研究了一种用于直接序列扩频系统的全数字非相干PN码定时跟踪环,除利用超前/滞后支路相关值的差别外,它还利用了准时支路的相关值信息。理论分析和仿真结果表明,在典型AWGN信道条件下,新方案改善了环路性能,并且算法复杂度明显降低。     

中频数字化直接序列扩频接收机的实现

给出了统一信道直接序列扩频通信系统的中频数字化接收机的实现方案。采用该方案所实现的直接序列扩频通信系统的载波与伪随机码的捕获分别采用了FFT辅助捕获技术,载波的跟踪采用了数字CPAFC环路牵引,数字COST-AS环路精确跟踪技术,伪码跟踪采用的是数字DLL环路实现。系统中I通道采用可编程GOLD扩频,Q通道采用截断m序列直扩,并置截断m序列与GOLD码具有相同速率、倍周期的关系,以简化系统伪码的同步电路设计。最后,讨论了该系统应用于扩频测距时,测量数据的"置中值"处理方法。     

Third-generation TDRSS-compatible direct-sequence spread-spectrumdigital receiver

A digital communication receiver, called a third-generation receiver, has been developed. This receiver takes samples of the direct-sequence spread signal at a nonzero intermediate frequency (IF) instead of the zero IF (baseband), and quantizes the samples by employing a 1-b analog-to-digital (A/D) converter at the receiver front end. These 1-b samples are digitally processed for pseudonoise (PN) code, carrier, bit synchronization, and bit decision with the use of an application-specific integrated circuit. The effects of the IF sampling and 1-b A/D conversion on PN code synchronization are analyzed for a PN spread-spectrum communication system with oversampling rate, e.g., 12 samples per chip. In addition, the bit-error rate (BER) degradation due to the 1-b A/D conversion is studied by assuming perfect PN code, carrier, and bit synchronization. It is observed that the BER degradation due to the 1-b A/D is significant, e.g., 2.4 dB, when decimation is made after IF sampling such that only one sample per chip is used for bit decision. These analyzed BER results agree well with the simulated results. However, if no decimation is made and oversampling is used for bit decision, BER degradation due to 2-b A/D conversion is insignificant, e.g., 0.6 dB     

A 2.6-V, 44-MHz all-digital QPSK direct-sequence spread-spectrumtransceiver IC [wireless LANs]

In this paper, an all-digital differentially encoded quaternary phase shift keying (DEQPSK) direct sequence spread-spectrum (DSSS) transceiver is proposed. The transceiver consists of two parts: a baseband/IF spread-spectrum transmitter and a coherent intermediate frequency (IF) receiver. The center frequency of this IF receiver is 11 MHz and the sampling rate is 44 Msamples/s. Modulation/demodulation, carrier recovery, PN acquisition, and differential coding are all provided within a single chip. Functional optimization and architecture design were performed before layout implementation. The 0.8-μm N-well CMOS chip has a complexity of 56000 transistors with a core area of 3.5×3.5 mm². Power dissipation is 92 and 145 mW at 2.6 and 3.3 V, respectively     

A noise whitening approach to multiple-access noise rejection .II.Implementation issues

Several practical methods are proposed for the implementation of linear filters that reject multiple-access noise in direct sequence code-division multiple-access (DS-CDMA) receivers. These methods rely on taking advantage of variations in the received chip spectrum, and do not require locking and despreading multiple signals. The resulting structures are simple, and some can operate at a high chip rate. Adaptive structures are also proposed. It is shown that a close relationship exists between noise whitening and chip-equalization for a DS-CDMA receiver. System issues affecting the choice of the chip spectrum, and thus the applicability of these methods, are described     

Two Step Timing Synchronization Scheme for OFDM Signal in General Purpose Processor Based Software Defined Radio Receiver

Software defined radio (SDR) is a technology that allows a single terminal to support various kinds of wireless systems by changing its software to reconfigure itself. A general purpose processor (GPP) based SDR receiver platform named Sora has been recently developed by Microsoft. In the GPP based SDR receiver, timing synchronization of an OFDM signal consumes a significant amount of computational resources in the GPP. In this paper, a timing synchronization scheme which uses delayed correlation and matched filtering for the GPP based SDR platform is evaluated. The two stage timing synchronization scheme reduces the computational complexity by limiting the timing range of matched filtering. The proposed scheme reduces the amount of data transmission between the memory and the GPP of the SDR platform. It is shown through an experiment that the proposed scheme reduces the number of cycles for timing synchronization by up to 30 %.     

动态环境中频数字接收机载波同步研究

文中介绍了中频数字接收机的实现结构和关键的载波同步技术,针对动态环境下载波同步需要解决的捕获带宽,捕获速度与精度的矛盾,利用传统锁频（FLL）环路和锁相（PLL）环路的优点,设计了一种适合动态环境下中频数字接收机的FLL＋PLL联合工作的方案。最后结合计算机仿真分析结果,证明了该方案的可行性和优越性,为进一步的硬件实现提供了参考。