A 50-Gbit/s 450-mW Full-Rate 4:1 Multiplexer With Multiphase Clock Architecture in 0.13- μm InP HEMT Technology

A full-rate multiplexer (MUX) with a multiphase clock architecture for over 40 Gbit/s optical communication systems is presented. The 4:1 MUX is comprised of a re-timer based on a D-type flip-flop (DFF) and a clock tree system that uses EXOR-type delay buffers to match its skews well to those of the data. The supply voltage is reduced to -1.5 V by analyzing the voltage allocation. Fabricated in a 0.13-mum InP HEMT technology, a DFF test circuit achieved 75-Gbit/s operation and exhibited performance sufficient to re-time 50-Gbit/s serialized data. The 4:1 MUX measurement results demonstrate successful 50-Gbit/s operation at room temperature, and 40-Gbit/s operation, which has 10^-11 error free for 2³¹ - 1 pseudorandom bit stream (PRBS) data, up to an ambient temperature of 90 degrees or down to - 1.24 V of supply voltage. The circuit consumes 450 mW at a - 1.5-V supply and exhibits an output jitter of 283 fs rms at 50-Gbit/s operation. We also propose a multiphase clock generator for a MUX that has a serialization of more than four channels     

Differential precoder IC modules for 20-and 40-Gbit/s opticalduobinary transmission systems

This paper reports on 20- and 40-Gbit/s differential precoder modules for optical duobinary transmission systems. These precoder modules overcome the speed limit of a conventional precoder by parallel processing. The proposed precoders handle two or four parallel signals before multiplexing with data rates of one-half or one-quarter the transmission bit rate, and the final preceded signal is obtained by multiplexing the precoder output bit by bit, production-level 0.2-μm gate-length GaAs MESFET's were used to fabricate the precoders. The precoders are mounted in an RF package. They successfully performed 20- and 40-Gbit/s precoding for the first time, and the 20-Gbit/s precoder achieved a maximum precoding rate of 22 Gbit/s, which is 76% faster than that of the conventional circuit using the same MESFETs. The 40-Gbit/s precoder performs 40-Gbit/s precoding when combined with a 40-Gbit/s multiplexer unit. Twenty-Gbit/s optical duobinary transmitter and receiver circuits using the 20-Gbit/s precoder module successfully generate fully encoded optical duobinary signal at this rate for the first time. These circuits show a receiver sensitivity of -28.6 dBm for a bit error rate of 1×10^-9     

40-Gbit/s TDM transmission technologies based on ultra-high-speedICs

This paper presents 40-Gbit/s time division multiplexing (TDM) transmission technologies based on 0.1-μm-gate-length InP high electron mobility transistor IC's and a scheme for upgrading toward a terabit-per-second capacity system. A 40-Gbit/s, 300-km, in-line transmission experiment and a dispersion-tolerant 40-Gbit/s duobinary transmission experiment are described as 40-Gbit/s single carrier system applications on dispersion-shifted fiber. An ultra-high-speed receiver configuration using a high-output-power photodiode is introduced to realize fully electrical receiver operation beyond 40 Gbit/s. The high-sensitivity operation of the optical receiver (-27.6 dBm@BER=10^-9) is demonstrated at a data bit rate of 50 Gbit/s for the first time using a unitraveling carrier photodiode. A dense wavelength division multiplexing (DWDM) system operating up to terabits per second can be easily realized on a zero-dispersion flattened transmission line using ultra-high speed TDM channels of 40 Gbit/s and beyond. An experiment demonstrates 1.04-Tbit/s DWDM transmission based on 40-Gbit/s TDM channels with high optical spectrum density (0.4 bit/s/Hz) without dispersion compensation     

A Novel Scheme for Seamless Integration of ROF With Centralized Lightwave OFDM-WDM-PON System

We have experimentally demonstrated a novel transmission system for seamless integration of ROF with centralized lightwave OFDM-WDM-PON based on an integrated external modulator. At the one of two arms of the integrated external modulator, the optical carrier suppression (OCS) is realized to generate 40–GHz optical millimeter-wave (mm-wave) and up-converted baseband data signal as wireless signal. In another arm of the integrated external modulator, 16 quadrature amplitude modulation intensity-modulated OFDM signals at 10 Gbit/s are used for downstream transmission as wired signal based on double sideband modulation. By using one intensity modulator (IM), the downstream RF OFDM signal is remodulated for upstream on–off keying (OOK) data at 2.5 Gbit/s because of its downstream RZ shape waveform. The 10-Gbit/s wired signal, 2.5-Gbit/s wireless signal, and 2.5-Gbit/s upstream signal have been transmitted over 20-km single mode fiber (SMF) successfully.      

Field Trial of 640-Gbit/s-Throughput, Granularity-Flexible Optical Network Using Packet-Selective ROADM Prototype

Reconfigurable optical add/drop multiplexers (ROADMs) are able to provide flexible wavelength path provisioning in wavelength division multiplexing (WDM) networks. However, the capability of conventional ROADMs is limited to handling wavelength paths, and it does not support fine granularity in add/drop multiplexing of packets. Recently, we have proposed and demonstrated a packet-selective ROADM that combines an acoustooptic wavelength-tunable filter (AOTF) and an optical packet ADM (PADM) using optical code label processing. It provides more efficient utilization of wavelengths than conventional ROADMs. However, the bit rate of the demonstration was limited up to 10 Gbit/s. In this paper, we newly develop a label-selectivity-enhanced optical en/decoder, which allows the optical label recognition with 40-Gbit/s nonreturn-to-zero (NRZ) data packets, and a wide pass-band AOTF for 40-Gbit/s signals. Furthermore, we develop 640-Gbit/s throughput, packet-selective ROADM prototype, and demonstrate a field trial of granularity-flexible 3-node optical network over 173 km. error-free packet ADMs (error rate of under 10^-12) for all 16-wavelength channels at all nodes are obtained.     

An 18-Mb, 12.3-GB/s CMOS pipeline-burst cache SRAM with 1.54Gb/s/pin

An 18-Mbit CMOS pipeline-burst cache SRAM achieves a 12.3-Gbyte/s data transfer rate with 1.54-Gbit/s/pin I/O's. The SRAM is fabricated on a 0.18-μm CMOS technology. The 14.3×14.6-mm² SRAM chip uses a 5.59-μm², six-transistor cell. Circuit techniques used for achieving high bandwidth include fully self-timed array architecture, segmented hierarchical sensing with separated global read/write bitlines in different metal layers, a high-speed data-capture technique, a reduced-swing output buffer, and a high-sensitivity, high-bandwidth input buffer     

640-Gbit/s Data Transmission and Clock Recovery Using an Ultrafast Periodically Poled Lithium Niobate Device

This paper presents the first demonstration of the use of a periodically poled lithium niobate device for signal processing at 640 Gbit/s. Clock recovery is performed successfully using the lithium niobate device, and the clock signal is used to control a nonlinear fiber-based demultiplexer. The full 640-Gbit/s system gives error-free performance with no pattern dependence and there is less than 1-dB power penalty after 50-km fiber transmission.      

The fabrication and performance of long lengths of silica core fiber

Three hundred kilometers of single-mode fiber exhibiting median optical losses of 0.19 dB/km at 1.57 μm have been fabricated from preforms made by a high-rate Modified Chemical Vapor Deposition (MCVD) process. A new fiber design [1] was utilized which minimizes Rayleigh scattering loss by reducing the amount of dopants in the core. Milestone systems experiments incorporating this fiber have already demonstrated 420-Mbit transmission through 203 km [2], 2-Gbit transmission through 130 km [3], 1.37 Tbit km/s using 10 wavelength division multiplexed lasers [4], 4-Gbit through 102 km using a novel electronic multiplexer/demultiplexer [5], and 4 Gbit through 117 km using a Ti:LiNbO3external modulator [6]. Additionally, very low induced losses from hydrogen and radiation are reported.     

Toward High-Speed 40-Gbit/s Transponders

Today a 40-Gbit/s data rate is agreed by major optical telecommunication players as the next step in the network evolution, with an actual deployment foreseen in the 2007-2008 timeframe. R&D activities on technologies for 40-Gbit/s products are currently active but the path to 40-Gbit/s transponders is not yet fully settled. In this paper, we review the different component technologies currently considered for the actual development and the implementation of future 40-Gbit/s transponders. Dedicated paragraphs are devoted to electronic ICs and electrooptical devices, along with considerations on the technical solutions ensuring suitable interconnections or integration of the different components. Such advanced transponders should be compliant with the requirements of the different segments of the optical transport market. Solutions derived from choices made at lower data rates are projected for the shortest transmission paths, based on conventional nonreturn to zero modulation. In the peculiar case of long-haul transmission, signal distortion resulting from fiber propagation impairments calls for the generation of alternative modulation formats at the transmitter side and the potential need for electronic processing at the receiver side. This obviously has a clear impact on both the transponder design and the individual components features. Finally, recent advances in the field of innovative "all-optical" transponders implementing optical regeneration are also reported.     

Very-high-speed InP/InGaAs HBT ICs for optical transmission systems

High-speed ICs for 20-40-Gbit/s time-division multiplexing (TDM) optical transmission systems have been designed and fabricated by using InP/InGaAs heterojunction-bipolar-transistor (HBT) technology. This paper describes four analog ICs and four digital ICs: a five-section cascode distributed amplifier with a gain of 9.5 dB and a bandwidth of 50 GHz, a three-section single-end-to-differential converter with a bandwidth of 40 GHz, a cascode differential amplifier with a gain of 10.5 dB and a bandwidth of 64 GHz, a preamplifier with a gain of 41.9 dBΩ and a bandwidth of 39 GHz, a modulator driver with an output voltage swing of 3.2 V peak-to-peak and rise and fall times of 16 and 15 ps, a 40-Gbit/s selector, a 20-Gbit/s D-type flip-flop, and a static frequency divider with an operating range of 2.0-44.0 GHz. All the ICs were measured with on-wafer RF probes     

A 39-to-45-Gbit/s multi-data-rate clock and data recovery circuit with a robust lock detector

We describe a 40-Gbit/s-class clock and data recovery (CDR) circuit with an extremely wide pull-in range. A Darlington-type voltage-controlled oscillator (VCO) is newly designed to cover the STM-256/OC-768 full-rate-clock frequencies with a wide frequency margin. We also describe a new lock detector using an exclusive-NOR gate. The CDR IC was fabricated using InP/InGaAs HBTs. Error-free operation and wide eye opening were confirmed for 40-, 43-, and 45-Gbit/s PRBS with a word length of 2/sup 31/ - 1. We attached a frequency search and phase control (FSPC) circuit to the chip as a new frequency acquisition aid, and this allows the CDR circuit to pull in throughout a 39-45-Gbit/s range. The peak-to-peak and rms jitter of the recovered clock were 3.6 and 0.48 ps, respectively.     

A 40-Gbit/s superdynamic decision IC fabricated with 0.12-μmGaAs MESFET's

This paper describes a 4O-Gbit/s decision integrated circuit (IC) fabricated with 0.12-μm gate length GaAs metal-semiconductor field-effect transistors (MESFET's). A superdynamic flip-flop circuit and a wide-band amplifier were applied in order to attain 40-Gbit/s operation. A conventional static decision IC was also fabricated for comparison. The dynamic decision IC operated up to 40 Gbit/s, which is twice as fast as the conventional static decision IC. Error-free 40-Gbit/s operation is the fastest among GaAs MESFET decision IC's     

Evaluation of Sensitivity of the Digital Coherent Receiver

In this paper, we investigate the sensitivity of the digital coherent receiver both theoretically and experimentally. The receiver sensitivity close to the shot-noise limit is demonstrated in the 10-Gbit/s binary phase-shift keying system with the help of a low-noise optical preamplifier. We also introduce polarization diversity into our receiver. Maximal-ratio polarization combining in the digital domain makes the receiver sensitivity independent of the state of polarization of the incoming signal without power penalty.      

A 3.125-Gbit/s Parallel Optical Receiver in 0.13-μm CMOS With Direct Crosstalk Power Penalty Measurement Capability

We introduce a new method to measure the crosstalk power penalty in an arrayed environment by using an on-chip pseudorandom-bit-sequence generator to drive the aggressors. The proposed method is implemented in a three-channel 3.125-Gbit/s/ ch parallel receiver. Experimental results are presented including measurements of bit-error rate and crosstalk power penalty for 2.5and 3.125-Gbit/s operations. The measured crosstalk power penalty is less than 1 dB at both data rates. The test chip was designed in a standard 0.13-mum CMOS process     

160-Gbit/s clock recovery using an electro-absorption modulator and 40-Gbit/s ETDM demultiplexer

A 10-GHz clock recovery from a 16×10-Gbit/s optical time-division-multiplexed (OTDM) data stream is experimentally demonstrated using an electro-absorption modulator and 40-Gbit/s electric time-division-multiplexed (ETDM) demultiplexer. The recovered clock signal exhibits excellent stability, with root square (RMS) jitter of 328 and 345 fs corresponding to back-to-back and transmission over 100 km, respectively.     

Long-distance gigabit-range optical fiber transmission experiments employing DFB-LD's and InGaAs-APD's

High-speed and long-distance transmission characteristics have been examined at 1.2, 2, and 4 Gbit/s, employing mesa structure DFB-DC-PBH LD transmitters and planar InGaAs APD receivers. High receiver sensitivities, -40 dBm at 1.2 Gbit/s, -37.4 dBm at 2 Gbit/s and -32.4 dBm at 4 Gbit/s, have been obtained employing high-speed and low noise InGaAs APD/FET receiver circuits. Long-span transmissions, 1.2-Gbit/s 170-km, 2-Gbit/s 141-km, and 4- Gbit/s 120-km at 1.55 μm, and 4-Gbit/s 74-km at 1.3 μm, have been performed. Power penalties caused by the LD wavelength chirping in the 1.5- μm wavelength region and error rate flooring caused by the LD side-mode oscillation in the 1.3- μm wavelength region are discussed. The transmission length is limited not only by the DFB LD wavelength chirping but also by the two-mode oscillation, which was observed at the pulse leading edge when LD bias current was near the threshold current. From the 1.3 μm wavelength 4-Gbit/s experiment, it was found that the pattern effect of the side-mode oscillation caused the error rate floor, when the LD bias current is set near the threshold current, and that the error rate floor disappeared when the bias current is set slightly above the threshold.     

Gigabit-per-second dual-gate MESFET switching and multiplexer operation for high-speed fiber-optic systems

The operation of dual-gate GaAs MESFET's in gigabit-per-second switching applications for high-speed fiber-optic systems is investigated, and a full nonlinear modeling procedure is presented for general switching simulations. The model is characterized via a new and efficient technique which only requires two-ports-parameter measurements to determine the nonlinear element variations. Circuit simulations implemented on program SPICE 2 have been applied to evaluate the transient switching response of dual-gate MESFET's in several circuits involving 1-Gbit/s pulse conversion and synchronization, pulse-width reduction and 2-Gbit/s multiplexing, and results show good agreement between predicted and experimental switching waveforms.     

High-speed high-power 1.3-µm InGaAsP/InP surface-emitting LED's for short-haul wide-bandwidth optical-fiber communications

High-speed high-power double-heterostructure 1.3-µm InGaAsP/InP LED's have been developed for use in short-haul wide-bandwidth fiber-optics systems. At 150-mA dc, devices typically launch - 11.7 dBm into a 62-µm core graded index (GI) fiber. Optical bandwidth is typically 690 MHz with a 50-mA prebias. Modulation capability was demonstrated at 1-Gbit/s NRZ with - 15.7 dBm of peak power launched into the fiber. Rise and fall times of 340 and 780 ps, respectively, were achieved. Reliability data indicates a median life of ∼ 10⁸h for anticipated operating conditions.     

40-Gbit/s ETDM Channel Technologies for Optical Transport Network

We review recent progress and the future of 40-Gbit/s electrical time division multiplexed (ETDM) channel technologies for the optical transport network (OTN), where optical technologies, including high-speed ETDM channel transmission and wavelength division multiplexing (WDM), dramatically enhance network flexibility while reducing transport node cost as well as transmission cost. The 40 Gbit/s channel has recently been specified to be one of the optical channels in OTN. A new digital frame for the optical channels [optical channel transport unit (OTU)] was introduced for the network node interface of OTN in International Telecommunication Union-Telecommunication (ITU-T) standard. The specified data bit rates are 2.7 Gbit/s (OTU1), 10.7 Gbit/s (OTU2), and 43.0 Gbit/s (OTU3). These OTU frames have additional overhead bytes that support the network management overhead for OTN and out-of-band forward error correcting (FEC) codes. We discuss the feasibility and impact of the OTU3 frame in terrestrial networks. A newly developed 43-Gbit/s OTN line terminal prototype that confirms the feasibility of 43-Gbit/s ETDM channels and the OTU3 management capability is discussed. As a guide to the evolution of OTN, modulation formats for 43Gbit/s-based DWDM transmission are described for long distance application with the total capacity over one terabit per second.     

A four-channel 3.125-Gb/s/ch CMOS serial-link transceiver with a mixed-mode adaptive equalizer

This work presents a quad-channel serial-link transceiver providing a maximum full duplex raw data rate of 12.5Gb/s for a single 10-Gbit eXtended Attachment Unit Interface (XAUI) in a standard 0.18-/spl mu/m CMOS technology. To achieve low bit-error rate (BER) and high-speed operation, a mixed-mode least-mean-square (LMS) adaptive equalizer and a low-jitter delay-immune clock data recovery (CDR) circuit are used. The transceiver achieves BER lower than <4.5/spl times/10/sup -15/ while its transmitted data and recovered clock have a low jitter of 46 and 64 ps in peak-to-peak, respectively. The chip consumes 178 mW per each channel at 3.125-Gb/s/ch full duplex (TX/RX simultaneous) data rate from 1.8-V power supply.