A Comparative Study of Dopant-Segregated Schottky and Raised Source/Drain Double-Gate MOSFETs

The performance of symmetric double-gate MOSFETs with dopant-segregated Schottky (DSS) source/drain (S/D) regions is investigated through a TCAD modeling study and compared to the performance of raised S/D (RSD) MOSFETs. It is shown that, while the doped extension region adjacent to the S/D Schottky barrier (SB) improves drive current by shrinking the SB, it is fundamentally limited by its dual role as a heavily doped S/D contact region to improve drive current and as a more lightly doped S/D extension region to reduce BTBT leakage. This restricts the design space for meeting low-standby-power leakage specifications, and so, the RSD structure ends up prevailing both in terms of leakage design space and on-state performance. For high-performance (HP) design, where the higher leakage specification permits heavier extension doping, the performances of optimized DSS and RSD MOSFETs are shown to be very similar. Thus, the optimal S/D design for HP is more likely to be decided by practical considerations such as process integration.     

An analytical compact model for Schottky-barrier double gate MOSFETs

An analytical and explicit compact model for undoped symmetrical silicon double gate MOSFETs (DGMOSFETs) with Schottky barrier (SB) source and drain is presented. The SB MOSFET can be studied as a traditional MOSFET where the doped source/drain regions have been replaced by a metal contact. Due to particular features of this new structure, the main transport mechanisms of these devices differ from those found in traditional MOSFETs. The model developed in this paper is based on a previously published DGMOSFET model which has been extended to include the characteristic tunneling transport mechanisms of SB MOSFET.The proposed model reproduces the well known ambipolar behavior found in SB MOSFET for a wide range of metal source and drain contacts specified through different values of their work function. The model has been validated with numerical data obtained by means of the 2D ATLAS simulator, where a SB DGMOSFET structure has been defined and characterized in order to obtain the transfer and output characteristics for several bias configurations. Devices with two channel lengths (2 μm and 3 μm) has been simulated and modeled.     

High-Frequency Noise of Modern MOSFETs: Compact Modeling and Measurement Issues

Compact modeling of the most important high-frequency (HF) noise sources of the MOSFET is presented in this paper, along with challenges in noise measurement and deembedding of future CMOS technologies. Several channel thermal noise models are reviewed and their ability to predict the channel noise of extremely small devices is discussed. The impact of technology scaling on noise performance of MOSFETs is also investigated by means of analytical expressions. It is shown that the gate tunneling current has a significant impact on MOSFETs noise parameters, especially at lower frequencies. Limitations of some commonly used noise models in predicting the HF noise parameters of modern MOSFETs are addressed and methods to alleviate some of the limitations are discussed.     

Device and technology evolution for Si-based RF integrated circuits

The relationships between device feature size and device performance figures of merit (FoMs) are more complex for radio frequency (RF) applications than for digital applications. Using the devices in the key circuit blocks for typical RF transceivers, we review and give trends for the FoMs that characterize active and passive RF devices. These FoMs include transit frequency at unity current gain f/sub T/, maximum frequency of oscillation f/sub MAX/ at unit power gain, noise, breakdown voltage, capacitor density, varactor and inductor quality, and the like. We use the specifications for wireless communications systems to show how different Si-based devices may achieve acceptable FoMs. We focus on Si complementary metal-oxide-semiconductor (CMOS), Si Bipolar CMOS, and Si bipolar devices, including SiGe heterojunction bipolar transistors, RF devices, and integrated circuits (ICs). We analyze trends in the FoMs for Si-based RF devices and ICs and show how these trends relate to the technology nodes of the 2003 International Technology Roadmap for Semiconductors. We also compare FoMs for the best reported performance of research devices and for the performance of devices manufactured in high volumes, typically more than 10 000 devices. Certain commercial equipment, instruments, or materials are identified in this article to specify adequately the experimental or theoretical procedures. Such identification does not imply recommendation by any of the host institutions of the authors, nor does it imply that the equipment or materials are necessarily the best available for the intended purpose.     

Figure of merit for narrowband,wideband and multiband LNAs

In software defined radio, the same radio front end is used to accommodate different wireless standards operating in different frequency bands. The use of wideband or multiband low noise amplifiers (LNAs) is mandatory in such situations. There are several figures of merit (FoMs) proposed for narrowband LNAs. These FoMs are modified for wideband/multiband LNAs just by the inclusion of 3?dB bandwidth, and designers tend to use the one that favours their own design. In this article, a review of the existing FoMs for narrowband LNAs is presented. Based on this analysis, we propose two different FoMs for fair comparison of improvement in LNA parameters due to complementary metal oxide semiconductor (CMOS) technology advancement and circuit optimisation (irrespective of transistor technology), separately. The empirical technology scaling factor for gain, noise figure (NF), f _T and linearity is used to differentiate between these FoMs for different types of LNAs.     

High-frequency small signal AC and noise modeling of MOSFETs for RFIC design

High-frequency (HF) AC and noise modeling of MOSFETs for radio frequency (RF) integrated circuit (IC) design is discussed. A subcircuit RF model incorporating the HF effects of parasitics is presented. This model is compared with the measured data for both y parameter and f_T characteristics. Good model accuracy is achieved against measurements for a 0.25 μm RF CMOS technology. The HF noise predictivity of the model is also examined with measured data. Furthermore, a methodology to extract the channel thermal noise of MOSFETs from HF noise measurements is presented. By using the extracted channel thermal noise, any thermal noise models can be verified directly. Several noise models including the RF model discussed in this paper have been examined, and the results show that the RF model can predict the channel thermal noise better than the other models     

MOSFET modeling for RF IC design

High-frequency (HF) modeling of MOSFETs for radio-frequency (RF) integrated circuit (IC) design is discussed. Modeling of the intrinsic device and the extrinsic components is discussed by accounting for important physical effects at both dc and HF. The concepts of equivalent circuits representing both intrinsic and extrinsic components in a MOSFET are analyzed to obtain a physics-based RF model. The procedures of the HF model parameter extraction are also developed. A subcircuit RF model based on the discussed approaches can be developed with good model accuracy. Further, noise modeling is discussed by analyzing the theoretical and experimental results in HF noise modeling. Analytical calculation of the noise sources has been discussed to understand the noise characteristics, including induced gate noise. The distortion behavior of MOSFET and modeling are also discussed. The fact that a MOSFET has much higher "low-frequency limit" is useful for designers and modelers to validate the distortion of a MOSFET model for RF application. An RF model could well predict the distortion behavior of MOSFETs if it can accurately describe both dc and ac small-signal characteristics with proper parameter extraction.     

High-frequency characterization and modeling of distortion behavior of MOSFETs for RF IC design

High frequency (HF) distortion of MOSFETs has been characterized at different frequencies and bias conditions with a single tone measurement system. The results show that a MOSFET has much higher "low frequency limit" (LFL) than a bipolar transistor with similar critical dimensions, implying that the HF distortion characteristics of MOSFETs operating at a frequency lower than LFL is dictated by its low-frequency behavior. This discovery is useful for designers and modelers to validate the distortion of a MOSFET model for RF application. It has also been found that the second harmonic P/sub f2/ reaches to its minimum as f/sub T/ peaks, due to a similar nonlinearity cancellation as in bipolar transistors. Furthermore, the measured data shows fairly constant distortion characteristics over a wide range of drain biases as the device operates in the saturation region. Simulation with a BSIM3v3-based sub-circuit model demonstrates that the distortion behavior of MOSFETs can be well predicted by an RF model if it can accurately describe both dc and ac characteristics with proper parameter extraction. Sensitivity of the distortion on various physical effects, such as the mobility degradation, velocity saturation, channel length modulation, and drain-induced barrier lowering, are also studied to provide insights of the key nonlinearity variation contributors from a practical modeling point of view.     

A wavelet-based heart rate variability analysis for the study of nonsustained ventricular tachycardia

It has been reported that the sympathovagal balance (SB) can be quantified by heart rate (HR) via the low-frequency (LF) to high-frequency (HF) spectral power ratio LF/HF. In this paper, an investigation of the relationship between the autonomic nervous system (ANS) and non-sustained ventricular tachycardia (NSVT) is presented. A wavelet transform (WT)-based approach for short-time heart rate variability (HRV) assessments is proposed for this aspect of analysis. The study was conducted on an RR-interval database consisting of 87 NSVT, 61 ischemic and five normal episodes. First, instantaneous SB estimates were generated by the proposed method. Then, waveforms of the WT-based SB evolutions were quantitatively examined. Numerical results showed that while a majority of SB waveforms (about 71%) derived from the non-NSVT population (i.e., ischemic and normal) appeared to come near oscillating with certain fixed levels, approximate 75% of SB evolutions underwent significantly rapid increases prior to the onset of NSVT, suggesting that an abrupt sympathovagal imbalance might partly account for the occurrence of NSVT.     

Carbon Nanotube Field-Effect Transistors for High-Performance Digital Circuits—DC Analysis and Modeling Toward Optimum Transistor Structure

Scaling of silicon technology continues while a research has started in other novel materials for future technology generations beyond year 2015. Carbon nanotubes (CNTs) with their excellent carrier mobility are a promising candidate. The authors investigated different CNT-based field effect transistors (CNFETs) for an optimal switch. Schottky-barrier (SB) CNFETs, MOS CNFETs, and state-of-the-art Si MOSFETs were systematically compared from a circuit/system design perspective. The authors have performed a dc analysis and determined how noise margin and voltage swing vary as a function of tube diameter and power-supply voltage. The dc analysis of single-tube SB CNFET transistors revealed that the optimum CNT diameter for achieving the best I_ON-to-I_OFF ratio while maintaining a good noise margin is about 1 to 1.5 nm. Despite several serious technological barriers and challenges, CNTs show a potential for future high-performance devices as they are being researched     

On the performance of single-gated ultrathin-body SOI Schottky-barrier MOSFETs

The authors study the dependence of the performance of silicon-on-insulator (SOI) Schottky-barrier (SB) MOSFETs on the SOI body thickness and show a performance improvement for decreasing SOI thickness. The inverse subthreshold slopes S extracted from the experiments are compared with simulations and an analytical approximation. Excellent agreement between experiment, simulation, and analytical approximation is found, which shows that S scales approximately as the square root of the gate oxide and the SOI thickness. In addition, the authors study the impact of the SOI thickness on the variation of the threshold voltage V/sub th/ of SOI SB-MOSFETs and find a nonmonotonic behavior of V/sub th/. The results show that to avoid large threshold voltage variations and achieve high-performance devices, the gate oxide thickness should be as small as possible, and the SOI thickness should be /spl sim/ 3 nm.     

Improved Carrier Injection in Ultrathin-Body SOI Schottky-Barrier MOSFETs

The impact of the gate oxide and the silicon-on-insulator (SOI) body thickness on the electrical performance of SOI Schottky-barrier (SB) MOSFETs with fully nickel silicided source and drain contacts is experimentally investigated. The subthreshold swing S is extracted from the experimental data and serves as a measure for the carrier injection through the SBs. It is shown that decreasing the gate oxide and body thickness allows to strongly increase the carrier injection and hence, a significantly improved on-state of SB-MOSFETs can be obtained     

Computational Study on the Performance of Multiple-Gate Nanowire Schottky-Barrier MOSFETs

Quantum simulations of multiple-gate nanowire Schottky-barrier (SB) MOSFETs in the ballistic transport regime have been performed by self-consistently solving the nonequilibrium Green's function transport equation and the Poisson's equation. The device characteristics have been examined as the channel length of the nanowire SB-MOSFETs was aggressively reduced, and their scaling behaviors were compared to planar SB devices and also to devices with doped source/drain. The enhancement of the device performance due to the multiple-gate effects has been assessed quantitatively. A limited improvement of the off-state performance has been observed, whereas ON-state currents increase significantly despite the size quantization effect.     

High-Quality Schottky Contacts for Limiting Leakage Currents in Ge-Based Schottky Barrier MOSFETs

Schottky barrier (SB) Ge channel MOSFETs suffer from high drain-body leakage at the required elevated substrate doping concentrations to suppress source–drain leakage. Here, we show that electrodeposited Ni–Ge and NiGe/Ge Schottky diodes on highly doped Ge show low off current, which might make them suitable for SB p-MOSFETs. The Schottky diodes showed rectification of up to five orders of magnitude. At low forward biases, the overlap of the forward current density curves for the as-deposited Ni/n-Ge and NiGe/n-Ge Schottky diodes indicates Fermi-level pinning in the Ge bandgap. The SB height for electrons remains virtually constant at 0.52 eV (indicating a hole barrier height of 0.14 eV) under various annealing temperatures. The series resistance decreases with increasing annealing temperature in agreement with four-point probe measurements indicating the lower specific resistance of NiGe as compared to Ni, which is crucial for high drive current in SB p-MOSFETs. We show by numerical simulation that by incorporating such high-quality Schottky diodes in the source/drain of a Ge channel PMOS, a highly doped substrate could be used to minimize the source-to-drain subthreshold leakage current.      

On the high-frequency characteristics of substrate resistance in RF MOSFETs

The high-frequency (HF) behavior of substrate components in MOSFETs is studied at different bias conditions for a 0.35 /spl mu/m BICMOS technology in the frequency range up to 10 GHz. It was found that the observed strong bias dependence of the real part of admittance y/sub 22/, Re{y/sub 22/}, is mainly contributed by the channel conductance. A very weak bias dependence of substrate resistance was found after deembedding the measured y/sub 22/ to remove the influence of channel resistance R/sub ds/ and gate-to-drain capacitance C/sub gd/. The results are key to the understanding and modeling of the HF behavior of MOSFET substrate components for RF IC design.     

Carbon Nanotube Field-Effect Transistors for High-Performance Digital Circuits—Transient Analysis, Parasitics, and Scalability

Silicon-based CMOS is the dominant technology choice for high-performance digital circuits. While silicon technology continues to scale, researchers are investigating other novel materials, structures, and devices to introduce into future technology generations, if necessary, to extend Moore's law. Carbon nanotubes (CNTs) have been explored as a possibility due to their excellent carrier mobility. The authors studied and compared different carbon-nanotube-based field-effect transistors (CNFETs) including Schottky-barrier (SB) CNFETs, MOS CNFETs, and state-of-the-art Si MOSFETs systematically from a circuit/system design perspective. Parasitics play a major role in the performance of CNT-based circuits. The data in this paper show that CNFET design's performance is limited by the gate overlap capacitance and the quality of nanocontacts to these promising transistors. Transient analysis of high-performing single-tube SB CNFET transistors and circuits revealed that 1-1.5 nm is the optimum CNT diameter resulting in best power-performance tradeoff for high-speed digital applications. The authors determined optimal spacing and layout of CNT arrays, an architecture that is most likely required for driving capacitive loads and interconnects in digital applications. CNTs have an intrinsic capability to improve performance, but many serious technological and experimental challenges remain that require more research to harvest their potential     

Complimentary single-electron/hole action of nanoscale SOI CMOS transistors

We propose a new device structure for room-temperature single-electron/hole transistors based on nanosize narrow-width fully depleted silicon-on-insulator (SOI) CMOS transistors. The floating body of SOI MOSFETs can become a Coulomb island, whose single charging energy is more than 30 meV, as the gate length and width of MOSFETs is less than 10 nm. As SOI MOSFETs are biased at accumulation, single-electron, or hole tunnels, are sent, one by one, from the source to the floating body and then to the drain via Zener tunneling process. N-channel SOI MOSFETs can have the functions of single-electron transistors (n-SETs) while p-channel MOSFETs can have the functions of single-hole transistors (p-SETs). SOI MOSFETs still behave as typical MOSFETs when biased at inversion. There is a gate voltage margin of 0.9 V to separate Coulomb blockade oscillations from CMOS normal operation.     

Impact of switching frequencies on the TID response of SiC power MOSFETs

Different switching frequencies are required when SiC metal-oxide-semiconductor field-effect transistors(MOSFETs)are switching in a space environment.In this study,the total ionizing dose(TID)responses of SiC power MOSFETs are investig-ated under different switching frequencies from 1 kHz to 10 MHz.A significant shift was observed in the threshold voltage as the frequency increased,which resulted in premature failure of the drain-source breakdown voltage and drain-source leakage current.The degradation is attributed to the high activation and low recovery rates of traps at high frequencies.The results of this study suggest that a targeted TID irradiation test evaluation method can be developed according to the actual switching fre-quency of SiC power MOSFETs.     

A method for the prediction of hot-carrier lifetime in floating SOINMOSFETs

A concept was presented for the prediction of the device lifetimes for the hot-carrier effect (hot-carrier lifetimes) in floating SOI MOSFETs. The concept is that hot-carrier lifetimes in floating SOI MOSFETs can be predicted by estimating the hole current. In order to verify the validity of this concept, the hole current was investigated using device simulation. The results showed that the ratio of the hole current to the drain current in a floating-body SOI MOSFET is approximately equal to the ratio of substrate current to drain current in a body-tied one. Based on this fact, a method for accurately predicting the hot-carrier lifetime in floating-body SOI MOSFETs was proposed. The hot-carrier lifetime predicted with this method agreed well with the experimental results. This study showed that only the drain current difference between floating and body-tied structures results in lifetime differences, and there is no special effect on hot-carrier degradation in floating SOI MOSFETs. In this prediction, therefore, floating SOI MOSFETs can be treated in the same way as bulk MOSFETs. Hot-carrier lifetimes in floating SOI MOSFETs can be predicted using the hole current, while substrate currents are used in bulk MOSFETs     

Frequency-dependent resistive and capacitive components in RFMOSFETs

It is found from measured high frequency (HF) S-parameter data that the extracted effective gate sheet resistance (R_gsh), effective gate unit-area capacitance (C_{gg, unit}), and transconductance (G_m) in radio-frequency (RF) MOSFETs show strong frequency dependency when the device operates at frequencies higher than some critical frequency. As frequency increases, R_gsh increases but C_{gg, unit} and G_m decrease. This behavior is different from what we have observed at low or medium frequencies, at which these components are constant over a frequency range. This phenomenon has been observed in MOSFETs with L_f longer than 0.35 μm at frequencies higher than 1 GHz, and becomes more serious as L_f becomes longer and the frequency higher. This behavior can be explained by a MOSFET model considering the Non-Quasi-Static (NQS) effect. Simulation results show that an RF model based on BSIM3v3 with the NQS effect describes well the behaviors of both real and imaginary parts of Y₂₁ of the device with strong NQS effect even though its fitting to Y₁₁ needs to be improved further