A unified diode model for circuit simulation

A new commercially available diode model is described. This unified model is capable of simulating the widest range of diode technologies of any presently available. The emphasis of this paper is on describing the model's extensive features and flexibility in the different domains of operation and is of particular interest in power applications     

A peeling algorithm for extraction of the HBT small-signal equivalent circuit

Direct extraction is the most accurate method for the determination of equivalent-circuits of heterojunction bipolar transistors (HBTs). The method is based on first determining the parasitic elements and then the intrinsic elements analytically. The accuracy and robustness of the whole algorithm therefore is determined by the quality of the extraction of the extrinsic elements. This paper focuses on a new extraction method for the extrinsic capacitances which have proven to be the main source of uncertainty compared to the other extrinsic parameters. Concerning the intrinsic parameters, all the elements are extracted using exact closed-form equations, including exact expressions for the base-collector capacitances, which model the distributed nature of the base. The expressions for the base-collector capacitances are valid for both the hybrid-/spl pi/ and the physics-based T-topology equivalent circuits. Extraction results for InP HBT devices on measured S-parameters up to 100 GHz demonstrate good modeling accuracy.     

A transaction-based unified architecture for simulation and emulation

The availability of millions of transistors on a single chip has allowed the creation of complex on-chip systems. The functional verification of such systems has become a challenge. Simulation run times are increasing, and emulation is now a necessity. Creating separate verification environments for simulation and emulation slows the design cycle and it requires additional human efforts. This paper describes a layered architecture suitable for both simulation and emulation. The architecture uses transactions for communication and synchronization between the driving environment (DE) and the device under test (DUT). Transactions provide synchronization only as needed and cycle and event-based synchronization common in emulators. The result is more efficient development of the DE and 100% portability when moving from simulation to emulation. We give an overview of our layered architecture and describe its implementation. Our results show that, by using emulation, the register-transfer level (RTL) implementation of an industrial design can be verified in the same amount of time it takes to run a C-based simulation. We also show two orders of magnitude speeds up over simulations of C and RTL through a programming language interface     

A unified approach for fault simulation of linear mixed-signal circuits

The rapidly evolving role of analog signal processing has spawned off a variety of mixed-signal circuit applications. The integration of the analog and digital circuits has created a lot of concerns in testing these devices. This paper presents an efficient unified fault simulation platform for mixed-signal circuits while accounting for the imprecision in analog signals. While the classical stuck-at fault model is used for the digital part, faults in the analog circuit cover catastrophic as well as parametric defects in the passive and active components. A unified framework is achieved by combining a discretized representation of the analog circuit with the Z-domain representation of the digital part. Due to the imprecise nature of analog signals, an arithmetic distance based fault detection criterion and a statistical measure of digital fault coverage are proposed.This research was supported by the National Science Foundation under grant MIP-9222481.     

A unified fast recursive algorithm for data shuffling in variousorders

Data shuffling in a particular order is frequently required in signal processing applications. The authors present fast recursive algorithms, of order O(N), for shuffling a data sequence in various orders, e.g. bit reversed, Gray code, and other related orders, under a unified framework. These algorithms are computationally efficient in that every permutation index is essentially computed by a single logical or arithmetic operation between a previous index and a proper offset. The proposed algorithms can be used for the fast Fourier transform, fast Hartley transform, and mutual conversion among three typical forms of the Walsh transform     

A small-signal calculation for one-dimensional transistors

A computation method to obtain an exact small-signal solution of a one-dimensional transistor model for high-frequency operation is presented under the assumption of negligible bulk recombination effect. Basis for the small-signal calculation is 1) a dc solution at the operating point under consideration, 2) trial potentials (electrostatic potential and quasi-Fermi potentials for electrons and holes, respectively), and 3) frequency. A scheme for iterative computation can be constructed in a manner similar to that for dc steady state given by Gummel. Discussions are made on conservation of the total currents, terminal currents relationship, as on a simplified method to obtain terminal characteristics. Some computation results will be demonstrated for potentials, carrier densities, current densities, and the current transfer factor. In the Appendix the relation between the exact solution and low-frequency treatment will be discussed.     

A new approach to the simulation of small-signal current gains ofpnpn structures

An approach to the mathematical simulation of small-signal current gains (alphas) versus frequency that respects Fulop's measuring procedure is proposed, using an arrangement close to the real measuring circuit. For this purpose, an exact 1-D mathematical model is used. The dependence of small-signal alphas on the anode current of a high power thyristor (GTO) was found to be in agreement with measurements for low anode-to-cathode voltage     

A unified simulation of Schottky and ohmic contacts

The Schottky contact is an important consideration in the development of semiconductor devices. This paper shows that a practical Schottky contact model is available for a unified device simulation of Schottky and ohmic contacts. The present model includes the thermionic emission at the metal/semiconductor interface and the spatially distributed tunneling calculated at each semiconductor around the interface. Simulation results of rectifying characteristics of Schottky barrier diodes (SBD's) and resistances under high impurity concentration conditions are reasonable, compared with measurements. As examples of application to actual devices, the influence of the contact resistance on salicided MOSFETs with source/drain extension and the immunity of Schottky barrier tunnel transistors (SBTTs) from the short-channel effect (SCE) are demonstrated     

A unified framework and algorithm for channel assignment in wireless networks

Channel assignment problems in the time, frequency and code domains have thus far been studied separately. Exploiting the similarity of constraints that characterize assignments within and across these domains, we introduce the first unified framework for the study of assignment problems. Our framework identifies eleven atomic constraints underlying most current and potential assignment problems, and characterizes a problem as a combination of these constraints. Based on this framework, we present a unified algorithm for efficient (T/F/C)DMA channel assignments to network nodes or to inter-nodal links in a (multihop) wireless network. The algorithm is parametrized to allow for tradeoff-selectable use as three different variants called RAND, MNF, and PMNF. We provide comprehensive theoretical analysis characterizing the worst-case performance of our algorithm for several classes of problems. In particular, we show that the assignments produced by the PMNF variant are proportional to the thickness of the network. For most typical multihop networks, the thickness can be bounded by a small constant, and hence this represents a significant theoretical result. We also experimentally study the relative performance of the variants for one node and one link assignment problem. We observe that the PMNF variant performs the best, and that a large percentage of unidirectional links is detrimental to the performance in general.     

A unified mobility model for analysis and simulation of mobile wireless networks

We propose a novel mobility model, named Semi-Markov Smooth (SMS) model, to characterize the smooth movement of mobile users in accordance with the physical law of motion in order to eliminate sharp turns, abrupt speed change and sudden stops exhibited by existing models. We formulate the smooth mobility model by a semi-Markov process to analyze the steady state properties of this model because the transition time between consecutive phases (states) has a discrete uniform distribution, instead of an exponential distribution. Through stochastic analysis, we prove that this model unifies many good features for analysis and simulations of mobile networks. First, it is smooth and steady because there is no speed decay problem for arbitrary starting speed, while maintaining uniform spatial node distribution regardless of node placement. Second, it can be easily and flexibly applied for simulating node mobility in wireless networks. It can also adapt to different network environments such as group mobility and geographic constraints. To demonstrate the impact of this model, we evaluate the effect of this model on distribution of relative speed, link lifetime between neighboring nodes, and average node degree by ns-2 simulations.

基于递推最小二乘算法的小信号检测

受到强干扰影响的小信号通常难于有效检测。在分析递推最小二乘算法(RLS)原理及其几种改进形式的基础上,采用自适应方法将已检测出的大信号与原混叠信号对消,降低大信号对小信号的遮蔽作用,再进行小信号的检测。最后通过仿真证明,该方法能够在较小失真的情况下,有效检测出被大调幅信号干扰下的小调频信号;同时分别比较了各种算法的优劣,得出基于可变遗忘因子的RLS(VFF-RLS)算法不仅具有较快的收敛速度,而且收敛之后具有很好的平稳性能。     

A non-quasi-static small-signal model for metal-semiconductor junction diodes

The quasi-static approximation, which assumes that free-carrier propagation delay in the semiconductor device is zero, is often used in device modeling. Consequently, the quasi-static model is adequate only for low-frequency excitations for which free-carrier propagation delay is very small compared to the variation of the excitations. This paper develops a non-quasi-static model suitable for metal-semiconductor junction diodes subjected to small-signal excitation. We show that the predictions of the non-quasi-static model agree more favourably with experimental data taken from Al---Si diodes than that of the quasi-static model, particularly when the frequency of the excitation is high.     

A mixed-signal pulse width modulator for portable SMPS applications

This paper presents a design for a mixed-signal pulse width modulator (MSPWM) integrated circuit that targets the digital control of high-frequency switched-mode DC–DC power supplies (SMPS). Previous designs consider digital pulse width modulators (DPWM) implementations that encounter important design issues, such as power consumption, non-linearity, layout dependency, trimming capability and temperature dependency. This work presents effective solutions, suitable for large-scale production of ICs, since it combines high-precision, high-linearity and temperature-independent standard analog circuits, which are commonly offered by the semiconductor industry, with the simplicity and reuse of digital PID compensation as input. The 8-bit prototype designed for a 0.18-μm CMOS process operates at switching frequency of 2 MHz, draws only 96.25 μA from a 1.8 V supply and takes 0.029 mm², including the non-overlapping control logic of SMPS power devices.     

A unified theory for frequency-domain simulation and sensitivityanalysis of linear and nonlinear circuits

The harmonic balance technique from nonlinear simulation is extended to nonlinear adjoint sensitivity analysis. This provides an efficient tool for the otherwise expensive but essential gradient calculations in design optimization. The hierarchical approach widely used for circuit simulation, is generalized to sensitivity analysis and to computing responses in any subnetwork at any level of the hierarchy. Important aspects of frequency-domain circuit computer-aided design (CAD) such as simulation and sensitivity analysis, linear and nonlinear circuits, hierarchical and nonhierarchical approaches, voltage and current excitations, or open- and short-circuit terminations are unified in this general framework. The theory provides a basis for the next generation of microwave CAD software. It takes advantage of mature techniques such as syntax-oriented hierarchical analysis, optimization, and yield-driven design to handle nonlinear as well as linear circuits. The sensitivity analysis approach has been verified by a MESFET mixer example, exhibiting a 90% saving of CPU time over the prevailing perturbation method     

A Monte Carlo simulation algorithm for finding MTBF

Prediction of mean time between failures (MTBF) is an important aspect of the initial stage of system development. It is often difficult to predict system MTBF during a given time since the component failure processes are extremely complex. The authors present a Monte Carlo simulation algorithm to calculate the MTBF during a given time of a binary coherent system. The algorithm requires the lifetime distributions of the components and the minimal path sets of the system. The MTBF for a specific time interval, e.g. a month or a year, can be estimated. If the component lifetime distributions are unknown, then a lower bound of system MTBF can be estimated by using known constant failure rates for each component     

Striving for small-signal stability

In this article, based on Bode's definition of return ratio with respect to a single controlled source, the loop-based two-port algorithm and device-based gain-nulling are proposed for small-signal stability analysis. These two algorithms are complementary in terms of applicability, and they produce accurate stability information for single-loop networks. After a brief primer on feedback and stability, we review Bode's feedback theory, where the return difference and return ratio concepts are applicable to general feedback configurations and avoid the necessity of identifying μ and β. Middlebrook's null double-injection technique, which provides a laboratory-based way to measure return ratio, is then discussed in the modern circuit analysis context; we then extend the unilateral feedback-model used in Middlebrook's approach to accommodate both normal-and reverse-loop transmission and characterize the return loop using a general two-port-analysis. This loop-based two-port algorithm determines the stability of a feedback network in which a critical wire can be located to break all return loops. The device-based gain-nulling algorithm is then discussed to evaluate the influence of the local return loops upon network stability. This algorithm determines the stability of a feedback network in which a controlled source can be nulled to render the network to be passive. Conditions under which these two algorithms can be applied are discussed