一种新的终止LDPC迭代译码算法

在传统的卫星广播系统中,信道纠错通常采用BCH码级联LDPC码的方案以达到良好的误码率性能,例如DVB-S2系统。作为内码的LDPC码通常采用迭代译码,且迭代次数较高才能实现比较好的系统性能。借助BCH级联LDPC的结构,文中提出了将BCH检错嵌套进LDPC每一次迭代译码过程中的新的迭代译码结构。仿真结果表明,新算法以较低的BCH码检错运算复杂度换取了LDPC码迭代次数的明显下降,从而极大降低了迭代译码总体复杂度和译码时延,且整体纠错性能与原始LDPC译码后BCH纠错的算法相比基本保持不变。     

基于SSCANL译码器的联合迭代检测译码算法

为了提升基于极化码的稀疏码多址接入（sparse code multiple access,SCMA）系统接收机性能,提出了基于简化软消除列表（simplify soft cancellation list,SSCANL）译码器的循环冗余校验（cyclic redundancy check,CRC）辅助联合迭代检测译码接收机方案。该方案中极化码译码器使用SSCANL译码算法,采用译码节点删除技术对软消除列表（soft cancellation list,SCANL）算法所需要的L次软消除译码（soft cancellation, SCAN）进行简化,通过近似删除冻结位节点,简化节点间软信息更新计算过程,从而降低译码算法的计算复杂度。仿真结果表明,SSCANL算法可获得与SCANL算法一致的性能,其计算复杂度与SCANL算法相比有所降低,码率越低,算法复杂度降低效果越好;且基于SSCANL译码器的CRC 辅助联合迭代检测译码接收机方案相较基于SCAN译码器的联合迭代检测译码（joint iterative detection and decoding based on SCAN decoder, JIDD-SCAN）方案、基于SCAN译码器的CRC辅助联合迭代检测译码（CRC aided joint iterative detection and decoding based on SCAN decoder,C-JIDD-SCAN）方案,在误码率为10^-4时,性能分别提升了约0.65 dB、0.59 dB。     

一种LDPC码混合迭代译码算法研究

根据LDPC码RRWBF算法和UMP BP-Based算法,提出一种混合迭代译码算法。该算法充分利用硬判决算法具有复杂度低和软判决算法性能好的优点,实现了在误码率性能没有下降的前提下,译码复杂度明显降低的效果,进而使传播时延得到减小。仿真结果表明,经过精心设计的不同迭代次数的MIA算法与性能相当的UMP BP-Based算法相比,译码复杂度降低28.5%。     

SCMA场景下的极化码编解码方案改进研究

极化码是目前唯一一种被证明可达到信道容量的编码方式,稀疏码分多址接入(Sparse Code Division Multiple Access,SCMA)可以提高频谱资源的利用率和接入系统的用户接入数量。为了提升SCMA与极化码的联合系统的误码率性能和译码时延,使联合系统的应用越来越广泛,提出了2种降低译码复杂度的方式:简化的左信息更新方式和剪枝译码算法。简化的左信息更新方式对于N=256,N=1024的极化码分别能降低37.6%和44.6%的存储资源占用数;剪枝译码算法在码率为0.5时能降低50%左右的计算复杂度。基于简化的SCAN算法改进了联合检测译码算法,在接收机采用外循环迭代的结构,引入了阻尼机制,选取最优的阻尼方式和最优阻尼值。仿真分析了所提联合检测译码算法与原有联合检测译码算法的误码率性能差异,外迭代接收机性能与内外双循环迭代的接收机性能相同,采用阻尼机制联合接收机的性能比无阻尼接收机的性能高0.8 dB左右,SJIDD的误帧率性能比保留宽度为32的SCLJDD的性能低0.7 dB左右,但能使接收机处理时延降至原来的1/4~1/8。     

LDPC码的改进迭代比特翻转译码算法

为提高低密度奇偶校验(LDPC)码的低复杂度硬判决译码算法的性能,提出了一种改进的比特翻转(BF)译码算法,在迭代时利用一个交替的门限模式对多个比特进行翻转,降低了每次迭代时比特被错误翻转的概率,从而有效提高了译码性能.仿真结果表明,与BF算法相比,该算法在保持低复杂度的基础上获得了更好的译码性能和更快的收敛速度.     

系统极化码的高效低复杂度编译码算法研究

系统极化码能减弱非系统极化码在连续抵消(SC)译码时的误码扩散敏感性,且在相同计算复杂度下拥有更好的误码性能,已被第五代通信系统采用,作为信道编码方式之一。在对系统极化码进行构造时采用经典的巴氏参数界法,编码时采用复杂度低且高效的非迭代编码算法,译码时采用循环校验码(CRC)辅助的基于对数似然比的连续抵消列表算法(LLR-SCL)与再编码结合。仿真结果表明,低信噪比下中等长度的系统极化码的SCL译码性能远优于SC译码;再加以CRC辅助译码后,其性能可得到大幅提升。     

一种简化的LDPC码BP译码算法的研究

低密度奇偶校验码(LDPC码)是一种逼近香农限的线性分组码,译码的复杂度较低;在LDPC码译码算法中性能较好的是置信传播译码(BP)算法,他能够在迭代译码过程中确定码字是否已译出,但是复杂度高,运算量大。采用一种改进的BP译码算法,在迭代译码过程中对校验节点的更新信息进行曲线拟合,以减小译码运算量,有利于硬件的并行实现,减少译码延时。仿真结果表明,改进的BP算法译码性能和原来的BP算法接近,而且复杂度较低。     

基于Polar码的速率兼容调制方案设计

提出了一种基于Polar码的速率兼容调制（rate compatible modulation,RCM）联合设计方案,用于提高无线通信频谱利用率.相应地设计了基于置信度传播（belief propagation,BP）和软抵消（soft cancellation,SCAN）的接收端高效联合迭代译码算法.根据该算法可通过优化变量节点对数似然比（log-likelihood ratio,LLR）信息迭代方式以及采用限制译码符号上限的改进措施,提高译码过程的稳定性与时效性.与距离优化的级联低密度奇偶校验（low-density parity-check codes,LDPC）码RCM方案对比结果表明,提出的高效联合迭代译码算法在低信噪比（signal noise ratio,SNR）下有更低的译码复杂度,并且具有更优的吞吐量和误码率性能.因此,本文所提方案适合在恶劣信道条件下的无线传输.     

基于循环群的准循环LDPC码构造

随机LDPC码的编码相当复杂,相对随机LDPC码而言准循环LDPC码具有编码复杂度低的特点,它可以用移位寄存器来实现线性复杂度的编码器.LDPC码通常采用Tanner图上的和积算法进行迭代译码.对于无圈的Tanner图,即girth为无穷大的Tanner图,和积译码是一种最优译码算法.本文提出了一种基于行列约束的LDPC码代数构造方法,这种构造方法可以构造出一类二元的准循环LDPC码,它的girth不小于6.仿真结果表明,构造出来的LDPC码在AWGN信道下采用和积迭代译码就误块率与误码率等方面的性能可与标准码相当.     

迭代检测算法在比特交织编码调制系统中的比较研究

迭代检测技术不仅局限于在传统的级联码系统中的应用,还可用于解决现代数字通信中的许多检测／译码问题。随着Turbo码的出现,人们对迭代译码算法进行深入研究,并提出一些简化译码算法。比特交织编码调制及迭代检测（bit—interleaved coded modulation with iterative decoding,BICMID）是一种高效数据传输系统。比特交织和迭代译码是BICM—ID系统具有卓越性能的关键因素,译码算法的选择不仅影响接收机的性能,也决定了系统的复杂度。文中研究迭代译码算法对BICM—ID系统性能的影响,分析各种译码算法的计算复杂度。仿真结果表明log-APP算法有好的性能同时复杂度也高,简化的译码算法能降低译码器的复杂度,但会带来一定的性能损失;随着信道条件的改善,算法简化带来的性能损失也随之减小。     

采用C语言FPGA技术实现LDPC码译码算法

针对LDPC码(Low Density Parity Check Codes)译码算法的特点和最新一代Impulse C语言的并行编程技术,提出一种对LDPC码译码器进行FPGA(Field Programmable Gate Array)设计与实现的便捷新方案,以获得译码速率和硬件资源消耗的平衡.在XC2V2000芯片上实现了一种码率1/2,码长2500的(3,6)LDPC码译码器.实验表明当最大迭代次数为10次,主频50MHz时,译码速率可达10Mbps.     

基于陷阱检测的咬尾卷积码译码算法

该文分析了循环维特比算法(CVA)中存在的循环陷阱问题,并证明了传统基于CVA的咬尾卷积码译码算法中存在的不足,提出了一种高效率的咬尾卷积码译码算法。该算法通过检测两次不同迭代中获得的两条最大似然路径是否相同来判断是否有循环陷阱产生,并及时终止循环,减少冗余迭代;在没有循环陷阱产生的情况下,新算法比较当前迭代中最大似然路径和已经发现的最优咬尾路径是否相同来自适应终止迭代。文中对循环陷阱检测方案和自适应终止方案做了进一步优化,即利用路径的净增量而非路径本身作为检测量。实验结果表明新算法提高了译码效率,降低了译码复杂度。     

RS码与LDPC码的联合迭代译码

针对RS码与LDPC码的串行级联结构,提出了一种基于自适应置信传播(ABP)的联合迭代译码方法.译码时,LDPC码置信传播译码器输出的软信息作为RS码ABP译码器的输入;经过一定迭代译码后,RS码译码器输出的软信息又作为LDPC译码器的输入.软输入软输出的RS译码器与LDPC译码器之间经过多次信息传递,译码性能有很大提高.码长中等的LDPC码采用这种级联方案,可以有效克服短环的影响,消除错误平层.仿真结果显示:AWGN信道下这种基于ABP的RS码与LDPC码的联合迭代译码方案可以获得约0.8 dB的增益.     

FPGA implementation of low complexity LDPC iterative decoder

Low-density parity-check (LDPC) codes, proposed by Gallager, emerged as a class of codes which can yield very good performance on the additive white Gaussian noise channel as well as on the binary symmetric channel. LDPC codes have gained lots of importance due to their capacity achieving property and excellent performance in the noisy channel. Belief propagation (BP) algorithm and its approximations, most notably min-sum, are popular iterative decoding algorithms used for LDPC and turbo codes. The trade-off between the hardware complexity and the decoding throughput is a critical factor in the implementation of the practical decoder. This article presents introduction to LDPC codes and its various decoding algorithms followed by realisation of LDPC decoder by using simplified message passing algorithm and partially parallel decoder architecture. Simplified message passing algorithm has been proposed for trade-off between low decoding complexity and decoder performance. It greatly reduces the routing and check node complexity of the decoder. Partially parallel decoder architecture possesses high speed and reduced complexity. The improved design of the decoder possesses a maximum symbol throughput of 92.95 Mbps and a maximum of 18 decoding iterations. The article presents implementation of 9216 bits, rate-1/2, (3, 6) LDPC decoder on Xilinx XC3D3400A device from Spartan-3A DSP family.     

An FPGA Implementation of High‐Speed Flexible 27‐Mbps 8‐StateTurbo Decoder

In this paper, we propose a flexible turbo decoding algorithm for a high order modulation scheme that uses a standard half‐rate turbo decoder designed for binary quadrature phase‐shift keying (B/QPSK) modulation. A transformation applied to the incoming I‐channel and Q‐channel symbols allows the use of an off‐the‐shelf B/QPSK turbo decoder without any modifications. Iterative codes such as turbo codes process the received symbols recursively to improve performance. As the number of iterations increases, the execution time and power consumption also increase. The proposed algorithm reduces the latency and power consumption by combination of the radix‐4, dual‐path processing, parallel decoding, and early‐stop algorithms. We implement the proposed scheme on a field‐programmable gate array and compare its decoding speed with that of a conventional decoder. The results show that the proposed flexible decoding algorithm is 6.4 times faster than the conventional scheme.     

Near-optimum decoding of product codes: block turbo codes

This paper describes an iterative decoding algorithm for any product code built using linear block codes. It is based on soft-input/soft-output decoders for decoding the component codes so that near-optimum performance is obtained at each iteration. This soft-input/soft-output decoder is a Chase decoder which delivers soft outputs instead of binary decisions. The soft output of the decoder is an estimation of the log-likelihood ratio (LLR) of the binary decisions given by the Chase decoder. The theoretical justifications of this algorithm are developed and the method used for computing the soft output is fully described. The iterative decoding of product codes is also known as the block turbo code (BTC) because the concept is quite similar to turbo codes based on iterative decoding of concatenated recursive convolutional codes. The performance of different Bose-Chaudhuri-Hocquenghem (BCH)-BTCs are given for the Gaussian and the Rayleigh channel. Performance on the Gaussian channel indicates that data transmission at 0.8 dB of Shannon's limit or more than 98% (R/C>0.98) of channel capacity can be achieved with high-code-rate BTC using only four iterations. For the Rayleigh channel, the slope of the bit-error rate (BER) curve is as steep as for the Gaussian channel without using channel state information     

A 690-mW 1-Gb/s 1024-b, rate-1/2 low-density parity-check codedecoder

A 1024-b, rate-1/2, soft decision low-density parity-check (LDPC) code decoder has been implemented that matches the coding gain of equivalent turbo codes. The decoder features a parallel architecture that supports a maximum throughput of 1 Gb/s while performing 64 decoder iterations. The parallel architecture enables rapid convergence in the decoding algorithm to be translated into low decoder switching activity resulting in a power dissipation of only 690 mW from a 1.5-V supply     

基于改进最小和算法的LDPC解码器的优化

对一种基于改进最小和算法的LDPC解码器做了优化,分析了由于量化引起的误差在解码过程中的变化过程,给出了优化后解码器的一种硬件结构。并在一个码长为504,码率为1/2的低密度奇偶校验码上,对优化前、后两种结构进行了分析和仿真,证明新结构与旧结构相比,在相同误比特率下所需信噪比节省约0.05dB,相同信噪比下成功解码所需平均迭代次数减少约3%     

LDPC-based channel coding of correlated sources with iterative joint decoding

This letter considers low-density parity-check (LDPC) coding of correlated binary sources and a novel iterative joint channel decoding without communication of any side information. We demonstrate that depending on the extent of the source correlation, additional coding gains can be obtained. Two stages of iterative decoding are employed. During global iterations, updated estimates of the source correlation are obtained and passed on to the sum-product decoder that performs local iterations with a predefined stopping criterion and/or a maximum number of local decoding iterations. Simulation results indicate that very few global iterations (2-5) are sufficient to reap significant benefits from implicit knowledge of source correlation. Finally, we provide analytical performance bounds for our iterative joint decoder and comparisons with sample simulation results.