基于异步保存及互锁存储单元的抗SEE触发器设计

利用Muller_C单元,设计一种异步保存及互锁存储单元结构,该结构采用状态锁存机制和增加节点电容方法,能有效防止单粒子翻转效应的发生,同时也可提高电路抗单粒子瞬变和多节点扰动效应的能力。在0.18μm工艺条件下用此结构设计的D触发器,面积为1 422μm2,动态功耗为0.42mW,建立时间为0.2ns,保持时间为0.03ns。实验结果表明:利用触发器链验证电路,在时钟频率为20 MHz时,单粒子LET翻转阈值为31MeV·cm2/mg,比双互锁存储单元结构的抗单粒子能力提高40%。     

一种带自刷新功能的三模冗余触发器设计

随着体硅CMOS电路工艺尺寸的不断缩小,数字电路在宇宙空间中受到的单粒子效应愈发严重。特别是触发器结构电路,单粒子效应中的单粒子翻转效应会造成触发器内部存储的数据发生错乱,影响电路正常工作。提出了一种带自刷新功能的三模冗余触发器设计,改进了传统三模冗余触发器设计只表决修正输出不刷新错误数据的不足。     

应用于抗辐照FPGA的多标准I/O电路设计

针对工业控制、航空航天等多种复杂的电磁辐射环境中对大规模FPGA器件及高速数据传输的迫切需求,设计了一种可应用于抗辐照FPGA的多标准I/O电路。该I/O电路中输入/输出寄存器均采用三模冗余(TMR)技术进行了抗辐照加固,能够支持14种电平标准,实现宽电压范围调节。该抗辐照FPGA抗单粒子翻转(SEU)大于37 MeV·cm2/mg。仿真及测试结果表明,该I/O电路满足设计要求。     

高可靠微处理器结构与实现

文章介绍了抗单粒子翻转容错处理器NBHARK的结构与实现．采用了改进的优化奇权重列编码方法纠检寄存器文件的瞬时错误。提出了多种有效方法提高整个处理器可靠性，如三模冗余内部临时寄存器,三模冗余时钟，片上EDAC，奇偶校验，强制cache缺失等。该芯片在smic0．18μmCMOS工艺投片。辐射试验表明，粒子注入（〉50，000）引起的单粒子翻转错误均成功纠正。试验采用^252Cf辐射源，3．5uCi，以及43MeV．cm^2／mg平均LET进行。     

异步FIFO抗SEU设计

在高空高能粒子的影响下，航天或航空电子设计中广泛使用的异步FIFO容易产生单粒子翻转，从而导致功能紊乱甚至失效。因此在面向航天或航空的高安全电子设计中需采用容错设计来提高异步FIFO电路的抗辐射能力。但传统的三模冗余设计应用于异步FIFO时有一定的局限性，会出现由指针错误引起的某一通道的数据持续出错、跨时钟域导致的输出数据不同步等降低三模冗余防护能力的问题。针对该问题，文中提出适用于异步FIFO的新的电路结构及三模冗余方案。经仿真证明，采用新三模冗余方案构建的异步FIFO在辐射环境下能快速纠正指针错误，同步三路冗余数据，使其具有更高的单粒子防护效果。     

DICE型D触发器三模冗余实现及辐照实验验证

分析了三模冗余(TMR)型D触发器和双互锁存储单元(DICE)型D触发器各自的优点和缺点,基于三模冗余和双互锁存储单元技术的(TMRDICE)相融合方法,设计实现了基于双互锁存储单元技术的三模冗余D触发器。从电路级研究了TMRDICE型D触发器抗单粒子翻转的性能,与其他传统类型电路结构的D触发器进行了抗单粒子翻转性能比较,并通过电路仿真和辐照实验进行了验证。仿真结果表明,TMRDICE型D触发器的抗单粒子翻转性能明显优于传统的普通D触发器、TMR型D触发器和DICE型D触发器。辐照实验结果表明,TMRDICE型D触发器具有最小的翻转截面。     

一种分辨率为39μV的高精度比较器设计

该文主要介绍了一个应用于12bit SAR ADC中的高精度比较器。基于预放大锁存理论,完成了预放大级、锁存比较级和输出缓冲级三个模块的设计。为达到所需比较器的精度,对预放大级进行优化设计,锁存比较级电路采用的是动态锁存结构,而输出缓冲级采用的是SR锁存电路。该比较器是在GSMC 0.18μm工艺下完成仿真设计的,经测试,在300M时钟下,比较器的分辨率为39μV。     

基于抗辐照技术的DDS电路设计与实现

直接数字频率合成器(DDS)作为关键器件被广泛应用在航空航天领域中。芯片在广阔的宇宙空间中易受到高能辐射粒子的影响,其中单粒子翻转(SEU)效应是一种十分常见的辐射效应,将导致电路功能异常甚至失效,这就要求DDS芯片能有非常强的抗辐照性能。提出一种基于三模冗余结构并具有自纠错功能的寄存器,将其应用在DDS的电路设计中,并将芯片的数字电路部分插入三模冗余结构,利用冗余结构去除掉故障电路对整个DDS芯片功能的影响,使得DDS芯片的抗辐照能力得到有效提升。     

基于DICE结构的主-从型抗辐照触发器设计

基于双互锁存储单元(DICE)结构,采用TSMC 0.18μm体硅CMOS工艺,设计了一个带复位和清零端的主一从型抗辐照触发器.通过将数据存放在不同的节点以及电路的恢复机制,使单个存储节点具有抗单粒子翻转的能力.采用多种改进设计,增强抗单粒子瞬态脉冲(single event transient,SET)的能力,并且降低了电路功耗.通过Spectre仿真,测试了触发器的抗单粒子翻转(single event upset,SEU)能力,确定了版图设计规则.采用新颖的3倍高度的版图布置及环栅NMOS结构,消除了总剂量效应;采用双保护环,降低了单粒子闩锁效应;最终完成了全方位抗辐照的触发器电路设计.     

一种双节点翻转加固的RS触发器

随着IC集成度的不断提高,电路中单粒子引起的多节点翻转现象愈加频繁。为了解决该问题,提出了一种可对两个电压节点翻转完全免疫的RS触发器电路。基于双互锁存储单元结构,设计了一个冗余度为4的前置RS触发器。将不相邻的两个输出节点连接到一个改进型C单元电路中,屏蔽了错误电压,最终输出电压不受单粒子翻转的影响。该RS触发器采用0.25 μm 2P4M 商用标准CMOS工艺实现。对RS触发器中任意两个电路节点同时分别注入两个单粒子事件,进行了抗单粒子翻转的可靠性验证。Spectre仿真结果表明,该RS触发器能完全对两个单粒子事件免疫。与已发表的辐射加固触发器相比,该触发器采用的晶体管个数减少了20.8%,功耗降低了21.3%。     

一种具有掉电数据保持功能的触发器设计

提出了一种用相变器件作为可擦写存储单元的具有掉电数据保持功能的触发器电路.该触发器由四部分组成:具有恢复掉电时数据的双置位端触发器DFF、上电掉电监测置位电路(Power On/Off Reset)、相变存储单元的读写电路(Read Write)和Reset/Set信号产生电路,使之在掉电时能够保存数据,并在上电时完成数据恢复.基于0.13μm SMIC标准CMOS工艺,采用Candence软件对触发器进行仿真,掉电速度达到0.15μs/V的情况下,上电时可以在30ns内恢复掉电时的数据状态.     

一种中速高精度模拟电压比较器的设计

设计一种中速高精度模拟电压比较器,该比较器采用3级前置放大器加锁存器和数字触发电路的多级结构,应用失调校准技术消除失调,应用共源共栅结构抑制回程噪声干扰;应用数字触发电路获得高性能数字输出信号,设计采用0．35μm5VCMOS工艺实现一个输入电压2．5V、速度1MS／s、精度12位的逐次逼近型MD转换器。Hspice仿真结果表明：在5V供电电压下,速度可达20MHz,准确比较0．2mV电压,有效校准20mV输入失调,功耗约1mW。     

Design techniques of low-power embedded EEPROM for passive RFID tag

This paper presents an optimized embedded EEPROM design approach which has reduced the power significantly in a short-range passive RFID tag. The proposed array control circuit employs an improved structure to minimize the leakage of memory bit cells. With the proposed array circuit design, the passive RFID tag can operate drawing a low quiescent current. The RFID tag with the proposed EEPROM was fabricated in a standard 0.35-μm four-metal two-poly CMOS process. Measurement results show that the erasing/writing current is 45 μA, and reading current consumption is 3 μA with a supply voltage of 3.3 V. The data read time is 300 ns/bit.     

Time-interleaved CMOS chip design of Manchester and Miller encoder for RFID application

In this paper, we propose a modified Manchester and Miller encoder that can operate in high frequency without a sophisticated circuit structure. Based on the previous proposed architecture, the study has adopted the concept of parallel operation to improve data throughput. In addition, the technique of hardware sharing is adopted in this design to reduce the number of transistors. This circuit is realized by using TSMC CMOS 0.35-μm 2P4M technologies. The simulation results of HSPICE indicate that it functions and works successfully at 200-MHz data rate. An experimental chip had been fabricated and measured. The measured results show that the experimental chip has 50 MHz data throughput rate under 3.3-V supply voltage. The lowest supply voltage 0.6 V is achievable working at 5 kHz data rate. The average power consumption of the circuit under room temperature is 549 μW. The chip area is 70.7 μm × 72.2 μm. The compact structure and high-speed operation are useful for radio frequency identification applications.     

A diagonal address generator for a Josephson memory circuit

The authors propose that a diagonal D address generator, which is useful for a single flux quantum (SFQ) memory cell in the triple coincidence scheme, can be performed by a full adder circuit. For the purpose of evaluating the D address generator for a 16-Kbit memory circuit, a 6-bit full adder circuit, using a current-steering flip-flop circuit, has been designed and fabricated with the lead-alloy process. Operating times for the address latch, carry generator, and sum generator were 150 ps, 250 ps/stage, and 1.4 ns, respectively. From these results, it has been estimated that the time necessary for the diagonal signal generation is 2.8 ns.     

三值低功耗多米诺JKL触发器设计及应用

通过对三值触发器和绝热多米诺电路的研究,提出一种新颖低功耗多米诺JKL触发器开关级设计方案。该方案首先利用开关—信号理论,根据三值JKL触发器真值表,推导出三值绝热多米诺JKL触发器开关级结构式;然后利用三值JKL触发器实现三值正循环门电路和三值反循环门电路的设计;最后,经Spice软件模拟证明所设计的三值绝热多米诺JKL触发器逻辑功能正确,与常规三值多米诺JKL触发器相比,能耗节省约69%。     

A 4K CMOS gate array with automatically generated test circuits

A 2-/spl mu/m CMOS 4K-gate array using a newly devised scan bus method has been developed. This method is applied to the array by using a double-latch structure, parallel scanning, and normal-test common pin techniques. The gate array can be tested for 95-100% of all DC faults using computer-generated test circuits and test data, without placing restrictions on the logic design. Due to an access-to-output flip-flop structure and a gate-isolated three-input type basic cell, including embedded transistors, the area increase and operating speed degradation due to test circuits are considerably reduced. Furthermore, besides the flip-flop blocks, a built-in RAM macroblock is available. Degradation of operating speed is evaluated as 10%. The scan operation is done at a clock cycle of 120 ns, and the access time of the RAM macroblock is 34 ns. The gate array includes 4032 three-input gates on a 7.2/spl times/7.02-mm chip.     

Optimization of the latching pulse for dynamic flip-flop sensors

Analysis of dynamic IGFET flip-flop charge sensors shows that the optimum latching waveform is an initial voltage step followed by a ramp of gradually increasing slope. Latchup time is approximately inversely proportional to the initial voltage imbalance. Capacitive coupling between the two sides of the flip-flop generates a voltage excursion of the off-side even when there is no off-side conduction. With a 10-V latching ramp, the off-side is no off-side conduction. With a 10-V latching ramp, the off-side voltage excursion is typically about 2 V, and full latchup is attained in about 75 ns for an initial imbalance of 0.5 V. If a small off-side conduction is allowed, then latchup time can be reduced by a factor of two or more. The penalty is a few tenths of a volt added excursion of the off-side voltage. Computer circuit simulations were used to verify the analytic derivations.     

Compact SPAD pixels with fast and accurate photon counting in the analog domain

A compact pixel for single-photon detection in the analog domain is presented.The pixel integrates a single-photon avalanche diode (SPAD),a passive quenching & active recharging circuit (PQARC),and an analog counter for fast and accurate sensing and counting of photons.Fabricated in a standard 0.18μm CMOS technology,the simulated and experimental results reveal that the dead time of the PQARC is about 8 ns and the maximum photon-counting rate can reach 125 Mcps (counting per second).The analog counter can achieve an 8-bit counting range with a voltage step of 6.9 mV.The differential nonlinearity (DNL) and integral nonlinearity (INL) of the analog counter are within the ± 0.6 and ± 1.2 LSB,respectively,indicating high linearity of photon counting.Due to its simple circuit structure and compact layout configuration,the total area occupation of the presented pixel is about 1500μm2,leading to a high fill factor of 9.2％.The presented in-pixel front-end circuit is very suitable for the high-density array integration of SPAD sensors.     

体串联电阻对体接触SOI数字D触发器速度特性的影响

在用体接触结构设计的SOI电路中,浮体效应被压制了,但是体串联电阻的存在仍旧在远离体接触的体区产生局部浮体效应。对于数字电路来说,浮体效应会影响他们的速度。本文采用体接触结构设计了数字D触发器,并制造了这种电路,展示了电路的性能。实际器件的输出特性表明了浮体效应的存在。SPICE模拟表明体串联电阻对体接触SOI数字D触发器速度特性有明显的影响。