基于网络监控器的专用片上网络动态容错路由

针对专用片上网络（Network on Chip,NoC）全局通信事务管理和可靠性设计问题,提出片上网络监控器的概念,用于获取全局网络实时状态信息及执行路径分配算法,基于此提出一种动态路由机制DyRS-NM.该机制能检测和定位NoC中的拥塞和故障链路,并能区分瞬时和永久性链路故障,采用重传方式避免瞬时故障,通过重新路由计算绕开拥塞和永久性故障.设计实现了RTL级网络监控器和与之通信的容错路由器模块,并将MPEG4解码器应用映射至基于网络监控器的4×4Mesh结构NoC体系结构中,验证了系统性能以及面积功耗开销.相比静态XY路由和容错动态路由FADR,DyRS-NM机制在可接受的开销代价下获得了更优的性能.     

基于重构的片上网络容错机制

为了保证片上网络的可靠性,本文提出了一种新的容错机制。在片上网络中由于路由器故障将导致与其连接的IP核不能与其他核通信,使片上网络的可靠性降低。本文的方法通过选择最优相邻的路由器来替代故障路由器,从而达到恢复IP核通信的目的。通过为每个路由器配置一个状态寄存器,用来存储相邻路由器的安全度,在路由时采用新的可重构路由算法绕过故障的路由器,以提高片上网络的可靠性。在OPNET平台上对5×52D-Mesh结构的片上网络进行仿真实验,统计了数据传输延时。试验结果表明,本文提出的路由算法与对比文献的路由算法相比,在延迟方面有明显的优势。     

A Fault Tolerant Hierarchical Network on Chip Router Architecture

Continuing advances in the processing technology, along with the significant decreases in the feature size of integrated circuits lead to increases in susceptibility to transient errors and permanent faults. Network on Chips (NoCs) have come to address the demands for high bandwidth communication among processing elements. The structural redundancy inherited in NoC-based design can be exploited to improve reliability and compensate for the effects of failures. In this paper, we propose an enhanced fault tolerant microarchitecture with deadlock-free routing for Hierarchical NoCs. The proposed router supplies dynamic Virtual Channel (VC) Allocation, and it employs a high-performance fault tolerant control flow, handling both transient and permanent faults in hierarchical networks without extra retransmission buffer requirements. Experimental results show a significant improvement in reliability as well as decreases in the average latency and energy consumption.     

Bio-inspired fault tolerant network on chip

The integration of heterogeneous processing elements (PEs) or nodes in the System on Chip (SoC) has made the communication structure very complex. The bus based system between these components is not able to handle the communication requirements and, this has led to the idea of Network on Chip (NoC). The NoC addresses the communication requirement of different nodes on SoC. The physical sizes of devices in NoC are scaled down, including routers, processing elements and interconnects, giving rise to faults, system delay, and latency issues. Fault tolerant routing algorithms are used to recover from temporary faults while redundant resources (wires, routers) are required to overcome the permanent faults. These routing algorithms, however, still suffer from congestion problems, low bandwidth, and throughput utilization as well as lacking adaptivity and robustness. In this work, novel biologically inspired techniques were proposed for NoC using combined best effort (BE) and guaranteed throughput (GT) services. Moreover, the bio-inspired algorithms are compared and analyzed with each other using BE, GT and combined BE-GT services. The bio-inspired mechanisms of “synaptogenesis” and “sprouting” have been adopted in the proposed NoC algorithms and architecture. These techniques were implemented using the BE and GT services. With the help of these two bio-inspired techniques, the NoC becomes robust, fault tolerant and is able to efficiently utilize the throughput and bandwidth. The bio-inspired algorithms improved the accepted traffic (flit/cycle/node) by 38.99% compared to different techniques in the literature. The bio-inspired algorithm also improved the bandwidth and throughput utilization by 71.04% and 72.42% respectively compared to the XY and Odd-Even fault tolerant routing algorithms. Moreover, the bio-inspired algorithm had less end-to-end latency and interflit arrival time by 196.44% and 88.10% respectively compared to the literature techniques of XY and Odd-Even.     

一种自适应动态缓存策略准入控制算法

针对片上网络的死锁问题,基于虚拟网络的自适应路由算法,设计了一个完全自适应片上路由器.重点介绍了路由算法及路由器的系统结构,设计实现了一个低代价、高效的完全自适应路由器,并在2DMesh拓扑结构下对其性能进行了模拟验证.实验结果表明,该路由器实现了无死锁的自适应路由,并提高了网络吞吐量,降低了平均网络延迟.     

Partial Virtual Channel Sharing: A Generic Methodology to Enhance Resource Management and Fault Tolerance in Networks-on-Chip

We present a novel Partial Virtual channel Sharing (PVS) NoC architecture which reduces the impact of faults on performance and also tolerates faults within the routing logic. Without PVS, failure of a component impairs the fault-free connected components, which leads to considerable performance degradation. Improving resource utilization is key in enhancing or sustaining performance with minimal overhead when faults or overload occurs. In the proposed architecture, autonomic virtual-channel buffer sharing is implemented with a novel algorithm that determines the sharing of buffers among a set of ports. The runtime allocation of the buffers depends on incoming load and fault occurrence. In addition, we propose an efficient technique for maintaining the accessibility of a processing element (PE) to the network even if its router is faulty. Our techniques can be used in any NoC topology and for both, 2D and 3D NoCs. The synthesis results for an integrated video conference application demonstrate 22 % reduction in average packet latency compared to state-of-the-art virtual channel (VC) based NoC architecture. Extensive quantitative simulation has been carried out with synthetic benchmarks. Simulation results reveal that the PVS architecture improves the performance significantly in presence of faults, compared to other VC-based NoC architectures.     

Adaptive gossip protocols: Managing security and redundancy in dense ad hoc networks

Many ad hoc routing algorithms rely on broadcast flooding for location discovery or, more generally, for secure routing applications. Flooding is a robust algorithm but because of its extreme redundancy, it is impractical in dense networks. Indeed in large wireless networks, the use of flooding algorithms may lead to broadcast storms where the number of collisions is so large that it causes system failure. To prevent broadcast storms, many mechanisms that reduce redundant transmissions have been proposed that reduce retransmission overhead either deterministically or probabilistically.Gossip is a probabilistic algorithm in which packet retransmission is based on the outcome of coin tosses. The retransmission probability can be fixed, dynamic or adaptive. With dynamic gossip, local information is used to determine the retransmission probability. With adaptive gossip, the decision to relay is adjusted adaptively based on the outcome of coin tosses, the local network structure, and the local response to the flooding call. The goal of gossip is to minimize the number of retransmissions, while retaining the main benefits of flooding, e.g., universal coverage, minimal state retention, and path length preservation.In this paper we consider ways to reduce the number of redundant transmissions in flooding while guaranteeing security. We present several new gossip protocols that exploit local connectivity to adaptively correct propagation failures and protect against Byzantine attacks. A main contribution of this work is that we introduce a cell-grid approach that allows us to analytically prove performance and security protocol properties. The last two gossip protocols that we give are fully adaptive, i.e., they automatically correct all faults and guarantee delivery, the first such protocols to the best of our knowledge.     

接口标记容错路由算法

随着片上系统(SoC)集成度的不断提高,IP核之间的通信故障成为亟待解决的问题,片上网络(NoC)是解决SoC通信问题的有效途径。容错路由算法是NoC设计中的关键技术,对NoC的通信效率有重要影响。在Valiant随机路由算法和源路由算法的基础上,提出了一种接口标记容错路由算法。该算法吸取了Valiant随机路由算法能平衡网络负载、降低拥塞概率的优良性能与源路由算法中路径不需要计算与查找的特点,减小了传输时延,提高了路由器的利用率。     

Region-Based Routing: A Mechanism to Support Efficient Routing Algorithms in NoCs

An efficient routing algorithm is important for large on-chip networks [network-on-chip (NoC)] to provide the required communication performance to applications. Implementing NoC using table-based switches provide many advantages, including possibility of changing routing algorithms and fault tolerance, due to the option of table reconfigurations. However, table-based switches have been considered unsuitable for NoCs due to their perceived high area and power consumption. In this paper, we describe the region-based routing (RBR) mechanism which groups destinations into network regions allowing an efficient implementation with logic blocks. RBR can also be viewed as a mechanism to reduce the number of entries in routing tables. RBR is general and can be used in conjunction with any adaptive routing algorithm. In particular, we have evaluated the proposed scheme in conjunction with a general routing algorithm, namely segment-based routing (SR) and an Application Specific Routing Algorithm (APSRA) using regular and irregular mesh topologies. Our study shows that the number of entries in the table is significantly reduced, especially for large networks. Evaluation results show that RBR requires only four regions to support several routing algorithms in a 2-D mesh with no performance degradation. Considering link failures, our results indicate that RBR combined with SR is able to tolerate up to 7 link failures in an 8 $,times,$8 mesh. RBR also reduces area and power dissipation of an equivalent table-based implementation by factors of 8 and 10, respectively. Moreover, the degradation in performance of the network is insignificant when using APSRA combined with RBR.      

Topology and analysis of an N-stage cascaded polymer eight-port microring optical router with 7N channel wavelengths

Eight-port optical routers are widely used in cluster-mesh photonic networks-on-chip(No C). By using 24 groups of cross-coupling two-ring resonators, a 1-stage 8-port polymer optical router is proposed, which can optically route 7 channel wavelength data streams along definite path in two-dimensional(2D) plane. Under the selected 7 channel wavelengths, the insertion losses along all routing paths are within 0.02-0.58 d B, the maximum crosstalk of all routing operations is less than-39 d B, and the device footprint size is about 0.79 mm2. Then, a universal novel structure and routing scheme of N-stage cascaded 8-port optical router are presented, which contains 7N channel wavelengths. Because of the good scalability in wavelength, this device shows potential application of wideband signal routing in optical No C.     

A low overhead load balancing router for network-on-chip

The design of a router in a network-on-chip (NoC) system has an important impact on some performance criteria. In this paper, we propose a low overhead load balancing router (LOLBR) for 2D mesh NoC to enhance routing performance criteria with low hardware overhead. The proposed LOLBR employs a balance toggle identifier to control the initial routing direction of X or Y for flit injection. The simplified demultiplexers and multiplexers are used to handle output ports allocation and contention, which provide a guarantee of deadlock avoidance. Simulation results show that the proposed LOLBR yields an improvement of routing performance over the reported routing schemes in average packet latency by 26.5%. The layout area and power consumption of the network compared with the reported routing schemes are 15.3% and 11.6% less respectively.     

Performance analysis and fault tolerance of randomized routing on Clos networks

Beside universality and very low latency, Youssef's randomized self-routing algorithms [25] have high tolerance for multiple faults and more strikingly have the potential for fault tolerance without diagnosis. In this paper we study the performance of Youssef's routing algorithms for faulty Clos networks in the presence of multiple faults in multiple columns with and without fault detection. We show that with fault detection and diagnosis, randomized routing algorithms provide scalable, very efficient and fault tolerant routing mechanisms. Without fault detection and diagnosis, randomized routing provides good fault tolerance for faulty switches in either the first or the second column. The delays become large for faults in the third column or for faults in more than one column. In conclusion, randomized routing enables the system to run without periodic fault detection/diagnosis, and if and when the performance degrades beyond a certain threshold, diagnosis can be performed to improve the routing performance. This revised version was published online in June 2006 with corrections to the Cover Date.     

Fault-Tolerant Mesh-Based NoC with Router-Level Redundancy

The aggressively scaled CMOS technology is increasingly threatening the dependability of network-on-chips (NoCs) architecture. In a mesh-based NoC, a faulty router or broken link may isolate a well functional processing element (PE). Also, a set of faulty routers may form isolated regions, which can degrade the design. In this paper, we propose a router-level redundancy (RLR) fault-tolerant scheme that differs from the traditional microarchitecture-level redundancy (MLR) approach to relieve the problem of isolated PE and isolated region. By simply adding one spare router within each router set in a mesh, RLR can be created and connection paths between adjacent routers can be diversified. To exploit this extra resource, two reconfiguration algorithms are demonstrated to detour observed faulty routers/links. The proposed RLR fault-tolerant scheme can tolerate at most one faulty router within a router set. After the reconfiguration, the original mesh topology is maintained. As a result, the proposed architecture does not need any support from the network layer routing algorithms. The scheme has been evaluated based on the three fault-tolerant metrics: reliability, mean time to failure (MTTF), and yield. The experimental results show that the performance RLR increases as the size of NoC grows; however, the relative connection cost decreases at the same time. This characteristic makes our architecture suitable for large-scale NoC designs.

     

BiLink: A high performance NoC router architecture using bi-directional link with double data rate

This paper presents a novel high performance Network-on-Chip (NoC) router architecture design using a bi-directional link with double data rate (BiLink). Ideally, it can provide as high as 2 times speed-up compared with the conventional NoC router. BiLink utilizes an extra link stage between routers and transmits two flits in one link per cycle using phase pipelining if both routers require to use the current link. To further increase the effective bandwidth, the direction of each link can be configured in every clock cycle to cater for different traffic loads from each side. Therefore, the data rate can be as high as 4 times compared with conventional NoC routers under uneven traffic. Centralized mode control scheme is implemented using a finite state machine (FSM) approach. Cycle-accurate simulations are carried out on both synthetic traffic patterns as well as real application benchmarks. Simulation results show that BiLink can provide as high as 90% and 250% speedup compared with conventional NoC routers for even and uneven traffic, respectively. 2X and 3X gains in throughput are obtained under even and uneven traffic, respectively, when compared with the conventional NoC router for the virtual channel flow control. The BiLink router architecture is synthesized using TSMC 65 nm process technology and it is shown that an area overhead of 28% over state-of-the-art bi-directional NoC is introduced while the critical path is about 9% higher than that of the conventional routers. Despite the overhead in critical path and power consumption, a 47.45% improvement of Energy-Delay-Product (EDP) is achieved by BiLink under high injection rate traffic.     

Multicast-enabled network-on-chip routers leveraging partitioned allocation and switching

Multicast on-chip communication is encountered in various cache-coherence protocols targeting multi-core processors, and its pervasiveness is increasing due to the proliferation of machine learning accelerators. In-network handling of multicast traffic imposes additional switching-level restrictions to guarantee deadlock freedom, while it stresses the allocation efficiency of Network-on-Chip (NoC) routers. In this work, we propose a novel partitioned NoC router microarchitecture, called SmartFork, which employs a versatile and cost-efficient multicast packet replication scheme that allows the design of high-throughput and low-cost NoCs. The design is adapted to the average branch splitting observed in real-world multicast routing algorithms. Compared to state-of-the-art NoC multicast approaches, SmartFork is demonstrated to yield high performance in terms of latency and throughput, while still offering a cost-effective implementation.     

A load balancing bufferless deflection router for network-on-chip

The bufferless router emerges as an interesting option for cost-efficient in network-on-chip (NoC) design. However, the bufferless router only works well under low network load because deflection more easily occurs as the injection rate increases. In this paper, we propose a load balancing bufferless deflection router (LBBDR) for NoC that relieves the effect of deflection in bufferless NoC. The proposed LBBDR employs a balance toggle identifier in the source router to control the initial routing direction of X or Y for a flit in the network. Based on this mechanism, the flit is routed according to XY or YX routing in the network afterward. When two or more flits contend the same one desired output port a priority policy called nearer-first is used to address output ports allocation contention. Simulation results show that the proposed LBBDR yields an improvement of routing performance over the reported bufferless routing in the flit deflection rate, average packet latency and throughput by up to 13%, 10% and 6% respectively. The layout area and power consumption compared with the reported schemes are 12% and 7% less respectively.     

Energy efficient fault-tolerant multipath routing scheme for wireless sensor networks

In wireless sensor network （MSN）, reliability is the main issue to design any routing technique. To design a comprehensive reliable wireless sensor network, it is essential to consider node failure and energy constrain as inevitable phenomena. In this paper we present energy efficient node fault diagnosis and recovery for wireless sensor networks referred as energy efficient fault tolerant multipath routing scheme for wireless sensor network. The scheme is based on multipath data routing. One shortest path is used for main data routing in our scheme and other two backup paths are used as alternative path for faulty network and to handle the overloaded traffic on main channel. Shortest pat data routing ensures energy efficient data routing. Extensive simulation results have revealed that the performance of the proposed scheme is energy efficient and can tolerates more than 60% of fault.     

Performance evaluation of a routing algorithm based on Hopfield Neural Network for network-on-chip

Network on chip (NoC) has emerged as a solution to overcome the system on chip growing complexity and design challenges. A proper routing algorithm is a key issue of an NoC design. An appropriate routing method balances load across the network channels and keeps path length as short as possible. This survey investigates the performance of a routing algorithm based on Hopfield Neural Network. It is a dynamic programming to provide optimal path and network monitoring in real time. The aim of this article is to analyse the possibility of using a neural network as a router. The algorithm takes into account the path with the lowest delay (cost) form source to destination. In other words, the path a message takes from source to destination depends on network traffic situation at the time and it is the fastest one. The simulation results show that the proposed approach improves average delay, throughput and network congestion efficiently. At the same time, the increase in power consumption is almost negligible.     

TRACK: An algorithm for fault-tolerant,dynamic and scalable 2D mesh network-on-chip routing reconfiguration

Network-on-chip (NoC) is a reliable and scalable on-chip interconnect solution particularly used for MPSoCs and CMPs. Increasing susceptibility of NoC to failures is becoming a new research concern. Failures in components such as on-chip link or router may disrupt the underlying routing function. Reconfiguration of routing function is required to sustain network connectivity while maintaining deadlock-freedom in event of failure(s). Existing approaches either use routing tables or meta-data or involve all network nodes for participation in the reconfiguration process. This paper proposes TRACK, an algorithm for fast and scalable routing reconfiguration. It uses logic-based routing instead of tables and identifies affected nodes (i.e., rows/columns of mesh network) by single and double-link failures. In the proposed algorithm, reconfiguration is needed only for the affected nodes and the remaining network can continue to work. TRACK outperforms the existing one and reduces latency up to 42% and improves throughput up to 22% for single and double-link failures in 8 × 8 2D mesh network-on-chip. By employing logic-based routing, hardware cost is also reduced, i.e., 30% in area and 29.5% in power overhead for a 16 × 16 mesh router.     

WiNoC中无线通信拥塞与故障感知的容错路由算法

在无线片上网络中,无线通信拥塞和故障对整个片上网络的通信效率具有严重影响.为此本文提出了一种针对无线通信拥塞和故障的容错路由算法,首先设计了无线通信拥塞和故障感知模型,该模型能够感知无线节点通信对的拥塞和故障信息,并对其编码发送给子网中的路由器;然后子网中的路由器根据接收到的无线节点通信对状态信息,判断数据包是否使用无线传输.实验表明,本文方案相较于对比对象能够在较小的额外面积、功耗开销下,保证较低的网络延迟和较高的网络吞吐率,并对无线节点通信对的永久性故障具有良好的容错能力.