Fabrication of nanoscale tungsten tip arrays for scanning probemicroscopy-based devices

A new fabrication process for nanoscale tungsten tip arrays was developed for scanning probe microscopy-based devices. It is suitable to make a huge array on a device chip and is potentially compatible with CMOS technology. In this study, tungsten was selected as a tip material because of its hardness and conductivity. The newly developed fabrication process mainly consists of several important techniques: a combination of optical lithography and electron beam (EB) lithography to reduce the total exposure time with high resolution and chromium/tungsten/chromium (Cr/W/Cr) sandwich deposition and etching in which the first chromium layer is used as a mask and a second one is used as an etch stop. A periodic array of dots in an EB resist with a spot diameter of less than 50 nm was obtained by a combination of optical lithography and EB lithography with a positive resist (polymethylmethacrylate) in which all processing conditions were optimized carefully. A thin and uniform chromium film, deposited by ion-beam sputtering, allowed the use of thin polymethylmethacrylate (PMMA) film which led to the high resolution. The conditions of dc magnetron sputtering were also optimized in order to deposit a densely packed and low-resistivity film. The resulting tungsten tip arrays had a cylindrical shape with diameters of less than 60 nm and heights of 300 nm     

Fabrication of monolithic integrated fiber-lens connector arrays by deep proton irradiation

Deep proton irradiation in poly (methyl methacrylate) (PMMA) is a fabrication method for monolithic integrated micro optics which offers high stability and interesting autoalignment features. The process consists of three basic steps: irradiation of a PMMA substrate followed by either a development of the irradiated regions or a swelling of the irradiated regions by organic vapor or both applied to different regions. With this technique a variety of elementary refractive microoptical components and monolithically integrated combinations can be fabricated: microlenses, microprisms, beam splitters, fiber connectors with selfaligned microlenses on top of each fiber. This work was funded by IUAP24 “Optoelectronic Information Technology” and IUAP47 “Nonlinear Optics”, NFWO, Concerted Research Action “Photonic in Computing”.     

Fabrication of monolithic integrated fiber-lens connector arrays by deep proton irradiation

 Deep proton irradiation in poly (methyl methacrylate) (PMMA) is a fabrication method for monolithic integrated micro optics which offers high stability and interesting autoalignment features. The process consists of three basic steps: irradiation of a PMMA substrate followed by either a development of the irradiated regions or a swelling of the irradiated regions by organic vapor or both applied to different regions. With this technique a variety of elementary refractive microoptical components and monolithically integrated combinations can be fabricated: microlenses, microprisms, beam splitters, fiber connectors with selfaligned microlenses on top of each fiber. Received: 30 October 1995 / Accepted: 8 December 1995     

Fabrication of vapor-deposited micro heat pipe arrays as anintegral part of semiconductor devices

Vapor-deposited micro heat pipe arrays (VDMHP) were fabricated as an integral part of semiconductor devices to act as efficient heat spreaders by reducing the thermal path between the heat sources and heat sink. Fabrication of the VDMHP was accomplished by first establishing a series of grooves in a silicon wafer. Orientation dependent etching (ODE) using a KOH-1-propanol-H₂O solution on a (100) wafer with a (111) flat covered with an oxide mask, resulted in grooves 25 μm wide and 25 μm deep with sharp, perpendicular edges. The wafers were predeposited with a layer of chromium followed by a layer of gold to improve the adhesion characteristics. Dual electron beam vapor deposition, followed by planetary process using molybdenum crucibles, were used to deposit copper 31.5-33.0 μm thick, and provide complete closure of the grooves. A glass cover slip was bonded on the top of the deposited layer. The grooves were finally charged and sealed. A computer model Simulation and Modeling of Evaporated Deposition Profiles (SAMPLE) was used to optimize the metal step coverage and successfully predict the cross-sectional profile of the VDMHP     

Novel capacitive sensor: Fabrication from carbon nanotube arrays and sensing property characterization

A sandwich-structured gas sensor based on vertically aligned carbon nanotube (CNT) arrays was fabricated and investigated for ammonia and formic acid sensing. Vertically aligned CNT arrays were synthesized by acetone pyrolysis in anodized aluminum oxide (AAO) templates without the use of catalysts. The capacitance change of the sensor with target gas exposure was used as the sensing parameter. The sensor had relatively short response and recovery time. It was completely recovered within 6 min, without requiring any external stimuli. The possible mechanism of the responses was also discussed.     

Fabrication of compliant high aspect ratio silicon microelectrode arrays using micro-wire electrical discharge machining

This paper reports on the fabrication of high aspect ratio silicon microelectrode arrays by micro-wire electrical discharge machining (μ-WEDM). Arrays with 144 electrodes on a 400 μm pitch were machined on 6 and 10 mm thick p-type silicon wafers to a length of 5 and 9 mm, respectively. Machining parameters such as voltage and capacitance were varied for different wire types to maximize the machining rate and to obtain uniform electrodes. Finite element analysis was performed to investigate electrode shapes with reduced lateral rigidity. These compliant geometries were machined using μ-WEDM followed by a two step chemical etching process to remove the recast layer and to reduce the cross sections of the electrodes.     

Fabrication and analysis of the reflowed microlens arrays using JSR THB-130 N photoresist with different heat treatments

This paper reports that the fabrication of the reflowed microlens by the negative tone JSR THB-130 N photoresist can be treated with different thermal treatments using hotplate and oven. The different disk or thin cylinder arrays with diameters of 40–70 μm and thickness of about 7.4 μm were patterned using photolithography technology, and baked at 220°C by two kinds of thermal treatments using hotplate and oven to form reflowed microlens arrays. The spot size of the refractive microlens was then measured by optical microscopy and the total focal length of refractive microlens was simulated by curve fitting the lens profiles. The resolution of the microlens arrays approaches to 400 dpi as coated with Hexamethyldisilizane material. The smallest spot size of about 2.72 μm at the nominal 40 μm microlensis is obtained by the oven heat treatment, and the shortest total focal length of about 150 μm at the nominal 40 μm microlens is achieved by the hotplate heat treatment. The reduced spot size and total focal length of the microlens could improve the density and performance of optical devices and imaging systems.     

Optimal simulation of tree arrays by linear arrays

We show that an n-node complete binary tree can be embedded into an n-node linear array such that the maximum edge length is n/log n, and the distribution of the tree nodes is regular in the sense that if each node in the tree array is a finite-state machine and each edge is a communication channel, then the message exchanges (i.e., communication) among the tree nodes can be easily simulated by the linear array which has also finite-state machines for its nodes. The embedding is optimal with respect to the maximum edge length. The motivation for this is the proof of the following result: every cellular (or (log n)-depth iterative) tree array running in T(n) time can be simulated by a linear cellular (or iterative) array in nT(n)/log n time.     

Unimodular arrays

This paper explores relationships between optimal erasure-burst-correcting convolutional codes, arrays of integers within which all submatrices whose upper left corner lies on a certain boundary have determinant one, and enumerations of certain parts within such arrays.     

Materials optimization for semiconducting polymer LEDs and FETs

Dye‐doped semiconducting polymers are used as active layers in polymer light‐emitting diodes (polyLEDs). The emission color can be tuned by doping the active polymer with certain dyes. This concept of energy transfer is demonstrated for a green matrix doped with a red‐emitting dye, suitable for use in LEDs. An absolute PL efficiency of 39% is observed for this system. Another very attractive development is taking place in the area of all‐polymer transistors. This may lead to a (partial) replacement of the driving electronics by all‐plastic circuits. A new precursor route toward poly(thienylenevinylene)s (PTVs), suitable as active material in all‐polymer integrated circuits, is presented. Synthesis of the precursors is reproducible and fast, and can readily be scaled for manufacture. Quantitative conversion of the precursor polymer can be accomplished by heating at 150°C for 20 min. The resulting mobility (6 × 10^?3 cm²/V‐sec) and ON‐OFF ratio (4 × 10⁴) makes this material a suitable candidate for the development and large‐scale manufacturing of all‐polymer integrated circuits.     

E-beam lithography of nano-interdigital transducers on insulating and semiconducting substrates

This work describes the micro-fabrication process developed to manufacture nano-interdigital transducers (nano-IDTs) to be used in surface acoustic wave applications. The combination of electron-beam (e-beam) lithography and lift-off process is shown to be effective in fabricating IDT finger patterns with a line width below 100 nm and good yield. It is also shown how a very thin organic anti-static layer can be used to avoid charge accumulation on the resist layer during e-beam lithography, which is easy to occur on insulating piezoelectric substrates and results in e-beam deflection. However, it is also shown how the use of this anti-static layer is not required with the insulating piezoelectric layer resting on a semiconducting substrate such as highly doped silicon. The effect of the e-beam dose on insulating and semiconducting layers is also discussed.     

A quick tour on suffix arrays and compressed suffix arrays

Suffix arrays are a key data structure for solving a run of problems on texts and sequences, from data compression and information retrieval to biological sequence analysis and pattern discovery. In their simplest version, they can just be seen as a permutation of the elements in {1,2,…,n}, encoding the sorted sequence of suffixes from a given text of length n, under the lexicographic order. Yet, they are on a par with ubiquitous and sophisticated suffix trees. Over the years, many interesting combinatorial properties have been devised for this special class of permutations: for instance, they can implicitly encode extra information, and they are a well characterized subset of the n! permutations. This paper gives a short tutorial on suffix arrays and their compressed version to explore and review some of their algorithmic features, discussing the space issues related to their usage in text indexing, combinatorial pattern matching, and data compression.     

半导体培养箱的ARM嵌入式控制系统研制

针对传统培养箱加热制冷器件能耗高、体积大且温控精度不高的特点,应用热电半导体对培养箱的温度进行调节.采用ARM920T架构的S3C2440AL处理器并配合外围设备,在Linux嵌入式操作系统上进行核心程序研发,并加入模糊自适应PID算法,以实现对培养箱温度的精确控制.试验结果表明,该培养箱的控温相对误差达到±1.1%.     

General-purpose systolic arrays

The extension of systolic array architecture from fixed- or special-purpose architectures to general-purpose, SIMD (single-instruction stream, multiple-data stream), MIMD (multiple-instruction stream, multiple-data stream) architectures, and hybrid architectures that combine both commercial and FPGA (field-programmable gate array) technologies is chronicled. The authors present a taxonomy for systolic organizations, discuss each architecture's methods of exploiting concurrencies, and compare performance attributes of each. The authors also describe a number of implementation issues that determine a systolic array's performance efficiency, such as algorithms and mapping, system integration through memory subsystems, cell granularity, and extensibility to a wide variety of topologies     

Wafer-scale transducer arrays

The production of wafer-scale transducer arrays using laser interconnection techniques and micromatching technology is discussed. The design of a wafer-scale thermal dynamic scene simulator that was implemented using the laser-linking redundancy technique is presented to illustrate typical design requirements. The simulator uses small arrays of thermal pixels and control circuitry in 3 μm CMOS technology     

Hardness results for covering arrays avoiding forbidden edges and error-locating arrays

Covering arrays avoiding forbidden edges (CAFEs) are used in testing applications (software, networks, circuits, drug interaction, material mixtures, etc.) where certain combinations of parameter values are forbidden. Danziger et al. (2009) [8] have studied this problem and shown some computational complexity results. Around the same time, Martinez et al. (2009) [19] defined and studied error-locating arrays (ELAs), which are closely related to CAFEs. Both papers left some computational complexity questions. In particular, these papers showed polynomial-time solvability of the existence of CAFEs and ELAs for binary alphabets (g=2), and the NP-hardness of these problems for g≥5. In this paper, we prove that optimizing CAFEs and ELAs is indeed NP-hard even when restricted to the case of binary alphabets, using a reduction from edge clique covers of graphs (ECCs). We also provide a hardness of approximation result. We explore important relationships between ECCs and CAFEs and give some new bounds for uniform ECCs and CAFEs.     

Zeolite cover layer for selectivity enhancement of p-type semiconducting hydrocarbon sensors

Screen-printed thick films of the p-type semiconducting materials family SrTi_1−xFe_xO_3−δ have been investigated for hydrocarbon sensing. Among the different compositions tested, the formulations containing 10 and 20% of iron are found to perform best for this purpose. A pronounced cross-interference of NO persisted at operating temperatures of about 400 °C. In order to eliminate this problem, the application of a zeolite cover layer was studied. The properties of this cover layer were optimized with respect to layer thickness and Pt content. Using initial results of a catalytic study on the zeolite powder in addition to a simple diffusion–reaction model, the effect of the zeolite layer with respect to NO cross-interference could be explained satisfactorily.     

Digital Fabrication

NNJ editor-in-chief Kim Williams introduces the papers in NNJ vol. 14, no. 3 (Winter 2012).     

Optimal control of photovoltaic arrays

A high value of the energy conversion efficiency is not the only feature a photovoltaic power processing system must have. An optimal control of the photovoltaic generator must be also designed in order to maximize the electrical power it produces, even in presence of a time varying irradiation level or when a part of the photovoltaic source is shaded. An overview of the main issues related to this real time optimization problem is given in this paper and some solutions, both presented in the literature and nowadays provided by leading companies, are overviewed.     

Implementing degradable processing arrays

Today's burgeoning multimedia and network technology require large high-performance processing arrays. Conventional chip packaging and board-level integration cannot meet operating speeds in these high-performance systems. In addition, large systems require technologies that provide reliable, single packaging. The main focus of this work is to demonstrate the feasibility of building reliable systems using MCMs, with special attention to implementation issues. A simple approach employing the gracefully degradable paradigm facilitates the continued operation of a faulty array that the system would otherwise discard. The scheme identifies and makes provision to extract healthy subarrays that retain original topology, and requires a small number of transistor switches. By exploiting various implementation options of MCMs, the technique poses no increase to primary circuit area. We must identify the topology of the system to incorporate the gracefully degrading scheme. An application will dictate the utility derived from various levels of degradation. The scheme has provision for extracting one or two subsystems for continued operation. By following the steps outlined for the tree architecture, it is possible to extend the algorithm to other topologies. The general hardware layout must include switches to provide connectivity between system I/O and all subsystems that can potentially take on the role of a boundary node