Theory and application of charge pumping for the characterizationof Si-SiO2 interface and near-interface oxide traps

A generalized charge pumping model has been developed which extends the use of charge pumping from a study of traps at the Si-SiO ₂ interface to a study of traps in the oxide. The analytical model, based on tunneling theory, allows the spatial distribution of near-interface oxide traps to be determined from variable frequency charge pumping data. Profiling of near-interface oxide traps in irradiated MOSFET's as well as SONOS nonvolatile memory devices is presented     

Profiling of traps in SiO2/Al2O3 gate stack by the charge pumping technique

In this paper, we present our results on the distribution and generation of traps in a SiO₂/Al₂O₃ transistor. The investigation has been carried out by using charge pumping measurements, both variable voltage and frequency techniques, and constant voltage stress.By increasing the amplitude of the gate pulse we observe an increase of the charge recombined per cycle closely related to the contribution of shallow traps near the SiO₂/Al₂O₃ interface. By reducing the pulse frequency we measure an increase in the charge pumping current due to traps located deeper in the Al₂O₃. By combining charge pumping and constant voltage stress measurements, we found that the traps are mostly generated near the Si/SiO₂ interface.     

Non-bulk Si-O bonding at the Si-SiO2 interface

A simple silicon dioxide bonding model is applied to a variety of films and shown to be applicable only for grown layers thicker than about 400 Å, indicating that `non-bulk' bonding is present near to the silicon interface     

Determination of Si-SiO2 interface recombinationparameters using a gate-controlled point-junction diode underillumination

A novel method is presented to determine Si-SiO₂ interface recombination parameters. The device used is a polysilicon-oxide-semiconductor capacitor with a microscale central junction (a gate-controlled point-junction diode). Data analysis has been performed using a numerical scheme to find a quasi-exact solution for the current combining at the interface. It was found that the interface recombination parameters depend only weakly on trap energy in a wide range around midgap. The cross-section for capturing electrons was found to exceed the cross-section for capturing holes by a factor of 10² to 10³     

The use of charge pumping to characterize generation by interface traps

A small rectangular pulse technique for measuring charge-pumping current has been proposed as a method to characterize interface traps near midgap. It is shown theoretically and experimentally that the small rectangular pulse technique can be used to predict the surface generation current measured on a MOSFET or a gated diode. This new technique has the advantage that the measured current is at least 10 to 100 times larger than the surface generation current.     

A comparative study of depth profiling of interface states using charge pumping and low frequency noise measurement in SiO2/HfO2 gate stack nMOSFETs

Charge pumping and low frequency noise measurements for depth profiling have been studied systematically using a set of gate stacks with various combinations of IL and HfO₂ thicknesses. The distribution of generated traps after HCI and PBTI stress was also investigated. The drain-current power spectral density made up all of the traps of IL in 0 < z < T_IL and the traps of HfO₂ in T_IL < z < T_HK. The traps near the Si/SiO₂ interface dominated the 1/f noise at higher frequencies, which is common in SiO₂ dielectrics. For the HfO₂/SiO₂ gate stack, however, the magnitude of the 1/f noise did not significantly change after HCI and PBTI because of more traps in the bulk HfO₂ film than at the bottom of the interface.     

Lateral profiling of interface traps and oxide charge in MOSFETdevices: charge pumping versus DCIV

An improved oxide-charge and interface-trap lateral profiling charge pumping technique (iLPCP) is described. Erase-induced oxide charge and interface traps are investigated in flash EPROM devices. It is shown that the improved technique allows the extraction of profiles in cases where the previous method does not yield satisfactory results. A comparative study of iLPCP and of an existing direct current (DCIV) technique for lateral profiling of interface traps is conducted: both erase- and program-induced interface traps are investigated in flash EPROM devices. The results indicate that 1) iLPCP probes a much bigger portion of the gate region; 2) iLPCP probes a wider energy range; 3) DCIV is more sensitive deep in the channel and thus complements iLPCP     

Avalanche electron injection in 4-nmSi3N4/8-nm SiO2 dielectric structure:turn-around phenomenon and Si-SiO2 interface degradation

Charge trapping and interface-state generation in very thin nitride/oxide (4-nm Si₃N₄+8-nm SiO₂) composite gate insulators are studied as a function of gate electrode work function and bottom oxide thickness. The behavior of the trapped positive charge under bias-temperature stress after avalanche electron injection (AEI) is investigated. Evidence is presented that secondary hole injection from the anode (gate/Si₃N₄ interface) and subsequent trapping near the SiO₂-Si interface result in a turnaround of the flatband voltage shift during AEI from the substrate. Just like the thermal oxides on Si, slow-state generation near the SiO₂-Si interface and boron acceptor passivation in the surface-space charge layer of the Si substrate are also observed after AEI in these nitride/oxide capacitors, and they are found to be strongly related to the secondary hole injection and trapping. Finally, interface-state generation can take place with little secondary anode hole injection and is enhanced by the occurrence of hole trapping     

Detailed analysis of charge pumping and IdVg hysteresis for profiling traps in SiO2/HfSiO(N)

By scanning 1/3 nm SiO₂/HfSiO(N) gate dielectrics with variable t_charge−t_discharge amplitude charge pumping technique (VT²ACP) and slow rate I_dV_g hysteresis, we study in detail the energy profile and estimate the spatial position (within SiO₂ or HKs layer) of pre-stress and stress-induced electron traps. Pre-stress traps are mainly at shallow energy levels while stress-induced traps are at deeper energy levels. We demonstrate that due to incomplete discharge of bulk traps, the commonly-used base level charge pumping (CP) sweep is not suited for trap energy profiling. Further, we show that in CP measurements, due to the non-negligible tail of the filling probability of traps, even at short charge times, a fraction of HK-bulk traps is scanned in addition to interfacial traps. When the trap density in the HK is significantly higher than in the IL, this fraction might dominate the CP signal and can cause misinterpretation of data. Finally, we point out the possible contribution of the initially-present traps in the formation of a percolation path causing the dielectric breakdown.     

The influence of mobile ions on the Si/SiO2 interface traps

An investigation of the relation between mobile ions and interface traps was carried out, using an appropriate technique to determine the number and type of mobile ions. It was found that mobile ions do not cause interface traps in the middle 0.8 eV of the bandgap. It appears that interface traps are rather caused by some stress effect. The results are considered in light of previously reported work.     

Determination of the Si-SiO2 barrier height from theFowler-Nordheim plot

It is shown that, even considering a field-dependent Si-SiO₂ barrier height for electron tunneling as predicted by the quantum-mechanical (QM) modeling of Si-SiO₂ interfaces, the Fowler-Nordheim (F-N) plot is linear. It is proved that the equivalent barrier height extracted from the graph slope is not representative of the actual field-dependent barrier. The problem of correctly estimating the oxide field to be used in F-N plots is also addressed     

Characterization of ultra-thin SiO2 by capacitance-voltage and charge pumping measurements

In this paper, we present results on electrical measurements of ultra thin SiO₂ layers (from 3.5 nm down to 1.7 nm), used as gate dielectric in metal-oxide-semiconductors (MOS) devices. Capacitance-voltage (C-V) measurements and simulations on MOS capacitors have been used for extracting the electrical oxide thickness. The SiO₂/Si interface and oxide quality have been analyzed by charge pumping (CP) measurements. The mean interface traps density is measured by 2-level CP, and the energy distribution within the semiconductor bandgap of these traps are investigated by 3-level charge pumping measurements. A comparison of the energy distribution of the SiO₂/Si interface traps is made using classical and quantum simulations to extract the surface potential as a function of the gate signal. When the gate oxide thickness <3.5 nm, we prove that it is mandatory to take into account the quantum effects to obtain a more accurate energy distribution of the SiO₂/Si interface traps. We also explain the increase of the apparent interface traps density measured by 2-levels CP with the increase of the oxide thickness, for transistors made from the same technological process.     

Simulation of a high performance MOSFET with a quantum wirestructure incorporating a periodically bent Si-SiO2 interface

A MOSFET using a serrated quantum wire structure that produces one-dimensional electron confinement shows excellent subthreshold characteristics and enhanced drive capability compared to a conventional MOSFET with a flat Si-SiO₂ interface. We studied the quantum wire structure with its periodically bent Si-SiO₂ interface using simulations. The potential in the convex regions of the silicon is 0.34 V higher than that in the concave ones when the bending angle is 90°, the bending period is 100 nm, substrate doping is 3.0×10 ¹⁷ cm^-3, and a gate voltage is 0.1 V. Because of this increase in potential in the convex regions, electrons are confined in a narrow width of 13 nm in the convex regions. This 1-D electron confinement effect by the bent Si-SiO₂ interface is clearly observed at low gate voltage and is reduced as the gate voltage becomes higher. Due to the confinement effect, drain current in the MOSFET with this quantum wire structure is 270 times higher than that of a MOSFET with a flat Si-SiO₂ interface at a gate voltage of 0.05 V. In addition, the short-channel effect is more effectively suppressed in this MOSFET than in a conventional MOSFET     

Annealing of Si---SiO2 interface states using Ar-ion-implant-damage-gettering

The effectiveness of Ar-ion-implant damage gettering on the Si---SiO₂ interface states has been investigated using MOS techniques and Rutherford backscattering. Silicon wafers of (100) orientation were used in the study. Some wafers were intentionally contaminated with Au and then Ar-ion-implant was performed on the back surface and the damaged layer subsequently annealed at 1050°C for times of 15 and 60 min in a nitrogen ambient. The quasi-static I–V technique of Kuhn was used to obtain experimental curves which were correlated with the theory to extract the interface state density and distribution. The effectiveness of Ar-ion-implant in removing Au from the interface is clearly demonstrated by the structure of the quasi-static I–V curves. Rutherford backscattering of ¹⁴N⁺ ions was carried out on the wafers indicating that the removal of gold from the interfacial traps is associated with its removal from the bulk.     

Profiling of stress induced interface states in short channel MOSFETs using a composite charge pumping technique

The charge pumping phenomenon is studied and the limits of validity of different experimental alternatives are analysed, taking into consideration emission processes and short channel effects. As a result, a composite charge pumping technique, which can accurately give the energy distribution of interface state densities in short channel MOSFETs, is proposed. The experiment is based on the successive variation of the gate voltage pulse parameters (top and bottom levels, rise and fall times) at room and low temperatures. This method is then applied to study aging effects due to channel hot electron injection. The comparison of the experimental energy profile determined before and after electrical stress shows a global increase of interface states, which is more pronounced near the conduction band edge.     

Electrical characterization of Al-SiO2-Si (N-type) tunnel structures. Influence of LPCVD and LPO2 oxide growth technologies on the properties of the Si-SiO2 interface

Metal-thin oxide-silicon tunnel diodes are studied. Two kinds of thin oxides (thickness $\text{δ < 30}\text{A}\text{?}$) are examined. The first fabricated by oxidation under low oxygen pressure (LPO₂) at $\text{t?950°}\text{C}$). The second fabricated by low pressure chemical vapor deposition (LPCVD) at $\text{T?880°}\text{C}$. Besides, the influence of thermal annealing of these devices has been studied. (I, V), C(V, ω) and G(V, ω) experimental characteristics are analysed and compared with theoretical (I, V) curves issued from a detailed and original model. Interface states energy distribution N_ss (E) surface potential V_s vs applied voltage V_a, effective affinities x_n and x_p and oxide thickness homogeneity are deduced. The influence of pinholes is also discussed.It is worth noticing the complementarity of experimental results and the theoretical (I, V) simulation.LPCVD oxides after annealing are found to be more homogeneos and provide a lower density N_ss (E) of interface states than LPO₂ thin oxides.     

Determination of Si/SiO2 interface roughness using weaklocalization

The interface roughness of intentionally textured Si/SiO₂ interfaces was measured using the quantum weak localization (WL) correction to the electrical conductivity at low temperatures. The deduced roughness was confirmed by observation of the Si surface replicas by atomic force microscopy (AFM). Quantitative agreement between the two methods was found (Δ=1.2 to 1.4 Å from WL and 1.35 Å from AFM). For a surface with artificially induced texture, it is found that WL can easily distinguish a significant increase in roughness relative to the smooth surfaces. AFM confirms this qualitative conclusion     

Distribution and generation of traps in SiO2/Al2O3 gate stacks

In this work we combine charge-pumping measurements with positive constant voltage stress to investigate trap generation in SiO₂/Al₂O₃ n-MOSFET. Trap density has been scanned either in energy or in position based on charge-pumping (CP) measurements performed under different operating conditions in terms of amplitude and frequency of the gate pulse. Our results have revealed that the traps are meanly localized shallow in energy level, deeper in spatial position and they are mostly generated near the Si/SiO₂ interface.     

Effects of the metal gate on the stress-induced traps in Ta2O5/SiO2 stacks

The degradation of Ta₂O₅-based (10 nm) stacked capacitors with different top electrodes, (Al, W, Au) under constant current stress has been investigated. The variation of electrical characteristics after the stress is addressed to gate-induced defects rather than to poor-oxidation related defects. The main wearout parameter in Ta₂O₅ stacks is bulk-related and a generation only of bulk traps giving rise to oxide charge is observed. The post-stress current–voltage curves reveal that stress-induced leakage current (SILC) mode occurs in all capacitors and the characteristics of pre-existing traps define the stress response. The results are discussed in terms of simultaneous action of two competing processes: negative charge trapping in pre-existing electron traps and stress-induced positive charge generation, and the domination of one of them in dependence on both the stress level and the gate used. The charge build-up and the trapping/detrapping processes modify the dominant conduction mechanism and the gate-induced defects are precursors for device degradation. It is concluded that the impact of the metal gate on the ultimate reliability of high-k stacked capacitors should be strongly considered.