Packaging effects on reliability of Cu/low-k interconnects

Chip-packaging interaction is becoming a critical reliability issue for Cu/low-k chips during assembly into a plastic flip-chip package. With the traditional TEOS interlevel dielectric being replaced by much weaker low-k dielectrics, packaging induced interfacial delamination in low-k interconnects has been widely observed, raising serious reliability concerns for Cu/low-k chips. In a flip-chip package, the thermal deformation of the package can be directly coupled into the Cu/low-k interconnect structure inducing large local deformation to drive interfacial crack formation. In this paper, we summarize experimental and modeling results from studies performed in our laboratory to investigate the chip-package interaction and its impact on low-k interconnect reliability. We first review the experimental techniques for measuring thermal deformation in a flip-chip package and interfacial fracture energy for low-k interfaces. Then results from three-dimensional finite element analysis (FEA) based on a multilevel submodeling approach in combination with high-resolution moire/spl acute/ interferometry to investigate the chip-package interaction for low-k interconnects are discussed. Packaging induced crack driving forces for relevant interfaces in Cu/low-k structures are deduced and compared with corresponding interfaces in Cu/TEOS and Al/TEOS structures to assess the effect of ILD on packaging reliability. Our results indicate that packaging assembly can significantly impact wafer-level reliability causing interfacial delamination to become a serious reliability concern for Cu/low-k structures.     

Interface reliability assessments for copper/low-k products

Multiple new materials are being adopted by the semiconductor industry at a rapid rate for both semiconductor devices and packages. These advances are driving significant investigation into the impact of these materials on device and package reliability. Active investigation is focused on the impact of back-end-of-line (BEOL) processing on Cu/low-k reliability. This paper discusses Cu/low-k BEOL interfacial reliability issues and relates key items from the assembly process and packaging viewpoint that should be managed in order to prevent adverse assembly impact on BEOL interfacial reliability. Reliability failure mechanisms discussed include interface diffusion-controlled events such as the well-known example of Cu electromigration (EM), as well as stress-migration voiding. Interface defectivity impact on dielectric breakdown and leakage is discussed. Lastly, assessments of assembly impact on these Cu/low-k interfacial concerns are highlighted.     

Interlevel dielectric failures in copper/low-k structures

Failure modes for inter-level dielectric layers under accelerated test conditions have been evaluated for a range of dielectric diffusion barriers in copper/low-k structures. The dominant failure mechanism for both constant voltage tests and ramped voltage tests was mechanical cracking at the dielectric barrier/low-k interface. Few occurrences of copper diffusion through the bulk ILD were observed. A simple model for the dominant failure mechanism is proposed which hypothesizes crack formation due to the electrostatic force between interdigitated lines followed by copper extrusion into the cracks. The proposed model is consistent with measurements of interfacial adhesion strengths in Cu/low-k stacks.     

Dynamic study of the physical processes in the intrinsic line electromigration of deep-submicron copper and aluminum interconnects

Various physical mechanisms are involved in an electromigration (EM) process occurring in metal thin film. These mechanisms are electron-wind force induced migration, thermomigration due to temperature gradient, stressmigration due to stress gradient, and surface migration due to surface tension in the case where free surface is available. In this work, a finite element model combining all the aforementioned massflow processes was developed to study the behaviors of these physical mechanisms and their interactions in an EM process for both Al and Cu interconnects. The simulation results show that the intrinsic EM damage in Al is mainly driven by the electron-wind force, and thus the electron-wind force induced flux divergence is the dominant cause of Al EM failure. On the other hand, the intrinsic EM damage in Cu is driven initially by the thermomigration, and the electron-wind force dominates the EM failure only at a latter stage. This shows that the early stage of void growth in Cu interconnects is more prone to thermomigration than Al.     

Investigation of dielectric/metal bilayer sidewall diffusion barrier for Cu/porous ultra-low-k interconnects

A dielectric/metal bilayer structure of a-SiC:H/Ta was integrated and investigated for application as a sidewall diffusion barrier in a Cu/porous ultra-low-k interconnect structure. Different dielectric/metal bilayer thicknesses were investigated. The electrical tests and physical analyses indicate that this a-SiC:H/Ta bilayer structure is a more efficient sidewall diffusion barrier than the conventional physical vapor deposited (PVD) multistack TaN/Ta metal barrier. With a similar total sidewall barrier thickness, an even better barrier integrity and reliability can be achieved by using a thicker a-SiC:H layer and a correspondingly thinner Ta barrier. This achievement is mostly attributed to the surface modification and sealing of the porous ultra-low-k surface by the a-SiC:H layer. Thus, the scenario of the barrier failure due to defects in the Ta (or TaN) barrier layer directly deposited on rough porous ultra-low-k material is avoided. Bias-temperature stress (BTS) and time-to-failure (TTF) studies indicate the Copper penetration through the sidewall barrier into the porous dielectric was the dominating failure mechanism in the conventional PVD TaN/Ta barrier and bilayer barrier of thinner a-SiC:H (14 /spl Aring/) and thicker Ta (71 /spl Aring/) layers, although the latter enhanced the lifetime of interconnect structures considerably. The bilayer barrier consisting of a thicker a-SiC:H (60 /spl Aring/) and correspondingly thinner Ta (53 /spl Aring/) layers was more robust to protect the sidewall region so that this sidewall Cu diffusion induced failure mechanism was no longer found in Cu/porous ultra-low-k interconnect structures even after thermal stress at 200/spl deg/C for 120 h.     

Initiation and propagation of delaminations at the underfill/passivation interface relevant to flip-chip assemblies

A crucial reliability issue for flip-chip microelectronic assemblies is the mechanical integrity of the various bi-material interfaces present. Understanding the mechanics and physics of adhesion is continually reiterated in the International Technology Roadmap for Semiconductors (ITRS). With current trends in the microelectronics industry pushing for smaller and smaller feature sizes, small-scale delamination and initiation are becoming more of a focus in adhesion studies. Our work looks at the application of a stress singularity approach to the initiation problem at various geometric singularities found at interfaces in flip-chip assemblies. Moreover, we compare the adhesion of the same interfaces using standard fracture mechanics. Specifically, several underfill/polyimide interfaces are tested, in both a standard double cantilever beam geometry and a tensile butt joint geometry. The results show a direct correlation between stress intensity values for both the initiation of delaminations and the propagation of existing delaminations. Modified tensile butt joint geometry testing shows an inverse relationship between singularity strength and overall joint strength.     

板级互连线的串扰规律研究与仿真

串扰是高速电路板设计中干扰信号完整性的主要噪声之一;为有效地抑制串扰噪声,保证系统设计的功能正确,有必要分析串扰问题。针对实际PCB中互连线拓扑和串扰的特点,构建三线耦合均匀传输线模型,采用信号完整性仿真工具HyperLynx进行PCB布线前的LineSim串扰仿真,详细分析了高速PCB中多种因素：耦合长度、耦合间距、信号上升时间、介质厚度、端接等对近端和远端串扰宽度和幅值的影响;最后总结了串扰宽度及其幅值的变化规律,可有效的指导PCB设计中减小串扰噪声。     

高速互连系统的串扰激励测试压缩算法研究

信号完整性中的串扰已经成为了高速互连系统中不容忽视的问题,并为测试领域带来了新的挑战。本文通过对串扰耦合机理的分析,提出了串扰的最大攻击性、对称性、衰减性及叠加性等特性,并依据这些性质,在不改变空间性质的情况下对最大攻击者模型的测试矢量集进行了压缩,同时为了验证该算法的正确性,在HSPICE下对不同的故障测试模型进行了仿真实验,实验结果表明本文的压缩算法对MA模型的矢量空间可大大减少,从而可以节省测试时间,提高测试效率,表明了该算法的有效性与优越性。     

Crosstalk overshoot/undershoot analysis and its impact on gate oxide reliability in multi-wall carbon nanotube interconnects

The work in this paper analyzes the crosstalk effects in Multi-wall Carbon Nanotube (MWCNT) based interconnect systems, and its impact on the reliability of the gate oxide of MOS devices. The electrical circuit parameters for interconnect are calculated using the existing models of MWCNT and the equivalent circuit has been developed to perform the crosstalk analysis. The crosstalk induced overshoot/undershoots have been estimated and the effect of the overshoot/undershoots on the gate oxide reliability is calculated in terms of failure-in-time (FIT) rate of the MOS devices. Single, double, and bundle of MWCNTs are considered for the analysis. The results are compared with that of traditional Cu based interconnects. It has been found that the average failure rate due to crosstalk overshoot/undershoots is ??10 to 100 times less in MWCNT based interconnect of length between 10 ??m to 50 ??m as compared to the copper based interconnects. Our analysis shows the applicability of MWCNTs in future VLSI circuits from the perspective of gate oxide reliability. The results also reveal that single or double MWCNT of large diameter is better than bundle of MWCNTs of smaller diameter.     

LED封装技术的比较

LED封装的作用是将外引线连接到LED芯片的电极上，LED封装不仅仅只是完成输出电信号，更重要的是保护管芯正常工作，输出可见光的功能，而且起至班组高发光效率的作用。无论何种LED都需要针对不同类型设计合理的封装形式，因为只有封装好的才能成为终端产品，才能投入实际应用。     

Analysis of a temperature-dependent delay optimization model for GNR interconnects using a wire sizing method

A temperature-dependent delay optimization model for a multilayered graphene nanoribbon (MLGNR) with top contact (TC-GNR), side contact (SC-GNR), and Cu-based nano-interconnects using a wire sizing method was applied to determine the delay for different interconnects widths (11 nm, 16 nm, and 22 nm) and lengths (10 μm, 50 μm, and 100 μm), being the first such model for TC-GNR, SC-GNR, and Cu interconnects applied at three different chip operating temperatures (233 K, 300 K, and 378 K). The results reveal that the SC-GNR requires ~ 3–6× and ~ 2–3× fewer repeaters w.r.t. the TC-GNR or Cu interconnect, and that the SC-GNR and Cu interconnects can achieve ~ 4–5× and ~ 2–2.5× reduction in repeater dimension compared with the TC-GNR interconnect. Meanwhile, the SC-GNR interconnect can achieve 73× less propagation delay w.r.t. the TC-GNR interconnect for interconnect width of 22 nm, interconnect length of 10 μm, and two different chip operating temperatures of 233 K and 300 K. Similarly, the Cu interconnect can achieve 6× less propagation delay w.r.t. the TC-GNR interconnect at interconnect width of 22 nm and 16 nm, interconnect length of 10 μm, and 300 K.     

High-speed optoelectronic VLSI switching chip with >4000 opticalI/O based on flip-chip bonding of MQW modulators and detectors tosilicon CMOS

We present the first high-speed optoelectronic very large scale integrated circuit (VLSI) switching chip using III-V optical modulators and detectors flip-chip bonded to silicon CMOS. The circuit, which consists of an array of 16×1 switching nodes, has 4096 optical detectors and 256 optical modulators and over 140K transistors. All but two of the 4352 multiple-quantum-well diodes generate photocurrent in response to light. Switching nodes have been tested at data rates above 400 Mb/s per channel, the delay variation across the chip is less than ±400 ps, and crosstalk from neighboring nodes is more than 45 dB below the desired signal. This circuit demonstrates the ability of this hybrid device technology to provide large numbers of high-speed optical I/O with complex electrical circuitry     

聚苯醚/环氧玻璃布覆铜板的研制

通过对聚苯醚（PPO）/环氧树脂体系固化剂、固化工艺等固化体系的研究，提高了PPO与环氧树脂的相容性，研制开发出介电常数为3.9的低介电常数高频电路用覆铜板。     

酞菁铜衍生物对Li/SOCl2电池性能的影响

合成了酞菁铜[Cu(Ⅱ)Pc]及其衍生物四乙酰胺酞菁铜[Cu(Ⅱ)TcaPc]、四乙酸酞菁铜[Cu(Ⅱ)TcPc]、四吡啶并卟啉铜[Cu(Ⅱ)PTp]和四吡嗪并卟啉铜[Cu(Ⅱ)PTpz],并用元素分析法及红外光谱法进行了研究。通过恒电阻放电实验研究了它们对Li/SOCl2电池放电电压及时间的影响。结果表明:Cu(Ⅱ)PTp及Cu(Ⅱ)PTpz具有较好的催化活性。     

变电站铜材接地网的应用效果分析

对铜与镀锌钢的性能和接地体最小截面进行比较分析;介绍了效果良好的铜接地体的放热火泥熔接的连接方式;提出铜材接地网实施的优化措施,并结合工程实践,对铜材接网及镀锌钢接地网进行了技术经济比较。论证了铜材接地网在技术和经济上的优势。     

中压电缆铜屏蔽层熔断引起事故扩大的分析

通过对上海所属的厦门、四川、海陆 3座变电站的中压电缆故障分析 ,认为铜屏蔽带型电缆一般适用于中性点经小电阻接地系统 ,但不能承受故障大电流。虽然故障大电流发生的概率较小 ,但应引起注意 ,尤其是在制作电缆中间接头时 ,建议恢复铜屏蔽层时采用三相统包绕包 ,同时要使绕包层的截面不小于电缆本体的铜屏蔽层截面 ,并做到与电缆本体铜屏蔽层连接良好     

LED芯片封装缺陷检测方法研究

引脚式LED芯片封装工艺中封装缺陷不可避免,基于p-n结的光生伏特效应和电子隧穿效应,分析了一种封装缺陷对LED支架回路光电流的影响。利用电磁感受定律对LED支架回路光电流进行非接触检测,得到LED芯片功能状态及芯片电极与引线支架间的电气连接情况,并对检测精度的影响因素进行分析。实验表明,该方法具有高检测信噪比,能够实现对封装过程LED芯片功能状态及封装缺陷的检测。计算结果与实验结果较好吻合。     

破损动力电池运输包装的探讨

阐述破损和高危状态的锂电池可能发生的各种危险:高温和热反应、起火爆炸、产生有毒气体和电解液泄漏等;介绍相关的国际规则和正确防范措施;分析国际上先进的防护材料和设备装置,并介绍了多个通过测试和当事国政府批准的案例.探讨国内回收锂电池需要重视的包装原则和要求,以及我国执行批准的方法和路径.     

基于机器视觉的铝塑泡罩药品包装检测研究

针对铝塑泡罩胶囊的颜色、大小和图片噪声等造成检测效果较差问题,提出基于GoogLeNet网络模型的铝塑泡罩胶囊包装缺陷检测方法。首先以药板批号区域为模板,利用归一化积相关灰度匹配法定位待检测药板,然后通过改进的灰度值投影法分割药板的胶囊泡罩区域,制作铝塑泡罩胶囊数据集,对改进的GoogLeNet网络模型进行训练和测试,实现铝塑泡罩胶囊的缺粒、胶囊凹帽,胶囊双帽缺陷识别。实验结果表明,改进的水平-垂直投影算法,对胶囊泡罩区域的分割准确率达到100%,网络对缺陷识别的召回率均在98.64%以上。改进的灰度值投影法算法鲁棒性高,分割效果较好;改进的网络对铝塑泡罩胶囊药板包装缺陷识别准确率相比较其他方法有明显提高,可应用于铝塑泡罩药板包装质检。     

射频/微波及ATE系统的应用、挑战与解决方案(英文)

射频/微波自动测试系统中仪器信号的传输依靠的是信号路由和分布式系统,例如从频谱分析仪和频率合成器到待测设备。系统的设计人员总是背负着系统交付的压力,因此,他们需要尽可能快的设计周期。同时,系统往往规格和要求多样,非常复杂。许多情况下,系统设计需要使用RF界面单元(RFIU)来引导并判定从测试仪器到待测设备的信号,包括衰减、过滤、开关等。然而,一个测试系统通常的需求是要对很多测试单位进行测试,单一信号的RFIU设计并不能满足需要。近年来,商用的设计工具已经进入仪器市场,这些工具集合了诸如:LXI(LAN extensions for Instrumentation)、LVI(Interchangeable Virtual Instrument)等工业标准,为RFIU提供基于商业现成可用(COTS)的基础构架,可以降低定制需求。文章介绍了不同行业的应用案例,自动测试系统(ATE)、射频/微波自动测试系统在其中可用作核心测试界面。文章进一步介绍了一些系统设计人员在系统应用时所面临的的挑战与问题。最后,介绍了如何利用基于LXI的RFIUs,将工业标准系统水平的驱动用于解决所遇到的这些问题,并优化应用性能。最后文章讨论了两个特定案例,一个关于航空电子链路可替代设备测试,另一个关于消费电子产品测试环境。