Analysis and Application of Particular Current Signatures (Symptoms) for Cage Monitoring in Nonsinusoidally Fed Motors With High Rejection to Drive Load, Inertia, and Frequency Variations

In this paper, some original and effective fault indicators for broken-bar detection in power squirrel-cage induction motors are presented. A motor phase-current signature analysis can be performed by evaluating the typical ratios $I_{(7 - 2s)f}/I_{5f}$ and $I_{(5 + 2s)f}/I_{7f}$, $I_{(13 - 2s)f}/I_{11f}$ and $I_{(11 + 2s)f}/I_{13f}$, etc., which appear in the phase-current spectrum of faulted motors fed by nonsinusoidal voltage sources. The main advantages of the new indicators are the following: 1) accentuate insensitivity to disturbs such as load torque, drive inertia, and frequency variations; 2) low dependence with respect to machine parameters (except the pole number); and 3) linear dependence on fault gravity. They can be directly applied on motors fed by open-loop low-switching frequency gate turn-off/thyristor converters. Railway traction drives are possible targets. Application to mains-fed motors can be tried too, if suitable harmonics are present in the plant supply. A detailed analytical formulation for fault indicators is furnished, based on the multiphase symmetrical component theory; theoretical results have been supported by experimental work, performed by using a motor with an appositely prepared cage, and successively, method validation was achieved on three other industrial motors.      

Scaling Properties of $hbox{Ge}$ –$hbox{Si}_{x}hbox{Ge}_{1 - x}$ Core–Shell Nanowire Field-Effect Transistors

We demonstrate the fabrication of high-performance $hbox{Ge}$ –$hbox{Si}_{x}hbox{Ge}_{1 - x}$ core–shell nanowire (NW) field-effect transistors with highly doped source (S) and drain (D) and systematically investigate their scaling properties. Highly doped S and D regions are realized by low-energy boron implantation, which enables efficient carrier injection with a contact resistance much lower than the NW resistance. We extract key device parameters, such as intrinsic channel resistance, carrier mobility, effective channel length, and external contact resistance, as well as benchmark the device switching speed and on/off current ratio.      

Performance of $n$-Type InSb and InAs Nanowire Field-Effect Transistors

The electronic structure of highly scaled InSb and InAs nanowire (NW) field-effect transistors (FETs) is calculated with an eight-band ${bf k} cdot {bf p}$ model. Cross sections of 4 nm or less result in bandgaps of 0.8 eV or more. For these cross sections, all devices are single moded and operate in the quantum capacitance limit. Analytical expressions for the transconductance, cutoff frequency, and gate delay time are presented and compared to numerical results. The dependence of the intrinsic cutoff frequency on drive current is weak, scaling as $sqrt{I_{D}}$ with values in the 4–7 THz range that are good for RF applications. The gate delay times strongly depend on the drive current, scaling as $I_{D}^{-3/2}$ with values ranging from 25 to 132 fs which are competitive for digital applications.      

High-Performance Poly-Silicon TFTs Using a High-$k$ $hbox{PrTiO}_{3}$ Gate Dielectric

In this letter, a polycrystalline-silicon thin-film transistor (poly-Si TFT) with a high- $k$ $hbox{PrTiO}_{3}$ gate dielectric is proposed for the first time. Compared to TFTs with a $hbox{Pr}_{2}hbox{O}_{3}$ gate dielectric, the electrical characteristics of poly-Si TFTs with a $hbox{PrTiO}_{3}$ gate dielectric can be significantly improved, such as lower threshold voltage, smaller subthreshold swing, higher $I_{rm on}/I_{rm off}$ current ratio, and larger field-effect mobility, even without any hydrogenation treatment. These improvements can be attributed to the high gate capacitance density and low grain-boundary trap state. All of these results suggest that the poly-Si TFT with a high- $k$ $hbox{PrTiO}_{3}$ gate dielectric is a good candidate for high-speed and low-power display driving circuit applications in flat-panel displays.      

Optical properties of a GaAlAs superluminescent diode

The optical properties of a GaAlAs superluminescent diode (SLD) are described. The spectra of this device exhibit a large number of longitudinal modes. The coupling efficiency into a 0.23 NA 50 μm diameter graded index fiber is ∼ 30 percent. The current required for constant light output at a temperatureTcan be written asI(T) sim I_{0} cdot exp (T/T_{2})whereT_{2} sim 120K. A model of the SLD is described.     

Integrated Hydrogen-Sensing Amplifier With GaAs Schottky-Type Diode and InGaP–GaAs Heterojunction Bipolar Transistor

New hydrogen-sensing amplifiers are fabricated by integrating a GaAs Schottky-type hydrogen sensor and an InGaP–GaAs heterojunction bipolar transistor. Sensing collector currents ( $I_{rm CN}$ and $I_{rm CH}$) reflecting to $hbox{N}_{2}$ and hydrogen-containing gases are employed as output signals in common-emitter characteristics. Gummel-plot sensing characteristics with testing gases as inputs show a high sensing-collector-current gain $(I_{rm CH}/I_{rm CN})$ of $≫hbox{3000}$. When operating in standby mode for in situ long-term detection, power consumption is smaller than 0.4 $muhbox{W}$. Furthermore, the room-temperature response time is 85 s for the integrated hydrogen-sensing amplifier fabricated with a bipolar-type structure.      

Two-dimensional dynamic analysis of short-channel thin-film MOS transistors using a minicomputer

A computer program is described for simulating two-dimensional thin-film MOS transistors on a minicomputer. Data are presented showing the variation of internal carrier density with time until a steady-state condition is reached. These data show the formation of a drain-induced back channel whose conduction properties depend on the back-channel length and carrier mobility. For channel length below 2.0 µm, the two-dimensional steady-state drain current is shown to fit the expressionI_{D}/W = frac{micro_{0}C_{0}}{L[1+(micro_{0}/upsilon_{s} V_{D}{L})^{2}]^{1/2}}(V_{G} - V_{T} - V_{D/2})V{D}for values of drain voltage below a specific saturation value (V_{DM}); andI_{D}/W = frac{10^{-8)(V_{G} - V_{T})^{1/2}}{(T_{ox})^{1/2}L}.(V_{D} - V_{DM}) + I_{DM}for drain voltages above the saturation value.     

Some integrals involving theQ_Mfunction (Corresp.)

Some integrals are presented that can be expressed in terms of theQ_Mfunction, which is defined as begin{equation} Q_M(a,b) = int_b^{infty} dx x(x/a)^{M-1} exp (- frac{x^2 + a^2}{2}) I_{M-1}(ax), end{equation} whereI_{M-1}is the modified Bessel function of orderM-1. Some integrals of theQ_Mfunction are also evaluated.     

Hot-electron-induced MOSFET degradation at low temperatures

The n-channel LDD MOSFET lifetime is observed to followtau=(A/I_{d})(I_{sub}/I_{d})^{-n}from 77 to 295 K when the device is stressed near the maximum Isub. Here Idis the drain current andAis the proportionality constant. The experimental result indicates thatnis approximately 2.7 and is independent of temperature. However, the proportionality constantAfollowsA = A_{0} exp (-E_{a}/kT), withE_{a} = 39meV. The smaller proportionality constant at low temperatures suggests that hot-electron injection (HEI) degradation is caused by the electron trapping in the oxide.     

Performance Improvement of N-Type $hbox{TiO}_{x}$ Active-Channel TFTs Grown by Low-Temperature Plasma-Enhanced ALD

We report on performance improvement of $n$-type oxide–semiconductor thin-film transistors (TFTs) based on $hbox{TiO}_{x}$ active channels grown at 250 $^{circ}hbox{C}$ by plasma-enhanced atomic layer deposition. TFTs with as-grown $hbox{TiO}_{x}$ films exhibited the saturation mobility $(mu_{rm sat})$ as high as 3.2 $hbox{cm}^{2}/hbox{V}cdothbox{s}$ but suffered from the low on–off ratio $(I_{rm ON}/I_{rm OFF})$ of $hbox{2.0} times hbox{10}^{2}$. $hbox{N}_{2}hbox{O}$ plasma treatment was then attempted to improve $I_{rm ON}/I_{rm OFF}$. Upon treatment, the $hbox{TiO}_{x}$ TFTs exhibited $I_{rm ON}/I_{rm OFF}$ of $hbox{4.7} times hbox{10}^{5}$ and $mu_{rm sat}$ of 1.64 $hbox{cm}^{2}/hbox{V}cdothbox{s}$, showing a much improved performance balance and, thus, demonstrating their potentials for a wide variety of applications such as backplane technology in active-matrix displays and radio-frequency identification tags.      

Hot-carrier-induced degradation in p-channel LDD MOSFET's

When the p-channel MOSFET is stressed near the maximum substrate current Isub, the lifetime t (5-percent increase in the transconductance) followstI_{sub} = A(I_{sub}/I_{d})^{-n}, with n = 2.0. A simple electron trapping model is proposed to explain the observed power law relationship. The current ratioI_{sub}/I_{d}and the maximum channel electric field decrease with increasing stress time, which is consistent with electron trapping in the oxide during the stress.     

Characteristics of I2L at low current levels

The validity of the injection model is assessed in the low power range. Experimental evidence is given that the three base current components (I_{nc}, I_{no}, and Ip) can be determined from a three-gate experiment. The results are explained from the underlying device physics. Experimental data are presented for the temperature dependence of the upward current gain.     

AlGaN/GaN MOSHEMTs With Liquid-Phase-Deposited $ hbox{TiO}_{2}$ as Gate Dielectric

$hbox{TiO}_{2}$ films deposited on GaN layers at room temperature through a simple and low-cost liquid-phase deposition (LPD) method are investigated and served as gate dielectrics in AlGaN/GaN MOSHEMTs. The electrical characteristics of the MOS structure on n-doped GaN show that the leakage current is about $hbox{1.01} times hbox{10}^{-7} hbox{A/cm}^{2}$ at 1 MV/cm and that the breakdown field is more than 6.5 MV/cm. The maximum drain current density of MOSHEMTs is higher than that of conventional HEMTs, and a wider gate voltage swing can also be observed. The maximum transconductance and threshold voltage almost maintain the same characteristics, even after inserting a dielectric layer between the gate metal and the 2DEG channel by using $ hbox{TiO}_{2}$ as a gate dielectric. The gate leakage current density is significantly improved, and the bias stress measurement shows that current collapse is much suppressed for MOSHEMTs.      

A simple method to evaluate device lifetime due to hot-carrier effect under dynamic stress

A method to evaluate hot-carrier-induced NMOSFET degradation under dynamic stress is discussed, based on an empirical relation between device lifetime and substrate current in static stress. The device lifetime τ under dynamic stress is given bytau = A.I_{sub,peak}^{-2.5}/R, whereI_{sub,peak}is the peak value of pulsive substrate current and R is its duty ratio. The device lifetime experimentally obtained in an inverter circuit is in good agreement with the calculation results obtained from the proposed method. This method is useful to estimate device lifetime in actual circuit operational conditions.     

Correlations between reverse recovery time and lifetime of p-n junction driven by a current ramp

When a p-n junction is switched from the forward to the reverse direction by a current ramp, the reverse recovery time trris found 1) either to be equal to the base lifetime τ if the ramp rateR ll I_{F} / tau, 2) to be equal to 0.79τ ifR approx I_{F} / tau, or 3) to be equal to 0.7 τ ifR gg I_{F} / tau. These results afford correlations between τrrand τ and also provide the basis for a useful method for measuring τ.     

A 10-kV Monolithic Darlington Transistor With $beta_{ rm forced}$ of 336 in 4H-SiC

4H-SiC bipolar Darlington transistors with a record-high current gain have been demonstrated. The dc forced current gain was measured up to 336 at 200 $hbox{W/cm}^{2}$ ( $J_{C} = hbox{35} hbox{A/cm}^{2}$ at $V_{rm CE} = hbox{5.7} hbox{V}$) at room temperature. The current gain exhibits a negative temperature coefficient and remains as high as 135 at 200 $^{circ}hbox{C}$. The specific on-resistance is 140 $hbox{m}Omegacdothbox{cm}^{2}$ at room temperature and increases at elevated temperatures. An open-emitter breakdown voltage $(BV_{rm CBO})$ of 10 kV was achieved at a leakage current density of $≪hbox{1} hbox{mA/cm}^{2}$. The device exhibits an open-base breakdown voltage $(BV_{rm CEO})$ of 9.5 kV. The high current gain of SiC Darlington transistors can significantly reduce the gate-drive power consumption with the same forward-voltage drop as that of 10-kV SiC bipolar junction transistors, thus making the device attractive for high-power high-temperature applications.      

High-Density and Low-Leakage-Current MIM Capacitor Using Stacked $hbox{TiO}_{2}/hbox{ZrO}_{2}$ Insulators

We have fabricated high-$kappa hbox{Ni}/hbox{TiO}_{2}/hbox{ZrO}_{2}/ hbox{TiN}$ metal–insulator–metal (MIM) capacitors. A low leakage current of $hbox{8} times hbox{10}^{-8} hbox{A/cm}^{2}$ at 125 $^{circ}hbox{C}$ was obtained with a high 38- $hbox{fF}/muhbox{m}^{2}$ capacitance density and better than the $hbox{ZrO}_{2}$ MIM capacitors. The excellent device performance is due to the lower electric field in 9.5-nm-thick $hbox{TiO}_{2}/ hbox{ZrO}_{2}$ devices to decrease the leakage current and to a higher $kappa$ value of 58 for $ hbox{TiO}_{2}$ as compared with that of $hbox{ZrO}_{2}$ to preserve the high capacitance density.      

A self-consistent model of the lateral behavior of a twin-stripe injection laser

A fully self-consistent computer model of the steady-state behavior of the zero-order lateral optical field of a GaAs twin-stripe injection laser is presented which takes into account current spreading in the p-type confining layer, the effect of lateral diffusion of carriers in the active layer, and bimolecular and stimulated radiative recombination. The results predict the lateral movement of the near field of the optical signal under asymmetric drive conditions, as observed in practice. Also calculated are the corresponding carrier and current density distributions. It is shown that the near-field zero order lateral optical field can be beam steered across the facet by only 2μm, typically. However, the initial position of the beam can be controlled by the two-stripe currents and also the geometry of the device. For the case whereI_{s1} approx I_{s2}the beam movement is seen to be proportional to eitherI_{s1}orI_{s2}. The results show that beam steering is not accompanied by a negative slope to theI-Lcharacteristics. The effect of geometry and diffusion coefficient on the value of maximum current allowed before modal instability occurs is also given.     

A Model for Predicting On-Current Degradation Caused by Drain-Avalanche Hot Carriers in Low-Temperature Polysilicon Thin-Film Transistors

A model for predicting on-current degradation caused by drain-avalanche hot carriers in NMOS low-temperature polysilicon thin-film transistors (TFTs) is described. The amount of trapped charge caused by hot-carrier stress was estimated by using a model describing the lightly doped drain region as an imaginary TFT, and it was found that the amount of trapped charge saturates as voltage-stress time passes. Moreover, the on-resistance increase caused by the trapped charge could be expressed as a function of voltage-stress time $(t)$ , stress drain current $(I_{d_str})$, and stress drain voltage $(V_{d_str})$, i.e., $Delta R_{on} = I_{d_str}exp(-beta / V_{d_str})At^{B}$. This function can be used to predict the on-current degradation of TFTs after a long time for various gate lengths, operation voltages, and crystallinities of polysilicon.      

Demonstration of Tunneling FETs Based on Highly Scalable Vertical Silicon Nanowires

This letter demonstrates a vertical silicon-nanowire (SiNW)-based tunneling field-effect transistor (TFET) using CMOS-compatible technology. With a $hbox{Si} hbox{p}^{+}{-}hbox{i}{-} hbox{n}^{+}$ tunneling junction, the TFET with a gate length of $sim$200 nm exhibits good subthreshold swing of $sim$ 70 mV/dec, superior drain-induced-barrier-lowering of $sim$ 17 mV/V, and excellent $I_{rm on} {-} I_{rm off}$ ratio of $sim!!hbox{10}^{7}$ with a low $I_{rm off} (sim!!hbox{7} hbox{pA}/muhbox{m})$. The obtained 53 $muhbox{A}/muhbox{m} I_{rm on}$ can be further enhanced with heterostructures at the tunneling interface. The vertical SiNW-based TFET is proposed to be an excellent candidate for ultralow power and high-density applications.