A low-power 2.5-GHz 90-nm level 1 cache and memory management unit

The design of a 90-nm virtually addressed cache subsystem with separate 32-kB instruction and data caches is described. The circuits and microarchitecture are illustrated, including architecture level trace data validating low-power features and provisions to support snooping while maintaining the latency and power of virtual addressing. Low-power memory management unit design including a translation lookaside buffer with process identifier mapping is also described. Level 1 caches with support for high bandwidth, single cycle 256 bit fill and evict, as well as features for low power are also described. The design approaches are validated through both simulation and experimental results.     

Measuring the uniqueness and variety of analog circuit design features

Analog circuit design activity is currently a less formalized process, in which the main source for innovation is the designer's ability to produce new designs by combining basic devices, sub-circuits, and ideas from similar solutions. There are few systematic methods that can fuse and transform the useful features of the existing designs into new solutions. Moreover, most automated circuit synthesis tools are still limited to routine tasks, like transistor sizing and layout design. Developing new design techniques that can combine the existing design features requires metrics that describe the uniqueness and variety of the features. This paper evaluates for analog circuits two such general-purpose metrics proposed in [1] and [2]. Three case studies are discussed on using the metrics to characterize the design features of current mirrors, transconductors, and operational amplifiers. The two metrics and the presented study is useful in producing an overall characterization of analog circuit features. This can help in enhancing the circuit design process, training of young designers, and developing new automated synthesis tools that can explore more solution space regions that are likely to include novel design features.     

New statistical features for the design of fiber optic statistical mode sensors

Novel statistical features are proposed for the design of fiber optic statistical mode sensors. The statistical features are radial pth order moments, more precisely first and second order moments. These new features are compared with correlation and image difference features which were reported in the literature earlier. The fiber optic statistical mode sensor experiments are conducted for different applied loads and the corresponding images are captured using the CCD camera. Different statistical features such as image differencing, correlation, first moment and second moment are extracted from the captured images. These features are compared with each other in terms of different characteristics such as precision error, non-linearity, and hysteresis. It is shown that the first and second order moment statistical features are better alternatives for the design of statistical mode sensors, when precision and linearity characteristics are more important than the hysteresis characteristic.     

Coding and modulation for a horrible channel

Designing a system able to cope with a hostile channel is a typical challenge for data communication engineers. High-data-rate communication over power lines is an exemplar case: while power lines are a potentially convenient and inexpensive "no new wire" medium for data transmission, their features make it very difficult to design a simple modem. In this article we illustrate the main features of the power line communication channel, and some of the solutions advocated for modem design.     

Design Considerations for Single-Chip Computers of the Future

In the mid 1980's it will be possible to put a million devices (transistors or active MOS gate electrodes) onto a single silicon chip. General trends in the evolution of silicon integrated circuits are reviewed and design constraints for emeging VLSI circuits are analyzed. Desirable architectural features in modem computers are then discussed and consequences for an implementation with large-scale integrated circuits are investigated. The resulting recommended processor design includes features such as an on-chip memory hierarchy, multiple homogeneous caches for enhanced execution parallelism, support for complex data structures and high-level languages, a flexible instruction set, and communication hardware. It is concluded that a viable modular building block for the next generation of computing systems will be a self-contained computer on a single chip. A tentative allocation of the one million transistors to the various functional blocks is given, and the result is a memory intensive design.     

Hierarchical classifier design in high-dimensional numerous classcases

In applying pattern recognition methods in remote sensing problems, an inherent limitation is that there is almost always only a small number of training samples with which to design the classifier. A hybrid decision tree classifier design procedure that produces efficient and accurate classifiers for this situation is proposed. In doing so, several key questions are addressed, among them the question of the feature extraction techniques to be used and the mathematical relationship between sample size, dimensionality, and risk value. Empirical tests comparing the hybrid design classifier with a conventional single layered one are presented. They suggest that the hybrid design produces higher accuracy with fewer features. The need for fewer features is an important advantage, because it reflects favorably on both the size of the training set needed and the amount of computation time that will be needed in analysis     

超高速移位寄存器单元结构设计方法

本文以高速八位移位寄存器的研制为例,介绍了一种简便可行的专用集成电路单元结构设计方法。专用集成电路的设计目前有很多方法,但都基于有先进的设计工具和较为丰富的集成电路CAD库。没有这些设计环境,使用单元结构设计方法同样可以较快地设计专用集成电路。与通常的设计相比,这种方法具有设计周期短,电路性能高,设计成本低,版图布局对称等特点,是一种较好的专用集成电路设计方法。     

最大中继距离的光网络传输工程设计方法

介绍了最大中继距离的光传输系统设计模型，比较了最坏值设计法、联合设计法和统计设计法三类最大中继距离的光传输系统设计方法的特点，给出了实际可以达到的要生段距离的具体计算方法及其在自愈网、波分复用系统、光放大器、无源光网络及有源光网络工程应用中需要进行的附加修正。     

基于深度学习的僵尸网络检测技术研究

入侵检测系统通过分析网络流量来学习正常和异常行为,并能够检测到未知的攻击。一个入侵检测系统的性能高度依赖于特征的设计,而针对不同入侵的特征设计则是一个很复杂的问题。因此,提出了一种基于深度学习检测僵尸网络的系统。该系统利用卷积神经网络(Convolutional Neural Network,CNN)和长短期记忆网络(Long Short-Term Memory,LSTM)分别学习网络流量的空间特征和时序特征,而特征学习的整个过程由深度神经网络自动完成,不依赖于人工设计特征。实验结果表明,该系统在僵尸网络检测方面具有良好的表现。     

CADRE: An Asynchronous Embedded DSP for Mobile Phone Applications

Asynchronous design techniques have a number of compelling features that make them suited for complex system on chip designs. However, it is necessary to develop practical and efficient design techniques to overcome the present shortage of commercial design tools. This paper describes the development of CADRE (Configurable Asynchronous DSP for Reduced Energy), a 750K transistor, high performance, low-power digital signal processor IP block intended for digital mobile phone chipsets. A short time period was available for the project, and so a methodology was developed that allowed high-level simulation of the design at the earliest possible stage within the conventional schematic entry environment and simulation tools used for later circuit-level performance and power consumption assessment. Initial modeling was based on C behavioral models of the various data and control components, with the many asynchronous control circuits required automatically generated from their specifications. This has enabled design options to be explored and unusual features of the design, such as the Register Bank which is designed to exploit data access patterns, are presented along with the power and performance results of the processor as a whole.     

On the capacity of associative memories with linear thresholdfunctions

Some important features of various known constructions of associative memories based on linear threshold functions are analyzed. Two important features are dealt with: (a) the ability to select an arbitrary set of desired memory vectors and design a network for this set; (b) the sizes and shapes of the domains of attraction of the desired memory vectors and their relation to various design parameters. The static capacity for randomly chosen desired memories is also analyzed. Two extremal examples of sets of desired memories are then analyzed in detail. For spectral schemes with randomly chosen O[N /ln N] memories, it is shown that almost all of the Hamming sphere around each memory is directly attracted     

Log domain filtering for RF applications

A new second-order log filter topology, which is particularly useful for RF signal processing, is introduced with a discussion of how its features meet the needs of RF design. The design concept behind log filters is reviewed. Simulation and experimental results on a test IC are presented for an electronically tunable filter which operates beyond 400 MHz, with Q's in excess of 60, using the AT&T CBIC-V2 process     

Technical Challenges for Designing Personal Digital Assistants

Personal Digital Assistants are battery powered portable computing devices that are targeted to the horizontal consumer market. These products contain more features than laptop computers in a much smaller form factor and with more intense price pressure. This paper will use the Apple Newton MessagePad and the Motorola Envoy to frame consideration of the design tradeoffs involved with Personal Digital Assistants. The issues considered include mechanical engineering and industrial design, analog I/O, display technology and power supply design. Each of these concerns is considered in the context of four key design criteria: low cost, small size and weight, advanced features, and long battery life. The MessagePad and Envoy indicate that a range of engineering choices exists and effective system design requires closely integrated optimization across multiple engineering disciplines.     

The Test Engineer's Assistant: a design environment for testableand diagnosable systems

The Test Engineer's Assistant (TEA) is a set of computer-aided design (CAD) tools that helps the system design engineer meet testability requirements by construction. TEA addresses system design for testability at all levels of the design hierarchy, the lowest level being the board level. The design is represented as a graph where each node indicates a hardware component (or chip on a board) and each arc represents intercomponent connections. Attributes associated with the graph nodes and a set of rules and testing techniques that are incorporated in the tool databases are used to determine the design features that have to be incorporated into the design to meet test and diagnostic requirements. The tool operates on a design using a combination of algorithmic and heuristic techniques. The authors present the design methodology supported by TEA, discuss the techniques used by the TEA tools to obtain solutions for different design for testability requirements, and present an example of the use of TEA with a real system     

Novel slot spiral antenna designs for dual-band/multiband operation

New applications for wireless communications are typically accompanied by a need for antennas that integrate several frequencies and functionalities under a single aperture. Different requirements for pattern, gain, and polarization at each operating frequency further complicate the design of such antennas. Novel slot spiral antenna designs for dual-band/multiband operation are introduced. Typically excited to operate in the first mode, the proposed two-arm slot spiral is redesigned to operate efficiently in the second mode and in a hybrid first/second mode for better functionality. Several key features are introduced to achieve requirements for impedance matching, pattern, and gain suitable for a specific automotive dual-band DAB/SDARS (digital audio broadcasting/satellite digital audio radio services) antenna system. Among these features are new feeding systems, a suitable mix of spiral growth rates, and a low-loss spiral arm termination. The design is accomplished using full-wave finite-element boundary integral simulations and is verified with measurements.     

基于1090ES的机载ADS-B设备总体设计

介绍了1090ES ADS-B系统组成和信号格式,提出了一种基于1090ES一次变频的超外差中频数字化ADS-B设备总体实现方案,包括天线、收发分机、终端分机和机内测试电路设计,计算了关键技术参数,并简述了其主要技术特征.该方案目前已在工程中得到应用,效果良好.     

高保真扬声器系统设计的探索

综合利用客观的测量结果、计算机模拟分析结果和主观的听感音质评价结果,进行了一个二分频高保真扬声器系统的设计。探索以主观听感的艺术性要求去进行高保真扬声器系统的技术性设计,追求艺术与技术的相互结合。     

A 45° dual dipole decomposition scheme to improve image fidelity

Dipole exposure techniques are currently being explored as alternatives to the low k1 problem that hinders the manufacture of sub 100 nm logic technology. Recently, there has been a great deal of interest in using a combination of vertical and horizontal dipole exposures capable of producing manufacturing-robust image results for Manhattan features. In this technique, a design is split into two complementary masks that have enhanced contrast at a given dipole imaging condition. The dipole is a strong case of off-axis illumination, and significant resolution enhancement can be achieved, but only for one pattern direction. Complementary dipole exposures are required when dense pitches in horizontal and vertical direction are present. Dipole decomposition approaches that separate vertical and horizontal features in a layout are based on the fact that horizontal features form an improved aerial image with a vertical dipole illumination, and vertical features show the same aerial image improvement with a horizontal dipole illumination. This technique, though conceptually simple, requires a computer algorithm to decompose a design layout into two patterns consisting of features oriented mainly in the horizontal and vertical directions. Some layout features, landing pads or angled lines for example, cannot easily be assigned to a particular mask based on this simple orientation logic. In this work a new approach has been presented in which 45° decomposition of the pattern is used to improve image contrast, pattern fidelity and focus behavior. The results will be analyzed in terms of contrast, pattern fidelity and focus dependence in order to determine the feasibility of printing manhattan and angled features using a dual dipole approach for sub 100 nm processes.     

一种雷达伺服系统负载模拟装置

介绍一种雷达伺服系统负载模拟装置的设计，对性能优异的磁粉离合器加载装置的特点和高精度的轴角编码显示器作重点介绍，并给出在雷达伺服系统中应用的某些实例。     

一种基于视觉感知的舰船目标智能化识别方法

为有效识别视觉系统采集的可见光图像中的舰船目标,提出了基于YOLO（You Only Look Once）网络模型改进的10层的卷积神经网络（Convolutional Neural Network,CNN）用于水面舰船目标的智能识别,通过反卷积的方法可视化CNN中不同卷积层提取到的舰船目标特征。按照传统目标识别方法提取了舰船目标的四类典型人工设计特征,将所提CNN的舰船目标识别结果与YOLO网络模型及四类人工设计特征结合支持向量机用于舰船目标识别的结果进行比较。实验结果表明,与YOLO网络模型相比,综合精确率、召回率和效率3个舰船目标识别的性能指标,改进后的CNN性能更好,从而验证了所提方法的有效性。不同数据量下采用典型特征识别舰船目标与基于深度CNN识别舰船目标的识别结果比较说明了不同类型目标识别算法的优劣势,有利于推动综合性视觉感知框架的构建。