A novel treatment technique for DMSO wastewater

We have developed an efficient treatment technique for wastewater containing dimethyl sulfoxide [DMSO, (CH₃)₂SO], a compound used as a photoresist stripping solvent in semiconductor manufacturing processes. Generally, wastewater containing organic compounds can be treated biologically, but with DMSO wastewater, biological treatment is not available because noxious compounds are produced that harm the environment. Here, we present an effective DMSO wastewater treatment technique in which we add an oxidizing agent and irradiate the wastewater with ultraviolet light to prevent damage to the environment. The use of hydrogen peroxide (H₂O₂) as an oxidizing agent in combination with ultraviolet irradiation causes DMSO to decompose promptly into methanesulfonic acid (MSA, CH₃SO₂OH). With continued treatment, the resultant MSA decomposes gradually into the inorganic compound sulfuric acid (H ₂SO₄). In this reactive route, no noxious compounds are generated. We confirmed that MSA can be biologically treated comparatively easily, and that by combining the initial ultraviolet irradiation/H₂O₂ addition treatment to rapidly produce MSA with a biological treatment to convert the MSA to H ₂SO₄, the total processing can be treated at very low cost. These treatment techniques make use of the characteristically high reactivity of DMSO and are very effective as a means of treating DMSO wastewater     

Enhanced H2-plasma effects on polysilicon thin-filmtransistors with thin ONO gate-dielectrics

This letter reports that passivation effects of the H₂-plasma on the polysilicon thin-film transistors (TFT's) were greatly enhanced if the TFT's have a thin Si₃N₄ film on their gate-dielectrics. Compared to the conventional devices with only the SiO₂ gate dielectric, the TFT's with Si ₃N₄ have much more improvement on their subthreshold swing and field-effect mobility after H₂-plasma treatment     

Planarization of dielectric layers for multilevel metallization

A process to planarize low-pressure chemical-vapor deposition (LPCVD) SiO₂ films formed over the abrupt topography of fine-line (2.0-μm pitch) integrated circuits with two levels of metallization and pillar interconnections has been developed with sacrificial photoresist and plasma etching using response-surface methodology. To produce flat dielectric surfaces with this topography, the ratio of the measured etch rate of photoresist to that of phosphorus-doped SiO₂ must be maintained at ~0.4 (3800 and 9100 Å/min, respectively) with an Ar/CF₄/O₂ high pressure plasma generated in a low radio-frequency etching system     

Fabrication of low dielectric constant materials for ULSImultilevel interconnection by plasma ion implantation

High dose-rate plasma ion implantation (PII) has been utilized to produce low dielectric constant (k) SiO₂ films for high quality interlayer dielectrics. The SiO₂ films are fluorine-doped/carbon-doped by PII with CF₄ plasma in an inductively-coupled plasma (ICP) reactor. It is found that the use of CF ₄ doping results in exceptional dielectric properties which differ significantly from fluorinated SiO₂. The dielectric constant of the SiO₂ film is reduced from 4.1 to 3.5 after 5 minute PII, other electrical parameters such as bulk resistivity and dielectric breakdown strength are also improved     

Plasma Etching for Sub-45-nm TaN Metal Gates on High-k Dielectrics

Etching of TaN gates on high-k dielectrics (HfO₂ or HfAlO) is investigated using HBr/Cl₂ chemistry in a decoupled plasma source (DPS). The patterning sequence includes 248-nm lithography, plasma photoresist trimming, etching of a SiN-SiO₂ hard mask, and photoresist stripping, followed by TaN etching. TaN etching is studied by design of experiment (DOE) with four variables using a linear model with interactions. It is found that at a fixed substrate temperature and wafer chuck power, etch critical dimensions (CD) gain decreases with decreasing HBr/Cl₂ flow rate ratio and pressure and with increasing source power and total gas flow rate. Based on these DOE findings, subsequent optimization is performed and a three-step etching process is developed; a main feature of the process is progressively increasing HBr/Cl₂ flow rate ratio. The optimized process provides etch CD gain within 2 nm and gate profile close to vertical and reliable etch-stop on high-k dielectric. This process is successfully applied to the fabrication of the 40-nm HfAlO/TaN gate stack p-MOSFETs with good electrical parameters     

H2/O2 plasma on polysilicon thin-filmtransistor

It is reported for that H₂ plasma followed by O₂ plasma is more effective for passivating grain boundary states in polysilicon thin film. Polysilicon thin-film transistors (TFTs) made after H₂/O₂ plasma treatment can exhibit a turn-on threshold voltage of -0.1 V, a subthreshold swing of 0.154 V/decade, an ON/OFF current ratio I_on/I_off over 1×10⁸, and an electron mobility of 40.2 cm² /V-s     

Plasma-charging effects on submicron MOS devices

Plasma-charging damage on gate dielectrics of MOS devices is an important issue because of shrinking dimension, plasma nonuniformity, and effects on high-k gate dielectrics. A comprehensive study of plasma-charging effects on the electrical properties of MOS devices was investigated in this work. Shunt diodes were used to estimate the charging polarity distribution. For high-frequency application, the 1/f noise was found to be a promising index for assessing plasma-charging damage. Gate oxynitride formed by two-step nitridation was demonstrated to have better electrical reliability as compared to the conventional one-step nitridation, especially accompanied by amorphous silicon gate electrode. This improvement could be attributed to the relaxation of interface stress by amorphous silicon gate electrode and the suppression of hydrogen effects by gate oxynitride using two-step nitridation. Plasma-charging damage on Si₃N₄ and Ta₂O₅ gate dielectrics with high dielectric constant was also investigated. For MOS devices with Si₃N₄ film, the leakier characteristic and shorter time to breakdown reveal its inferior reliability. For MOS devices with Ta₂O₅ gate dielectric, the trap-assisted current mechanism makes a thicker physical thickness of Ta₂O₅ film more susceptible to plasma-charging-induced damage. Smaller physical thickness of Ta₂O₅ film in MOS devices is favorable due to the better reliability and comparable plasma-induced electrical degradation     

Conduction mechanisms in barium tantalates films and modificationof interfacial barrier height

The leakage current-voltage characteristics of rf-magnetron sputtered BaTa₂O₆ film in a capacitor with the top aluminum and the bottom indium-tin-oxide electrodes have been investigated as a function of applied field and temperature. In order to study the effect of the surface treatment on the electrical characteristics of as-deposited film we performed an oxygen plasma treatment on BaTa₂O₆ surface. The dc current-voltage, bipolar pulse charge-voltage, dc current-time, and small ac signal capacitance-frequency characteristics were measured to study the electrical and the dielectric properties of BaTa₂O ₆ thin film. All of the BaTa₂O₆ films in this study exhibited a low leakage current, a high breakdown field strength (3-4.5 MV/cm), and a high dielectric constant (20-30). From the temperature dependence of the leakage current, we could conclude that the dominant conduction mechanism under high electrical fields (>1 MV/cm) is ascribed to the Schottky emission while the ohmic conduction is dominant at low electrical fields (<1 MV/cm). Furthermore, the oxygen plasma treatment on the surface of as-deposited BaTa₂O ₆ resulted in a lowering of the interface barrier height and thus, a reduction of the leakage current at Al under a negative bias. This can be explained by the formation of Ba-rich metallic layer by surface etching effect and by filling the oxygen vacancies in the bulk     

Plasma charging damage on MOS devices with gate insulator ofhigh-dielectric constant material

Plasma charging effects on the gate insulator of high-dielectric constant (k) material in MOS devices deserve to be investigated because of different trap-assisted conduction mechanisms. Plasma-induced degradation in gate-leakage current and time to breakdown is clearly observed in this work. MOS device with Si₃N₄ film seems to have smaller degradation of gate-leakage current while it suffers shorter time to breakdown as compared to Ta₂O₅ samples. For devices with Ta₂O₅ film, a larger physical thickness suffers more reliability degradation from plasma charging damage because of the richer traps. Thus, a smaller physical thickness of high-k dielectric film is favorable for sub-micron MOS devices of ULSI application     

Challenges of back end of the line for sub 65 nm generation

This paper presents a review of interconnect challenges for sub 65 nm node. From this generation, porous ultra low K (ULK) dielectric materials (dielectric constant k<2.1) are required. Their porosity makes integration very difficult, due to the mechanical weakness and process interaction issues (especially during stripping, CVD metal barrier deposition…). To overcome these process incompatibilities and keep the ‘effective dielectric constant’ low, dual damascene architecture becomes more and more complex and requires additional steps (porosity sealing treatment, degas steps, supercritical CO₂ clean, low k dielectric barrier, self aligned barrier…). Possible contamination trapped in the porosity (moisture, metallic residues…), and lower thermo-mechanical properties of ULK will probably impede reliability. Copper resistivity increase with dimension shrinkage will also be an extra issue.     

High performance damascene metal gate MOSFETs for 0.1 μm regime

A novel transistor formation process (damascene gate process) was developed in order to apply metal gates and high dielectric constant gate insulators to MOSFET fabrication and minimize plasma damage to gate insulators. In this process, the gate insulators and gate electrodes are formed after ion implantation and high temperature annealing (~1000°C) for source/drain formation, and the gate electrodes are fabricated by chemical mechanical polishing (CMP) of gate materials deposited in grooves. Metal gates and high dielectric constant gate insulators are applicable to the MOSFET, since the processing temperature after gate formation can be reduced to as low as 450°C. Furthermore, process-damages on gate insulators are minimized because there is no plasma damage caused by source/drain ion implantation and gate reactive ion etching (RIE). By using this process, fully planarized metal (W/TiN or Al/TiN) gate transistors with SiO₂ or Ta₂O₅ as gate insulators were uniformly fabricated on an 8-in wafer. Further, the damascene metal gate transistors exhibited low gate sheet resistivity, no gate depletion and drastic improvement in gate oxide integrity, resulting in high transistor performance     

A photo-oxidation generated low-k dielectric film deposited by reactive evaporation of SiO

A non-stoichiometric silicon oxide film has been deposited by evaporating SiO as a source material in Ar and O₂ mixed gas. The film is composed of SiO and SiO₂, and has a porous structure. The SiO₂ results from some part of SiO reacting with O₂ and its amount depends on the pressure in the chamber. The residual SiO in the film can be photo-oxidized into SiO₂ by ultraviolet radiation with a Hg lamp. The dielectric constant of the film after photo-oxidation is 1.89±0.04 (at frequency of 1 MHz), which shows that this porous structure film is promising for potential application as a low-k dielectric.     

Resist-related damage on ultrathin gate oxide during plasma ashing

This paper presents an important observation of plasma-induced damage on ultrathin oxides during O₂ plasma ashing by metal “antenna” structures with photoresist on top of the electrodes. It is found that for MOS capacitors without overlying photoresist during plasma ashing, only minor damage occurs on thin oxides, even for oxide thickness down to 4.2 nm and an area ratio as large as 10⁴. In contrast, oxides thinner than 6 nm with resist overlayer suffer significant degradation from plasma charging. This phenomenon is contrary to most previous reports. It suggests that the presence of photoresist will substantially affect the plasma charging during ashing process, especially for devices with ultrathin gate oxides     

Robust Cu Dual Damascene Interconnects With Porous SiOCH Films Fabricated by Low-Damage Multi-Hard-Mask Etching Technology

Low-damage hard-mask (HM) plasma-etching technology for porous SiOCH film (k=2.6) has been developed for robust 65-nm-node Cu dual damascene interconnects (DDIs). No damage is introduced by fluorocarbon plasma etching irrespective of whether rigid (k=2.9) or porous (k=2.6) SiOCH films are used, due to the protective CF-polymer layer deposited on the etched sidewall. The etching selectivity of the SiOCH films to the inorganic HMs is kept high by controlling the radical ratio of carbon relative to oxygen in the etching plasma gas. However, oxidation damage penetrates the films from the sidewalls due to the O₂ plasma used for photoresist ashing. This damage is increased by the porous structure. As a result, we developed a via-first multi-hard-mask process for the DD structure in porous SiOCH film with no exposure to O ₂-ashing plasma, and we controlled the via-taper angle by RF bias during etching. We fabricated robust Cu DDIs with tapered vias in porous SiOCH film that can be applied to 65-nm-node ULSIs and beyond     

可实现铜及低k技术等离子去胶工艺的湿法清洗技术

用一种顺流微波等离子干法除胶设备开发出了一种享有专利的等离子工艺,该工艺可满足后道工序中铜及低k材料应用中密集和渗透性低k介电材料的抗蚀剂除胶要求。最终结果显示等离子各向同性除胶工艺与其他等离子化学方法相比,在很大程度上可对介电材料的损伤率降到最小,且能实现除胶后的湿法清洗。首先介绍并讨论了在涂覆抗蚀剂片子上得到的综合工艺特征数据。这些数据包括抗蚀剂去胶速率、低k膜厚度损失及折射指数变化、除胶选择性、k值变化、FTIR光谱以及FDS和SIMS分析结果。在有图形的片子上得到的扫描电镜检查结果显示了在等离子去胶和随后的湿法清洗后的清洁度、良好的图形轮廓和图形结构的关键尺寸保持情况。并介绍了评价器件性能的电性能测试和可靠性数据。此外还讨论了等离子工艺在铜表面清洗的有效性。     

Robust ultrathin oxynitride dielectrics by NH3nitridation and N2O RTA treatment

In this paper, a method to grow robust ultrathin (E_OT=28 Å) oxynitride film with effective dielectric constant of 5.7 is proposed. Samples, nitridized by NH₃ with additional N₂O annealing, show excellent electrical properties in terms of very low bulk trap density, low trap generation rate, and high endurance in stressing. This novel dielectric appears to be very promising for future ULSI devices     

Hydrogenated amorphous silicon thin film transistor fabricated onplasma treated silicon nitride

We have demonstrated that the performance of the inverted staggered, hydrogenated amorphous silicon thin film transistor (a-Si:H TFT) is improved by a He, H₂, NH₃ or N₂ plasma treatment for a short time on the surface of silicon nitride (SiN _x) before a-Si:H deposition. With increasing plasma exposure time, the field-effect mobility increase at first and then decrease, but the threshold voltage changes little. The a-Si:H TFT with a 6-min N₂ plasma treatment on SiN_x exhibited a field effect mobility of 1.37 cm²/Vs, a threshold voltage of 4.2 V and a subthreshold slope of 0.34 V/dec. It is found that surface roughness of SiN_x is decreased and N concentration in the SiN _x at the surface region decreases using the plasma treatment     

Thin-gate SiO2 films formed by in situ multiple rapidthermal processing

A reliable method of forming very thin SiO₂ films (<10 nm) has been developed by rapid thermal processing (RTP) in which in situ multiple RTP sequences have been employed. Sub-10-nm-thick SiO₂ films formed by single-step RTP oxidation (RTO) are superior to conventional furnace-grown SiO₂ on the SiO₂ /Si interface characteristics, dielectric strength, and time-dependent dielectric-breakdown (TDDB) characteristics. It has been confirmed that the reliability of SiO₂ film can be improved by pre-oxidation RTP cleaning (RTC) operated at 700-900°C for 20-60 s in a 1%HCl/Ar or H₂ ambient. The authors discuss the dielectric reliability of the SiO₂ films formed by single-step RTO in comparison with conventional furnace-grown SiO₂ films. The effects and optimum conditions of RTC prior to RTO on the TDDB characteristics are demonstrated. The dielectric properties of nitrided SiO₂ films formed via the N₂O-oxynitridation process are described     

Characterization of ultrathin oxynitride (18-21 A) gate dielectricsby NH3 nitridation and N2O RTA treatment

In this paper, we developed a new method to grow robust ultrathin oxynitride (E_OT=18 A) film with effective dielectric constant of 7.15. By NH₃-nitridation of Si substrate, grown ultrathin Si₃N₄ With N₂O annealing shows excellent electrical properties in terms of significant lower leakage current, very low bulk trap density and trap generation rate, and high endurance in stressing. In addition, this oxynitride film exhibits relatively weak temperature dependence due to a Fowler-Nordheim (FN) tunneling mechanism. This dielectric film appears to be promising for future ultralarge scale integrated (ULSI) devices     

H_2O_2对溶液法制备a-IGZO薄膜光学特性的影响

基于溶液旋涂法和高压退火工艺制备了a-IGZO薄膜。采用椭圆偏振光谱分析仪以及原子力显微镜研究和分析了H_2O_2对薄膜的表面结构和光学特性的影响。实验结果表明,a-IGZO前驱液中不含H_2O_2的薄膜,退火温度从220℃升高到300℃,薄膜的光学带隙从3.03增加到3.29,而膜表面粗糙层由20.69nm降至4.68nm。在同样的高压退火条件处理下,与前驱液中没加入H_2O_2的薄膜相比,折射率显著增加并明显的降低了薄膜表面粗糙度。退火温度在300℃时,薄膜的光学带隙由3.29eV增大到3.34eV,表面粗糙层由4.68nm减少到2.89nm。因此,H_2O_2可以在相对低温条件下有效降低薄膜内部的有机物残留及微缺陷,形成更加致密的a-IGZO薄膜。证明了利用H_2O_2能够有效降低溶液法制备aIGZO薄膜所需的退火温度。