Minimal March Tests for Detection of Dynamic Faults in Random Access Memories

The class of dynamic faults has been recently shown to be an important class of faults for the new technologies of Random Access Memories (RAM) with significant impact on defect-per-million (DPM) levels. Very little research has been done in the design of memory test algorithms targeting dynamic faults. Two March test algorithms of complexity 11N and 22N, N is the number of memory cells, for subclasses of two-operation single-cell and two-cell dynamic faults, respectively, were proposed recently [Benso et al., Proc., ITC 2005] improving the length of the corresponding tests proposed earlier [Hamdioui et al., Proc. of IEEE VLSI Test Symposium, pp. 395–400, 2002]. Also, a March test of length 100N was proposed [Benso et al., Proc. ETS 2005, Tallinn, pp. 122–127, 2005] for detection of two-cell dynamic faults with two fault-sensitizing operations both applied on the victim or aggressor cells. In this paper, for the first time, March test algorithms of minimum length are proposed for two-operation single-cell and two-cell dynamic faults. In particular, the previously known March test algorithm of length 100N for detection of two-operation two-cell dynamic faults is improved by 30N.

Efficient March Test Procedure for Dynamic Read Destructive Fault Detection in SRAM Memories

This paper presents an analysis of dynamic faults in core-cell of SRAM memories. These faults may appear as the consequence of resistive-open defects that appear more and more frequently in VDSM technologies. In particular, the study concentrates on those defects that generate dynamic Read Destructive Faults, dRDFs. In this paper, we demonstrate that read or write operations on a cell involve a stress on the other cells of the same word line. This stress, called Read Equivalent Stress (RES), has the same effect than a read operation. On this basis, we propose to modify the well known March C-, which does not detect dRDFs, into a new version able to detect them. This is obtained by changing its addressing order with the purpose of producing the maximal number of RES. This modification does not change the complexity of the algorithm and its capability to detect the former target faults.This work has been partially funded by the French government under the framework of the MEDEA+ A503 “Associate“ European program.     

Testing and Diagnosis Methodologies for Embedded Content Addressable Memories

Embedded content addressable memories (CAMs) are important components in many system chips where most CAMs are customized and have wide words. This poses challenges on testing and diagnosis. In this paper two efficient March-like test algorithms are proposed first. In addition to typical RAM faults, they also cover CAM-specific comparison faults. The first algorithm requires 9N Read/Write operations and 2(N + W) Compare operations to cover comparison and RAM faults (but does not fully cover the intra-word coupling faults), for an N × W-bit CAM. The second algorithm uses 3N log₂ W Write and 2W log₂ W Compare operations to cover the remaining intra-word coupling faults. Compared with the previous algorithms, the proposed algorithms have higher fault coverage and lower time complexity. Moreover, it can test the CAM even when its comparison result is observed only by the Hit output or the priority encoder output. We also present the algorithms that can locate the cells with comparison faults. Finally, a CAM BIST design is briefly described.     

Classification and Test Generation for Path-Delay Faults Using Single Struck-at Fault Tests

We classify all path-delay faults of a combinational circuit intothree categories: singly-testable (ST), multiply-testable (MT), and singly-testable dependent} (ST-dependent). The classification uses anyunaltered single stuck-at fault test generation tool. Only two runsof this tool on a model network derived from the original network areperformed. As a by-product of this process, we generate single andmultiple input change delay tests for all testable faults. With thesetests, we expect that most defective circuits are identified. All STfaults are guaranteed detection in the case of a single fault, andsome may be guaranteed detection through robust and validatablenon-robust tests even in the case of multiple faults. An ST-dependentfault can affect the circuit speed only if certain ST faults arepresent. Thus, if all ST faults are tested, the ST-dependent faultsneed not be tested. MT faults cannot be guaranteed detection, butaffect the speed only if delay faults simultaneously exist on a setof paths, none of which is ST. Examples and results on several ISCAS89 benchmarks are presented. The method of classification throughtest generation using a model network is complex and can be appliedto circuits of moderate size. For larger circuits, alternativemethods will have to be explored in the future.     

Dynamic Faults in Random-Access-Memories: Concept, Fault Models and Tests

The ever increasing trend to reduce DPM levels of memories requires tests with very high fault coverage and low cost. This paper describes an important fault class, called dynamic faults, that cannot be ignored anymore. The dynamic fault behavior can take place in the absence of the static fault behavior, for which the conventional memory tests have been constructed. The concept of dynamic fault will be established and validated for both dynamic and static Random-Access-Memories. A systematic way to develop fault models for dynamic faults will be introduced. Further, it will be shown that conventional memory tests do not necessarily detect its dynamic faulty behavior, which has been shown to exist in real designs. The paper therefore also presents new memory tests to target the dynamic fault class.     

Testing Address Decoder Faults in Two-Port Memories: Fault Models, Tests, Consequences of Port Restrictions, and Test Strategy

A two-port memory contains two duplicated sets of address decoders, which operate independently. Testing such memories requires the use of single-port tests as well as special two-port tests; the test strategy determines which tests have to be used. Many two-port memories have ports which are read-only or write-only; this impacts the possible tests for single-port and two-port memories, as well as the test strategy. In this paper the effects of interference and shorts between the address decoders of the two ports on the fault modeling are investigated. Fault models and their tests are introduced. In addition, the consequences of the port restrictions (read-only or write-only ports) on the fault models and tests are discussed, together with the test strategy.     

The Coupling Model for Function and Delay Faults

We propose a high-level fault model, the coupling fault (CF) model, that aims to cover both functional and timing faults in an integrated way. The basic properties of CFs and the corresponding tests are analyzed, focusing on their relationship with other fault models and their test requirements. A test generation program COTEGE for CFs is presented. Experiments with COTEGE are described which show that (reduced) coupling test sets can efficiently cover standard stuck-at-0/1 faults in a variety of different realizations. The corresponding coupling delay tests detect all robust path delay faults in any realization of a logic function. This research was sponsored in part by the U.S. National Science Foundation under Grants No. CCR-9872066 and CCR-0073406. Joonhwan Yi received the B.S degree in electronics engineering from Yonsei University, Seoul, Korea, in 1991, and the M.S. and Ph.D degrees in electrical engineering and computer science from the University of Michigan, Ann Arbor, in 1998 and 2002, respectively. From 1991 to 1995, he was with Samsung Electronics, Semiconductor Business, Korea, where he was involved in developing application specific integrated circuit cell libraries. In 2000, he was a summer intern with Cisco, Santa Clara, CA, where he worked for path delay fault testing. Since 2003, he has been with Samsung Electronics, Telecommunication Network, Suwon, Korea, where he is working on system-on-a-chip design. His current research interests include C-level system modeling for fast hardware and software co-simulation, system-level power analysis and optimization, behavioral synthesis, and high-level testing. John P. Hayes received the B.E. degree from the National University of Ireland, Dublin, and the M.S. and Ph.D. degrees from the University of Illinois, Urbana-Champaign, all in electrical engineering. While at the University of Illinois, he participated in the design of the ILLIAC III computer. In 1970 he joined the Operations Research Group at the Shell Benelux Computing Center in The Hague, where he worked on mathematical programming and software development. From 1972 to 1982 he was a faculty member of the Departments of Electrical Engineering– Systems and Computer Science of the University of Southern California, Los Angeles. Since 1982 he has been with the Electrical Engineering and Computer Science Department of the University of Michigan, Ann Arbor, where he holds the Claude E. Shannon Chair in Engineering Science. Professor Hayes was the Founding Director of the University of Michigan's Advanced Computer Architecture Laboratory (ACAL). He has authored over 225 technical papers, several patents, and five books, including Introduction to Digital Logic Design (Addison-Wesley, 1993), and Computer Architecture and Organization, (3rd edition, McGraw-Hill, 1998). He has served as editor of various technical journals, including the Communications of the ACM, the IEEE Transactions on Parallel and Distributed Systems and the Journal of Electronic Testing. Professor Hayes is a fellow of both IEEE and ACM, and a member of Sigma Xi. He received the University of Michigan's Distinguished Faculty Achievement Award in 1999 and the Humboldt Foundation's Research Award in 2004. His current teaching and research interests are in the areas of computer-aided design, verification, and testing; VLSI circuits; fault-tolerant embedded systems; ad-hoc computer networks; and quantum computing.     

March SR3C: A Test for a reduced model of all static simple three-cell coupling faults in random-access memories

A fault primitive-based analysis of all static simple (i.e., not linked) three-cell coupling faults in n×1 random-access memories (RAMs) is discussed. All realistic static coupling faults that have been shown to exist in real designs are considered: state coupling faults, transition coupling faults, write disturb coupling faults, read destructive coupling faults, deceptive read destructive coupling faults, and incorrect read coupling faults. A new March test with 66n operations able to detect all static simple three-cell coupling faults is proposed. To compare this test with other industrial March tests, simulation results are also presented in this paper.     

Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test

This paper presents the results of resistive-open defect insertion in different locations of Infineon 0.13 m embedded-SRAM with the main purpose of verifying the presence of dynamic faults. This study is based on the injection of resistive defects as their presence in VDSM technologies is more and more frequent. Electrical simulations have been performed to evaluate the effects of those defects in terms of detected functional faults. Read destructive, deceptive read destructive and dynamic read destructive faults have been reproduced and accurately characterized. The dependence of the fault detection has been put in relation with memory operating conditions, resistance value and clock cycle, and the importance of at speed testing for dynamic fault models has been pointed out. Finally resistive Address Decoder Open Faults (ADOF) have been simulated and the conditions that maximize the fault detection have been discussed as well as the resulting implications for memory test.This work has been partially funded by the French government under the framework of the MEDEA + A503 ASSOCIATE European program.A paper based on this work was presented at the Eighth IEEE European Test Workshop, Maastricht, The Netherlands, May 2003.Simone Borri received the M.Sc. Degree (summa cum laude) in Electronics Engineering from the University of Pisa (Italy) in 1995. In 1997 he joined STMicroelectronics as a digital designer in the DSP development group of S.S.D. (formerly Parthus, now Ceva), Dublin, Ireland. From 1998 to 2000 he was with ST Microelectronics, Milan, Italy as ASIC DSP designer in the Car Communication business unit. Since 2000 he is with Infineon Technologies, Sophia-Antipolis, France as Staff design engineer in the embedded-SRAM design group. He has recently joined the Secure Mobile System Business Unit. His current interests include BIST, DFT techniques and SoC verification. Simone is an IEEE member since 1995.Magali Hage-Hassan was born near Lyon (France) in 1979. She received a Master of Science degree of Microelectronics and Automatics from the Institute of Engineering Sciences of Montpellier in 2003. She is currently working for Infineon in the memory library department in Sophia-Antipolis. She participated to the European research project MEDEA associate. Hage-Hassans interest include memory test.Luigi Dilillo was born in Barletta (Italy) in 1974. At this moment he is doing his last year of Ph.D. in the Microelectronics Department of the Laboratory of Informatics, Robotics and Microelectronics of Montpellier (LIRMM) in France. He received his degree in Electrical Engineering in 2001, at Politecnico di Torino (Italy). His researches include MEMS and digital circuits. At this moment he is working on delay-fault testing, and memory testing.Patrick Girard is presently Researcher at CNRS (French National Center for Scientific Research), and works in the Microelectronics Department of the LIRMM (Laboratory of Informatics, Robotics and Microelectronics of Montpellier—France). His research interests include the various aspects of digital testing, with special emphasis on DfT, logic BIST, delay fault testing and diagnosis, low power testing and memory testing. He has authored and co-authored 1 book and more than 100 papers on these fields. He has managed several European research projects and industrial research contracts. He is Editor-in-Chief of JOLPE—Journal of Low Power Electronics, and Associate Editor of JEC—Journal of Embedded Computing. He will serve as Program vice-Chair for the International Conference on Embedded And Ubiquitous Computing in 2005 and as Program Chair for the IEEE International Workshop on Electronic Design, Test & Applications in 2006. He is also topic chair of two European conferences (DATE and ETS) and is member of the program committee of several other international conferences. Patrick GIRARD obtained the Ph.D. degree in microelectronics from the University of Montpellier in 1992 and the Habilitation à Diriger des Recherches degree from the University of Montpellier in 2003.Serge Pravossoudovitch was born in 1957. He is currently professor in the electrical and computer engineering department of the University of Montpellier and his research activities are performed at LIRMM (Laboratoire dInformatique, de Robotique et de Microélectronique de Montpellier). He got the Ph.D. degree in electrical engineering in 1983 for his work on symbolic layout for IC design. Since 1984, he is working in the testing domain. He obtained the doctorat détat degree in 1987 for his work on switch level automatic test pattern generation. He is presently interested in memory testing, delay fault testing, design for testability and power consumption optimization. He has authored and co-authored numerous papers on these fields, and has supervised several Ph.D. dissertations. He has also participated to several European projects (Microelectronic regulation, Esprit, Medea).Arnaud Virazel was born in Montpellier (France) in 1974. He is presently assistant professor at the university of Montpellier, and works with the LIRMM (Laboratoire dInformatique, de Robotique et de Microélectronique de Montpellier). He received the B.Sc. (1995) and the M.Sc. (1997) degrees in Electrical Engineering and the Ph.D. (2001) degree in Microelectronics, all from the University of Montpellier/LIRMM. A. Virazels interests include delay testing, memory testing and power optimization during test.     

ADOFs and Resistive-ADOFs in SRAM Address Decoders: Test Conditions and March Solutions

This paper presents a comparative analysis of ADOFs (Address Decoder Open Faults) and resistive-ADOFs in embedded-SRAMs. Such faults are the primary target of this study because they are hard-to-detect faults. These faults are caused by some particular defects which may appear in the parallel transistor network of the logic gates in the address decoders. With this study, we show that the test conditions required for ADOFs testing (sensitization and observation) are also useful for resistive-ADOFs detection, but more stringent timing requirements are needed. In the last part of the paper, we propose a study on the conditions to detect ADOFs with March tests. Moreover, we propose new March elements, which are effective for ADOF testing, and which can be added to existing March tests. *This work has been partially funded by the French government under the framework of the MEDEA+ A503 “ASSOCIATE” European program.     

Generation and Verification of Tests for Analog Circuits Subject to Process Parameter Deviations

The paper presents a test stimulus generation and fault simulation methodology for the detection of catastrophic faults in analog circuits. The test methodology chosen for evaluation is RMS AC supply current monitoring. Tests are generated and evaluated taking account of the potential fault masking effects of process spread on the faulty circuit responses. A new test effectiveness metric of probability of detection is defined and the application of the technique to an analog multiplier circuit is presented. The fault coverage figures are therefore more meaningful than those obtained with a fixed threshold.     

Testing for Bounded Faults in RAMs

We study the class of bounded faults in random-access memories;these are faults that involve a bounded number of cells. This is avery general class of memory faults that includes, for example, theusual stuck-at, coupling, and pattern-sensitive faults, but also manyother types of faults. Some bounded faults are known to requiredeterministic tests of length proportional to n log2 n, where nis the total number of memory cells. The main result of this paper isthat, for any bounded fault satisfying certain very mild conditions,the random test length required for a given level of confidence isalways O(n).     

容错计算机系统中潜在故障的分析和处理途径

潜在故障是容错系统的潜在危害，因为大多数容错系统是基于单故障假设。以汽车导航系统为例来研究这一潜在危害，并用马尔可夫模型说明潜在故障恶化系统平均故障前时间。本文深入研究了一些可能的补救措施，其中透明的在线测试是最有效的方法之一，而用暂时离线的热贮备系统进行测试则是更可靠的方法。     

Simulating Realistic Bridging and Crosstalk Faults in an Industrial Setting

Three different techniques for simulating realistic faults generated from IC layout are discussed. Two of them deal with bridging faults, and the third one handles crosstalk faults. The simulation is performed on top of a commercial simulator and thus is very well applicable in an industrial environment. No change of the design database and only minimal changes of the test shell are required. Experimental results are reported for a library cell and a block from a full-custom design.     

A Low-Cost At-Speed BIST Architecture for Embedded Processor and SRAM Cores

We have introduced a low-cost at-speed BIST architecture that enables conventional microprocessors and DSP cores to test their functional blocks and embedded SRAMs in system-on-a-chip architectures using their existing hardware and software resources. To accommodate our proposed new test methodology, minor modifications should be applied to base processor within its test phase. That is, we modify the controller to interpret some of the instructions differently only within the initial test mode. In this paper, we have proposed a fuctional self-test methodology that is deterministic in nature. In our proposed architecture, a self test program called BIST Program is stored in an embedded ROM as a vehicle for applying tests. We first start with testing processor core using our proposed architedture. Once the testing of the processor core is completed, this core is used to test the embedded SRAMs. A test algorithm which utilizes a mixture of existing memory testing techniques and covers all important memory faults is presented in this paper. The proposed memory test algorithm covers 100% of the faults under the fault model plus a data retention test. The hardware overhead in the proposed architecture is shown to be negligible. This architecture is implemented on UTS-DSP (University of Tehran and Iran Communicaton Industries (SAMA)) IC which has been designed in VLSI Circuits and Systems Laboratory.     

An Efficient Built‐in Self‐Test Algorithm for Neighborhood Pattern‐ and Bit‐Line‐Sensitive Faults in High‐Density Memories

As the density of memories increases, unwanted interference between cells and the coupling noise between bit‐lines become significant, requiring parallel testing. Testing high‐density memories for a high degree of fault coverage requires either a relatively large number of test vectors or a significant amount of additional test circuitry. This paper proposes a new tiling method and an efficient built‐in self‐test (BIST) algorithm for neighborhood pattern‐sensitive faults (NPSFs) and new neighborhood bit‐line sensitive faults (NBLSFs). Instead of the conventional five‐cell and nine‐cell physical neighborhood layouts to test memory cells, a four‐cell layout is utilized. This four‐cell layout needs smaller test vectors, provides easier hardware implementation, and is more appropriate for both NPSFs and NBLSFs detection. A CMOS column decoder and the parallel comparator proposed by P. Mazumder are modified to implement the test procedure. Consequently, these reduce the number of transistors used for a BIST circuit. Also, we present algorithm properties such as the capability to detect stuck‐at faults, transition faults, conventional pattern‐sensitive faults, and neighborhood bit‐line sensitive faults.     

Thermal Annealing and Propagation of Shockley Stacking Faults in 4H-SiC PiN Diodes

Stacking faults within 4H-SiC PiN diodes are known to be detrimental to device operation. Here, we present electroluminescence (EL) images of 4H-SiC PiN diodes providing evidence that electrically and optically stimulated Shockley stacking fault (SSF) propagation is a reversible process at temperatures as low as 210°C. Optical beam induced current (OBIC) images taken following complete optical stressing of a PiN diode and that lead to a small number of completely propagated SSFs provide evidence that such defects propagate across the n–/p+ interface and continue to grow throughout the p+ layer. These observations bring about questions regarding the validity of the currently accepted driving force mechanism for SSF propagation.     

Fault macromodeling and a testing strategy for opamps

In this paper, we propose a simple testing technique based on DC measurements for operational amplifiers. We first develop a comprehensive macromodel for the transistor-level opamp to alleviate the efforts of fault simulation. By incorporating appropriate I/O characteristics into the macromodel, the output deviation due to the modeling error can be significantly reduced. We use the transistor short/bridging faults to illustrate the efficiency of our proposed technique. Experimental results show that a high fault coverage can be achieved for the stand-alone opamp by measuring two DC parameters V _o-max ^* and V _o-min ^*. For the embedded opamps, many short/bridging faults cannot be detected by traditional functional testing. However, by using similar DC measurements along with a design for testability (DFT) scheme, we can improve the fault coverage dramatically.An earlier version of this work was reported in ICCAD-94.     

Trade-offs in scan path and BIST implementations for RAMs

In this article we propose efficient scan path and BIST schemes for RAMs. Tools for automatic generation of these schemes have been implemented. They reduce the design effort and thus allow the designer to select the more appropriate scheme with respect to various constraints.