纳米晶浮栅存储器的模拟、制备和电学特性

介绍了在纳米晶浮栅存储器数据保持特性方面的研究工作,重点介绍了纳米晶材料的选择与制备和遂穿介质层工程。研究证明,金属纳米晶浮栅存储器比半导体纳米晶浮栅存储器具有更好的电荷保持特性。并且金属纳米晶制备方法简单,通过电子束蒸发热退火的方法就能够得到质量较好的金属纳米晶,密度约4×1011cm-2,纳米晶尺寸约6～7nm。实验证明,高介电常数隧穿介质能够明显改善浮栅存储器的电荷保持特性,所以在引入金属纳米晶和高介电常数遂穿介质之后,纳米晶浮栅存储器可能成为下一代非挥发性存储器的候选者。     

Electronic properties of Ge nanocrystals for non volatile memory applications

Charge and discharge phenomena of Germanium nanocrystals fabricated by low pressure chemical vapor deposition are investigated by means of Capacitance–Voltage and capacitance decay measurements. The study shows fast programming and erasing times as compared with conventional devices. It is shown that the charge saturation depends on the gate voltage stress in the low electric field regime. For high gate voltages, a saturation of the stored charge is obtained, indicating that the density of trapped carriers in Ge nanocrystals is limited and depends only on the dots size. Capacitance decay measurements exhibits a very long retention time for holes as compared with silicon nanocrystal memories. This is mainly due to the barrier height for holes at the nc-Ge/ ₂ interface. A model for simulation of the retention kinetics has been developed and allows to extract the band alignment of the nc-Ge/SiO₂/Si system. The simulation results are then used to determine the band gap energy of Ge nanocrystals. Finally, it is shown that Ge nanocrystals are very good candidates for P-type Metal Oxide Semiconductor nonvolatile memories.     

金属纳米晶快闪存储器研究进展

金属纳米晶具有态密度高、费米能级选择范围广以及无多维载流子限制效应等优越性,预示着金属纳米晶快闪存储器在下一代闪存器件中具有很好的应用前景。从金属纳米晶存储器的工作原理、纳米晶的制备方法、以及新型介质材料和电荷俘获层结构等方面,对金属纳米晶存储器近年来的研究进展进行了总结。     

Nonvolatile memory with a metal nanocrystal/nitride heterogeneous floating-gate

Heterogeneous floating-gates consisting of metal nanocrystals and silicon nitride (Si/sub 3/N/sub 4/) for nonvolatile memory applications have been fabricated and characterized. By combining the self-assembled Au nanocrystals and plasma-enhanced chemical vapor deposition (PECVD) nitride layer, the heterogeneous-stack devices can achieve enhanced retention, endurance, and low-voltage program/erase characteristics over single-layer nanocrystals or nitride floating-gate memories. The metal nanocrystals at the lower stack enable the direct tunneling mechanism during program/erase to achieve low-voltage operation and good endurance, while the nitride layer at the upper stack works as an additional charge trap layer to enlarge the memory window and significantly improve the retention time. The write/erase time of the heterogeneous stack is almost the same as that of the single-layer metal nanocrystals. In addition, we could further enhance the memory window by stacking more nanocrystal/nitride heterogeneous layers, as long as the effective oxide thickness from the control gate is still within reasonable ranges to control the short channel effects.     

Metal nanocrystal memories. I. Device design and fabrication

This paper describes the design principles and fabrication process of metal nanocrystal memories. The advantages of metal nanocrystals over their semiconductor counterparts include higher density of states, stronger coupling with the channel, better size scalability, and the design freedom of engineering the work functions to optimize device characteristics. One-dimensional (1-D) analyses are provided to illustrate the concept of work function engineering, both in direct-tunneling and F-N-tunneling regimes. A self-assembled nanocrystal formation process by rapid thermal annealing of ultrathin metal film deposited on top of gate oxide is developed and integrated with NMOSFET to fabricate such devices     

High-performance nonvolatile HfO/sub 2/ nanocrystal memory

In this letter, we demonstrate high-performance nonvolatile HfO/sub 2/ nanocrystal memory utilizing spinodal phase separation of Hf-silicate thin film by 900/spl deg/C rapid thermal annealing. With this technique, a remarkably high nanocrystal density of as high as 0.9 /spl sim/ 1.9 /spl times/ 10/sup 12/ cm/sup -2/ with an average size <10 nm can be easily achieved. Because HfO/sub 2/ nanocrystals are well embedded inside an SiO/sub 2/-rich matrix and due to their sufficiently deep energy level, we, for the first time, have demonstrated superior characteristics of the nanocrystal memories in terms of a considerably large memory window, high-speed program/erase (P/E) (1 /spl mu/s/0.1 ms), long retention time greater than 10/sup 8/ s for 10% charge loss, and excellent endurance after 10/sup 6/ P/E cycles.     

Hafnium silicate nanocrystal memory using sol-gel-spin-coating method

The authors fabricate the hafnium silicate nanocrystal memory for the first time using a very simple sol-gel-spin-coating method and 900 /spl deg/C 1-min rapid thermal annealing (RTA). From the TEM identification, the nanocrystals are formed as the charge trapping layer after 900 /spl deg/C 1-min RTA and the size is about 5 nm. They demonstrate the composition of nanocrystal is hafnium silicate from the X-ray-photoelectron-spectroscopy analysis. They verify the electric properties in terms of program/erase (P/E) speed, charge retention, and endurance. The sol-gel device exhibits the long charge retention time of 10/sup 4/ s with only 6% charge loss, and good endurance performance for P/E cycles up to 10/sup 5/.     

Memory characteristics of an MOS capacitor structure with double-layer semiconductor and metal heterogeneous nanocrystals

An MOS (metal oxide semiconductor) capacitor structure with double-layer heterogeneous nanocrystals consisting of semiconductor and metal embedded in a gate oxide for nonvolatile memory applications has been fabricated and characterized. By combining vacuum electron-beam co-evaporated Si nanocrystals and self-assembled Ni nanocrystals in a SiO_2 matrix, an MOS capacitor with double-layer heterogeneous nanocrystals can have larger charge storage capacity and improved retention characteristics compared to one with single-layer nanocrystals. The upper metal nanocrystals as an additional charge trap layer enable the direct tunneling mechanism to enhance the flat voltage shift and prolong the retention time.     

包含双层半导体和金属纳米晶MOS电容的存储特性

制备了包含双层半导体和金属纳米晶的MOS电容结构,研究了其在非挥发性存储器领域的应用。利用真空电子束蒸发技术,在二氧化硅介质中得到了半导体硅纳米晶和金属镍纳米晶。与包含单层纳米晶的MOS电容相比,这种包含双层异质纳米晶的MOS电容显示出更大的存储能力,且保留性能得到改善。说明顶层的金属纳米晶作为一层额外的电荷俘获层可以通过直接隧穿机制进一步延长保留时间和提高平带电压漂移量。     

Self-assembly of metal nanocrystals on ultrathin oxide for nonvolatile memory applications

The self-assembly of metal nanocrystals including Au, Ag, and Pt on ultrathin oxide for nonvolatile memory applications are investigated. The self-assembly of nanocrystals consists of metal evaporation and selective rapid-thermal annealing (RTA). By controlling process parameters, such as the thickness of the deposited film, the post-deposition annealing temperatures, and the substrate doping concentration, metal nanocrystals with density of 2–4 × 10¹¹ cm⁻², diameter less than 8.1 nm, and diameter deviation less than 1.7 nm can be obtained. Observation by scanning-transmission electron microscopy (STEM) and convergent-beam electron diffraction (CBED) shows that nanocrystals embedded in the oxide are nearly spherical and crystalline. Metal contamination of the Si/SiO₂ interface is negligible, as monitored by STEM, energy dispersive x-ray spectroscopy (EDX), and capacitance-voltage (C-V) measurements. The electrical characteristics of metal, nanocrystal nonvolatile memories also show advantages over semiconductor counterparts. Large memory windows shown by metal nanocrystal devices in C-V measurements demonstrate that the work functions of metal nanocrystals are related to the charge-storage capacity and retention time because of the deeper potential well in comparison with Si nanocrystals.     

Modeling of tunneling P/E for nanocrystal memories

This paper presents a detailed study of the program/erase (P/E) dynamics under uniform tunneling for nanocrystal (NC) memories. Calculating the potential profile and the tunneling currents across the dielectric barriers, we evaluate NC charging and discharging transients during P/E operations. The calculated P/E windows and times compare well with experimental data for memory cells with different oxide thicknesses. The model accounts for the typical features of threshold voltage (V/sub T/) shift as a function of applied gate voltage, and can be used as a valuable tool for optimizing the cell geometry and parameters for maximum performance.     

Impact of high-κ dielectric and metal nanoparticles in simultaneous enhancement of programming speed and retention time of nano-flash memory

A methodology to simulate memory structures with metal nanocrystal islands embedded as floating gate in a high-κ dielectric material for simultaneous enhancement of programming speed and retention time is presented. The computational concept is based on a model for charge transport in nano-scaled structures presented earlier, where quantum mechanical tunneling is defined through the wave impedance that is analogous to the transmission line theory. The effects of substrate-tunnel dielectric conduction band offset and metal work function on the tunneling current that determines the programming speed and retention time is demonstrated. Simulation results confirm that a high-κ dielectric material can increase programming current due to its lower conduction band offset with the substrate and also can be effectively integrated with suitable embedded metal nanocrystals having high work function for efficient data retention. A nano-memory cell designed with silver (Ag) nanocrystals embedded in Al₂O₃ has been compared with similar structure consisting of Si nanocrystals in SiO₂ to validate the concept.     

Size-quantization stark effect in quasi-zero-dimensional semiconductor structures

A theory of the size-quantization Stark effect in semiconductor nanocrystals under conditions in which the polarization interaction of an electron (hole) with a nanocrystal surface plays the dominant role is developed. It is shown that, in the region of interband absorption, the shifts of electron (hole) size-quantization levels in a nanocrystal subjected to an external homogeneous electric field are governed by the quadratic Stark effect. A new electrooptical method is proposed furnishing an opportunity to determine the critical radii of nanocrystals in which bulk excitons can appear.     

The effect of light irradiation on electrons and holes trapping in nonvolotile memory capacitors employing sub 10 nm SiO2-HfO2 stacks and Au nanocrystals

We demonstrate the possibility to control charge trapping in the memory stacks comprised of metal nanocrystals (NCs) sandwiched between SiO₂ and high-k dielectric films by light irradiation. Non-equilibrium depletion effects in the state of the art charge trapping memories are reported for the first time. The studied nonvolatile memory devices employ Au NCs, thermal SiO₂ tunnel layer, atomic layer deposited HfO₂ blocking layer and Au/Pt metal gate. The memory windows are 3 V and 10.5 in the dark and under illumination for ±10 V programming voltages. Reliability limitations of the studied structure, in particular leakage currents and effects in high electric fields have been investigated in detail and are discussed in view of the mentioned device application. Low programming voltages and currents, and high light sensitivity make suggested NVM structures promising for developing digital imagers with ultra-low power consumption.     

Charge trapping in organic transistor memories: On the role of electrons and holes

In this work, we study charge trapping in organic transistor memories with a polymeric insulator as gate dielectric. We found that the mechanism of charge trapping is tunneling from the semiconductor channel into the gate dielectric. Depending on the semiconductor and its processing, charge trapping can result in large bi-directional threshold voltage shifts, in case the semiconductor is ambipolar, or in shifts in only one direction (unipolar semiconductor). These results indicate that optimal memory performance requires charge carriers of both polarities, because the most efficient method to lower the programming field is by overwriting a trapped charge by an injected charge of opposite polarity.     

Self-assembled metallic nanocrystal structures for advanced non-volatile memory applications

Nanocrystal (NC) based non-volatile memories are a leading candidate to replace conventional floating gate memory. Substituting the poly-silicon gate with a layer of discrete nanocrystals or nanodots provides increased immunity to charge loss. Metallic nanocrystals have been found to be advantageous over Si- or Ge-based approaches due to good controllability of the size distribution and the achievable NC densities as well as increased charge storage capacity of metallic nanocrystals. Sufficiently high NC densities have been achieved to demonstrate feasibility for sub-32 nm node non-volatile memory devices.     

Fabrication of Ni Nanocrystal Flash Memories Using a Polymeric Self-Assembly Approach

Fabrication of nickel nanocrystal flash memories using a polymeric approach is presented. Heat treatment of the poly (styrene-b-methyl methacrylate) block copolymer with a molecular weight of 67 000 g/mol followed by PMMA removal in an organic solvent created a porous PS film with 20-nm-diameter pores and a total pore density of ~6 times 10¹⁰ cm^-2. A trilayer pattern-transfer approach was employed in order to solve the metal lift-off issue intertwined with the low aspect ratio block copolymer patterns. As a result, a highly uniform self- assembled array of nickel nanocrystals was attained and utilized for flash memory fabrication. The memory devices demonstrated an unchanged memory window for up to 2 times 10⁵ stressing cycles.     

Optimization of threshold voltage window under tunneling program/erase in nanocrystal memories

This paper analyzes solutions to improve the program/erase (P/E) window for nanocrystal (NC) memory cells, by means of the model presented in our previous work . The limited threshold voltage (V/sub T/) window typically observed in the Fowler-Nordheim (FN) programming regime for NC memories was shown to be a direct consequence of the lack of any conduction and /spl epsi/ mismatch between the tunnel and the interpoly-oxide at steady-state. This condition can be avoided when tunnel oxide conduction is due to direct tunneling, but to assure sufficiently short P/E times very thin oxides are required, sacrificing cell nonvolatility. The use of alternative materials for interpoly dielectric, gate and NC is investigated. Finally, barrier engineering is presented as a valid way to improve the available V/sub T/ window.     

Silicon nanocrystal non-volatile memory for embedded memory scaling

In this paper, we present key features of silicon nanocrystal memory technology. This technology is an attractive candidate for scaling of embedded non-volatile memory (NVM). By replacing a continuous floating gate by electrically isolated silicon nanocrystals embedded in an oxide, this technology mitigates the vulnerability of charge loss through tunnel oxide defects and hence permits tunnel oxide and operating voltage scaling along with accompanied process simplifications. However, going to discrete nanocrystals brings new physical attributes that include the impact of Coulomb blockade or charge confinement, science of formation of nanocrystals of correct size and density and the role of fluctuations, all of which are addressed in this paper using single memory cell and memory array data.     

A three charge-states model for silicon nanocrystals nonvolatile memories

In the field of nonvolatile memories, substantial improvement of reliability is obtained by replacing the continuous polysilicon floating gate by a planar distribution of silicon nanocrystals, each acting as a storage node. The test devices in the present paper are MOS capacitors containing a two-dimensional layer of nanocrystals located 2.5 nm away from the oxide/substrate interface, inside the SiO/sub 2/. This work presents various measurements of the charge current versus either bias voltage or time. On the other side, the charge and discharge dynamics of the nanocrystals had already been described by De Salvo using a model borrowed from the conventional floating-gate memory. We show this approach to be not completely suitable to explain the experimental observations. Thus, we describe and apply a so-called granular model, based on a mono-electronic principle limited by Coulomb blockade, in which electrons interact with the nanocrystals one by one. Omitting the reality of such a one-by-one principle may involve important mistakes in the interpretation of phenomena.