电推进技术和空心阴极组件/中和器的发展

电推进系统经过多年发展,已经成功在多个卫星平台以及科学探测器上应用.本文对电推进系统的国内外的发展状况进行了介绍,重点介绍了几个成功应用案例;之后文章对电推进系统的核心部件——用空心阴极/中和器的种类和发展状况等进行了对比分析.     

微空心阴极放电及其应用

微空心阴极放电（MHCD）是指阴极孔径为亚毫米量级时的高气压辉光放电。本文介绍了微空心阴极放电的研究进展，分析了其光谱特性，最后讨论了它的应用前景。     

用于杆控双模行波管的高精度空心阴极组件的装配技术

介绍了一种高精度空心阴极组件的装配技术,该阴极应用于杆控双模行波管中,经过摸索和试验,得出一套行之有效的装配方法,装配精度完全满足要求.     

毫米波返波管阴极的研制

本文讨论了毫米波返波管对阴极的要求;介绍了所设计的实心注和空心注阴极结构以及制造技术;给出了阴极的发射特性;试验表明,所研制的阴极满足八毫米返波管的要求。     

六硼化镧与钡钨空心阴极的放电特性实验研究

空心阴极作为电推力器点火和羽流中和的核心部件,其内部气体放电特性对于阴极的工作性能起着决定性的作用.本文对基于不同发射体的钡钨空心阴极和六硼化镧阴极的放电特性进行了系统的实验研究,结果表明:随着阴极工作参数的不同,两种阴极的放电均表现为三种典型的放电模式;在相同的工作参数下,六硼化镧阴极可维持的放电电流较钡钨阴极的大,工作电流范围也更宽,但钡钨阴极工作时的放电电压更加稳定,应用于霍尔推力器时,有利于推力器工作效率的提高和稳定.     

微空心阴极放电与准分子光源

微空心阴极放电是一种新颖的、非平衡、高气压辉光放电.综述了微空心阴极放电的基本原理;详细论述了微空心阴极放电中的准分子辐射,以及微空心阴极放电的放电方式(直流放电、脉冲放电、射频放电)对准分子辐射强度和效率的影响;最后论述了微空心阴极放电的运行方式(串联运行、并联运行)对准分子辐射的影响.     

特殊氧化物阴极基底金属的电成型

正 一、前言 特殊形状的氧化物阴极基底用市场供应的镍材加工成形比较困难,有时甚至不可能。我们利用电成型工艺解决了这个难题。我们曾用电成型工艺成功地制成旋束管用的螺旋形阴极基底(图1)、10cm返波管用的环形束阴极基底(图2)、大功率速调管用的空心束阴极基底(图3)和行波管用的贮备式阴极基底(图4)等。而用电成型镍阴极基底制成的长寿命贮存式氧化物阴极,经几万小时后阴极性能仍保持良好。说明电成型阴极基底金属符合制作长寿命高性能阴极的要求。实践证明电成型工艺具有工艺简单、可制成形状复杂、精度高、性能好的阴极基底,为设计微波电子器件提供了方便,是一种值得推广的     

空心阴极放电的研究

空心阴极放电是因为空心的阴极包围着放电阴极区域而得名的。这种放电特征和特性在某些方面比较接近辉光放电或弧光放电。但是在另一些方面则又与二者有明显的不同,空心阴极放电中的一些特有过程决定了特有的特征和特性,这些牲和特引起了人们的很大兴趣,促使人们对空心阴极放电进行了广泛而深入的研究。 空心阴极放电有如下一些基本特征: 空心阴极从几个方面包围了阴极区,使得空心阴极中形成了重迭的负辉区。负辉区杜来就是一个高带电粒子浓度的等离子区,而任空心阴极中负辉区的带电粒子浓度更高出1-2个数量级。常常可达到10~(14)/cm~3或更高。 在空心阴极放电的负辉区和四周的阴极之间存在着一个离     

真空电子技术

0462 02020117集螺旋阴极笼型阴极网状阴极为一体的新型阴极(Z阴极)/张新富(南京电子管厂)11真空电子技术一2001,(1)一10一13文中阐述了Z阴极的由来、定义、特性和运用,以及Z阴极与螺旋阴极、笼型阴极、网状阴极之间的转换和代替.图5参2(刚)0462 02020118空心阴极直流放电的二维自洽模型描述和阴极溅射分析/赖建军,余建华,黄建军,王新兵,丘军林(华中理工大学激光技术国家实验室)11物理学报一2001,50(8)一1528一1533建立了空心阴极放电的二维自洽理论模型,理论研究了气压为50一12OPa,电压为150一300V的范围内Ar空合阴极放电栩生、粒子密度…     

空心阴极限制性放电的氦-氖激光器

空心阴极放电是一种新的激励技术,用低电压就可放电,激活区为空心阴极中的阴极位降区与负辉区.由于这两个区域中存在高能电子,使氦原子激发产生足够多的亚稳态,故也可以获得氦-氖激光.本文报导了通过外部触发能实现低气压下的空心阴极放电,激光输出功率有几倍的增加.本文采用笛子形空心阴极,它是内径为4毫米、长度为55厘米的无氧铜管, 每隔5厘米开一个孔,对准孔的位置上面安装上阳极,共有十个阳极,如图1所示.     

Performance Comparison of VLV, ULV, and ECR Tests

It has been shown that Very-Low-Voltage and Minimum-Voltage tests can detect defects that escape tests applied at normal voltages. Energy Consumption Ratio test, a recently developed current-based test, has shown its ability to reduce the impact of process variations and detect various types of defects. These tests may be used as supplements to traditional tests to ensure high quality product. In this paper, Very-Low-Voltage, Ultra-Low-Voltage (a modified version of Minimum-Voltage), and Energy Consumption Ratio tests are applied as supplemental tests along with existing traditional tests to a biomedical IC product. The effectiveness and efficiency of these supplemental tests are evaluated and compared with some major traditional tests. The effectiveness analysis indicates that Ultra-Low-Voltage and Energy Consumption Ratio tests identified potentially defective devices from the good devices. The efficiency analysis shows that Energy Consumption Ratio test is much more efficient than Very-Low-Voltage, Ultra-Low-Voltage, and major traditional tests.     

Synthesis of Native Mode Self-Test Programs

Recent studies show that at-speed functional tests are better for finding realistic defects than tests executed at lower speeds. This advantage has led to growing interest in design for at-speed tests. In addition, time-to-market requirements dictate development of tests early in the design process. In this paper, we present a new methodology for synthesis of at-speed self-test programs for microprocessors. Based on information about the instruction set, this high-level test generation methodology can generate instruction sequences that exercise all the functional capabilities of complex processors. Modern processors have large memory modules, register files and powerful ALUs with comprehensive operations, which can be used to generate and control built-in tests and to evaluate the response of the tests. Our method exploits the functional units to compress and check the test response at chip internal speeds. No hardware test pattern generators or signature analyzers are needed, and the method reduces area overhead and performance impact as compared to current BIST techniques. A novel test instruction insertion technique is introduced to activate the control/status inputs and internal modules related to them. The new methodology has been applied to an example processor much more complex than any benchmark circuit used in academia today. The results show that our approach is very effective in achieving high fault coverage and automation in at-speed self-test generation for microprocessor-like circuits.     

Automated System-Level Test Development for Mixed-Signal Circuits

While in the digital domain, test development is primarily conducted with the use of automated tools, knowledge-based, ad hoc test methods have been in use in the analog domain. High levels of design integration and increasing complexity of analog blocks within a system necessitate automated system-level analog test development tools. We outline a methodology for specification-based automated test generation and fault simulation for analog circuits. Test generation is targeted at providing the highest coverage for each specified parameter. The flexibility of assigning analog test attributes is utilized for merging tests leading to test time reduction with no loss in test coverage. Further optimization in test time is obtained through fault simulations by selecting tests that provide adequate coverage in terms of several components and dropping the ones that do not provide additional coverage. A system-level test set target in the given set of specifications, along with fault and yield coverages in terms of each targeted parameter, and testability problems are determined through the proposed methodology.     

软件的单元测试方法

软件测试是软件质量保障的技术关键,而单元测试是软件开发过程中不可缺少的部分,是其他测试的基础。重点介绍了单元测试的方法,并结合实际说明了这些方法的技术应用。     

汽车电子产品环境与可靠性试验标准研究

汽车电子产品的可靠性,直接关系到整车的安全性和可靠性,因此其测试要求也比较严格。介绍了汽车电子产品环境与可靠性试验所采用的标准,并对相应标准中的试验项目进行了分析研究;同时,举例分析了试验顺序方案的制定方法。     

The Role of Test Protocols in Automated Test Generation for Embedded-Core-Based System ICs

Modular testing is an attractive approach to testing large system ICs, especially if they are built from pre-designed reusable embedded cores. This paper describes an automated modular test development approach. The basis of this approach is that a core or module test is dissected into a test protocol and a test pattern list. A test protocol describes in detail how to apply one test pattern to the core, while abstracting from the specific test pattern stimulus and response values. Subsequent automation tasks, such as the expansion from core-level tests to system-chip-level tests and test scheduling, all work on test protocols, thereby greatly reducing the amount of compute time and data involved. Finally, an SOC-level test is assembled from the expanded and scheduled test protocols and the (so far untouched) test patterns. This paper describes and formalizes the notion of test protocols and the algorithms for test protocol expansion and scheduling. A running example is featured throughout the paper. We also elaborate on the industrial usage of the concepts described.     

验证复杂电子系统任务可靠度的试验方案

阐述了基本可靠性验证试验不能取代任务可靠度验证试验的方案。在很多情况下,系统的基本可靠性验证试验获得通过,但任务可靠性却达不到指标要求;相反,任务可靠性验证试验则可以包含基本可靠性的信息。介绍了同时进行两种验证试验的试验方法和数据处理方法。     

Combining Scan Test and Built-in Self Test

For digital chips containing functional logic and embedded memories, these are usually tested separately: Scan test is used for testing functional logic; Memory Built-in Self Test (MBIST) is run for embedded memories. A new approach is proposed to exercise scan test and MBIST in parallel in order to reduce production test time and improve stress tests. It requires only small additional logic and allows to simultaneously run both test modes. In general, the approach can be used to control simultaneously scan test and any Built-in Self Test (BIST) providing a simple pass/fail result.     

合理安排电磁兼容测试在产品测试中的顺序

实例表明,将电磁兼容试验置于气候环境影响试验与机械要求试验之前与之后进行所得的结果存在较大的差异。通过分析认为气候环境影响试验与机械要求试验可能会影响被测设备中的某些材料特性,从而影响设备的电磁兼容性能。因此电磁兼容测试应与其他测试一起形成一个有机的整体,合理安排测试顺序,可以更好地发现产品的质量问题,提高产品的技术优势和市场竞争力。