Study of unipolar pulsed ramp and combined ramped/constant voltage stress on mos gate oxides

MOS gate oxide capacitors over a wide range of oxide thicknesses (10.9–28 nm) were stressed using a unipolar pulsed voltage ramp and combined ramped/constant voltage stress measurements. The reliability measurements were performed with several different bias conditions in order to assess the effects of the measurement conditions on times to breakdown and breakdown fields. In the first part it was verified that the unipolar pulsed ramp yields breakdown distributions which are identical to those of a widely used staircase ramp. In the second part the unipolar pulsed ramp was used for pre-stress prior to a constant stress and measurement results were compared to those of a ramped/constant stress with a staircase ramp. In several cases a ramp prior to a constant stress increases time to breakdown. The observations made in this study imply that the time to breakdown of a constant stress in the Fowler-Nordheim tunneling regime is strongly dependent on charge trapping and, therefore, on the stressing history of the oxide. Finally, it is shown that the combined ramped/constant voltage stress is a valuable tool for monitoring extrinsic and intrinsic breakdown properties when applying stress parameters in the correct way.     

Quality assessment of thin oxides using constant and ramped stress measurements

Two methods are proposed for obtaining extrinsic oxide lifetime data using fast ramped tests. It is shown that the intersection point between the extrinsic and intrinsic branches of a Weibull plot coincides for ramped and constant stress tests. This is the basis of our fast qualification approach, where intrinsic data are obtained by constant voltage stress and extrinsic data are cumulated with a fast ramped test. The correctness of our approaches is supported by constant voltage and exponentially ramped current measurements.     

Effects of temperature and defects on breakdown lifetime of thinSiO2 at very low voltages

This paper investigates the physics of voltage and temperature accelerated breakdown testing of silicon dioxide within the framework of an anode hole injection model which can predict low voltage (3.3 V and below) breakdown lifetime. The field acceleration rate is shown to be independent of temperature, while the reduction of oxide breakdown lifetime at increased temperature is due to the oxide's enhanced susceptibility to damage caused by the holes' transport through the oxide. This paper also investigates defect related breakdown, showing that defects can be mathematically modeled as effective thinning even for aggressively scaled oxides. The effective thickness statistic derived from ramp breakdown or high-field lifetime or charge-to-breakdown tests enables determination of the oxide integrity of a specific oxide technology. For 3.3 V operation, an oxide technology must provide an effective thickness of 44 Å; for 2.5 V operation, 34 Å     

Reliability of ultrathin silicon dioxide under combined substratehot-electron and constant voltage tunneling stress

An experimental investigation of breakdown and defect generation under combined substrate hot-electron and tunneling electrical stress of silicon oxide ranging in thickness from 2.0 nm to 3.5 nm is reported. Using independent control of the gate current for a given substrate and gate bias, the time-to-breakdown of ultrathin silicon dioxide under substrate hot-electron stress is observed to be inversely proportional to the gate current density. The thickness dependence (2.0 nm to 3.5 nm) of substrate hot-electron reliability is reported and shown to be similar to constant voltage tunneling stress. The build-up of defects measured using stress-induced-leakage-current and charge-pumping for both tunneling and substrate hot-electron stress is reported. Based on these and previous results, a model is proposed to explain the time-to-breakdown behavior of ultrathin oxide under simultaneous tunneling and substrate hot-electron stress. The results and model provide a coherent understanding for describing the reliability of ultrathin SiO₂ under combined substrate hot-electron injection and constant voltage tunneling stress     

A new technique for determining long-term TDDB accelerationparameters of thin gate oxides

A new technique, the dual voltage versus time curve (V-t) integration technique, is presented as a much faster method to obtain time-dependent dielectric breakdown (TDDB) acceleration parameters (α and τ) of ultrathin gate oxides compared to conventional long-term constant voltage stress tests. The technique uses V-t curves measured during highly accelerated constant or ramped current injection breakdown tests. It is demonstrated that the technique yields acceleration parameters that are statistically identical to values obtained from long-term constant voltage TDDB tests. In contrast to traditional TDDB tests, the proposed technique requires over an order of magnitude less testing time, a smaller sample size, and can be used during production monitoring     

A model relating wearout to breakdown in thin oxides

A model has been developed relating wearout to breakdown in thin oxides. Wearout has been described in terms of trap generation inside of the oxide during high voltage stressing prior to breakdown. Breakdown occurred locally when the local density of traps exceeded a critical value and the product of the electric field and the higher leakage currents through the traps exceeded a critical energy density. The measurement techniques needed for determining the density of high-voltage stress generated traps have been described along with the method for coupling the wearout measurements to breakdown distributions. The average trap density immediately prior to breakdown was measured to be of the order of low-10¹⁹/cm³ in 10 nm thick oxides fabricated on p-type substrates stressed with negative gate voltages. The model has been used to describe several effects observed during measurements of time-dependent-dielectric-breakdown distributions. The area dependence of breakdown distributions, the differences in the breakdown distributions during constant current and constant voltage stressing, and the multi-modal distributions often observed were simulated using the model. The model contained the provision for incorporation of weak spots in the oxide     

Influence of charge trapping on oxide scaling down

The aim of this work is the characterization, in terms of trapped charge and charge to breakdown, of the quality of an oxide with reduced thickness. A comparison between two evaluation methods, the widely used exponentially ramped current stress (ERCS) and the constant current stress (CCS), is established obtaining contradictory results. A measurement of the charge trapped in the oxide bulk is performed by sensing the modification of the Fowler–Nordheim barrier under constant current stress. Using this technique it is possible to correlate the charge trapping characteristics with the charge to breakdown and to explain the inconsistencies.     

Statistical nature of hard breakdown recovery in high-κ dielectric stacks studied using ramped voltage stress

In replacing the conventional SiO₂ gate dielectric with high-κ materials, new challenges emerge on understanding the kinetics of dielectric breakdown due to the different properties of the new bulk oxide and the interfacial layers at the substrate and gate electrode interface as well. Among several complexities, dielectric relaxation and recovery have received a lot of attention due to their promising applications in resistive random access memory (RRAM). In this study, we explore the stochastic nature of hard breakdown recovery in HfO₂, taking advantage of ramped voltage stress (RVS) measurements, which are theoretically equivalent to the widely used constant voltage stress (CVS), while being significantly less time-consuming. We found that the possibility of recovery is largely dependent on the ramp rate during RVS as the dielectric needs adequate time and sufficient thermal budget to recover. The clustering model is found to be a good fit to the RVS data sets for post-recovery subsequent breakdown events and the extent of defect clustering is found to be more intense after increasing number of recovery events. The breakdown mechanism in the stack is confirmed by measuring the resistance change trends with temperature.     

Accurate determination of ultrathin gate oxide thickness andeffective polysilicon doping of CMOS devices

We present an efficient and accurate method to characterize the physical thickness of ultrathin gate oxides (down to 25 Å) and the effective polysilicon doping of advanced CMOS devices. The method is based on the model for Fowler-Nordheim (F-N) tunneling current across the gate oxide with correction in gate voltage to account for the polysilicon-gate depletion. By fitting the model to measured data, both the gate oxide thickness and the effective poly doping are unambiguously determined. Unlike the traditional capacitance-voltage (C-V) technique that overestimates thin-oxide thickness and requires large area capacitor, this approach results in true physical thickness and the measurement can be performed on a standard sub-half micron transistor. The method is suitable for oxide thickness monitoring in manufacturing environments     

Dielectric breakdown distributions for void containing silicon substrates

Distributions of gate oxide failure in various types of silicon substrate materials have been investigated for a wide range of oxide thicknesses. Silicon substrates containing various well-characterized void distributions along with defect-free materials were tested using special low-series resistance capacitor structures. Results of both ramped field tests of variable ramp rate and constant field tests were performed and analyzed within the framework of Weibull statistics. Ramped field tests are not “time zero dielectric breakdown” tests as is commonly asserted. They can in fact be very useful in extrapolating time dependent failure. The same set of Weibull parameters can be used to describe both ramped field and constant field wearout tests if an appropriate model for the time dependent damage accumulation during the field ramp is used. There are implications for reliability predication and the burn-in screening of device populations containing such defects.     

Modeling and characterization of gate oxide reliability

A technique of predicting the lifetime of an oxide to different voltages, different oxide areas, and different temperatures is presented. Using the defect density model in which defects are modeled as effective oxide thinning, many reliability parameters such as yield, failure rate, and screen time/screen yield can be predicted. This modeling procedure is applicable to both wafer-level and long-term reliability tests. Process improvements including defect gettering and alternative dielectrics such as chemical-vapor-deposited oxides are evaluated in the format of defect density as a function of effective oxide thinning     

A new gate current extraction technique for measurement of on-statebreakdown voltage in HEMTs

We present a new simple three-terminal technique for measuring the on-state breakdown voltage in HEMTs. The gate current extraction technique involves grounding the source, and extracting a constant current from the gate. The drain current is then ramped from the off-state to the on-state, and the locus of drain voltage is measured. This locus of drain current versus drain voltage provides a simple, unambiguous definition of the on-state breakdown voltage which is consistent with the accepted definition of off-state breakdown. The technique is relatively safe and repeatable so that temperature dependent measurements of on-state breakdown can be carried out. This helps illuminate the physics of both off-state and on-state breakdown     

Monitoring plasma-process induced damage in thin oxide

Plasma etching and resist ashing processes cause current to flow through the thin oxide and the resultant plasma-induced damage can be simulated and modeled as damage produced by constant current electrical stress. The oxide charging current produced by plasma processing increases with the `antenna' size of the device structure. Oxide charge measurement such as CV or threshold voltage is a more sensitive technique for characterizing plasma-processing induced damage than oxide breakdown. The oxide charging current is collected only through the aluminum surfaces not covered by the photoresist during plasma processes. Although forming gas anneal can passivate the traps generated during plasma etching, subsequent Fowler-Nordheim stressing causes more traps to be generated in these devices than in devices that have not been through plasma etching. Using the measured charging current, the breakdown voltage distribution of oxides after plasma processes can be predicted accurately. Oxide shorts density of a single large test capacitor is found to be higher than that in a multiple of separated small capacitors having the same total oxide area. This would lead to overly pessimistic oxide defect data unless care is taken     

Effect of stress voltages on voltage acceleration and lifetime projections for ultra-thin gate oxides

This paper investigates the effect of NFET (N+ poly gate, N+ diffusion of FET) stress voltage conditions, for ultra-thin gate oxides, on the voltage acceleration, and lifetime projections to use conditions. This work employs the model relating the critical defect density (N^BD) to the charge-to-breakdown and the defect generation probability (P_g). The models for N^BD and P_g were adjusted for effects at voltages between 2 V and 3 V, and oxide thickness less than 2.7 nm. For N^BD, a model is proposed that is supported by published data and provides a gradual transition to a plateau for oxide thickness less than 2.7 nm. For P_g, a stronger dependency of Log(P_g) in the range of 2–3 V is employed to give a better fit to published data. This adjusted P_g is also used below 2 V to show trend of projection. In the direct tunneling range below 3 V, there is an increase of the voltage acceleration factor (AF) with decreasing voltage. Also, below 3 V, AF shows a decrease as the oxide thickness is reduced from 2.0 nm to 1.2 nm, and this trend becomes stronger as the gate voltage is reduced. Above a gate stress voltage of 3 V, in the range of 3–4 V, AF is almost constant, and there is a slight decrease of AF with decreasing oxide thickness in the range of 2.0–1.2 nm. A voltage power-law fit for the range above 3 V shows a decreasing power index with decreasing oxide thickness.     

Series resistance effects in thin oxide capacitor evaluation

The effects of undesired series resistance in thin oxide capacitors are studied. Thin dielectric reliability is usually evaluated by means of accelerated tests (ramped or constant voltage or current stress). It is shown that the breakdown electric field can be highly overestimated due to the series resistance associated with the test structure: the larger the resistance, the bigger the error. Moreover, breakdown detection criteria in automatic test routines become more critical. It is also demonstrated that a nonuniform stress is applied to the dielectric whenever the series resistance is position-dependent, as it usually is. Erroneous breakdown-related defect distributions could be inferred as a consequence of neglecting the series resistance effect. It is therefore suggested that workers pay much attention to the test structure layout definition in order to minimize these problems     

A comparison of RTO and furnace SiO2 time-zero-breakdowncharacteristics

The breakdown features under ramp voltage stresses of rapid thermal oxidation (RTO) and conventional dry oxides were compared and the results analyzed according to a model that relates defect seriousness to an effective thinning of the nominal film thickness. A method is presented that allows the extraction of valid conclusions about film quality, even on the basis of data collected on samples of different area. From the obtained Weibull plots at least two modes of extrinsic breakdown are evident, each one related to a different type of defect. None of these two kinds of defects is found to be completely randomly distributed. The superior quality of RTO oxides is confirmed insofar as they exhibit lower densities of these defects     

Accelerated testing of SiO2 reliability

This paper compares several popular accelerated test methods for projecting SiO₂ lifetime distribution or failure rate: constant-voltage and constant-current time-to-breakdown and charge-to-breakdown tests, ramp-voltage breakdown test, and ramp-current charge to-breakdown test. Charge trapping affects the electric field acceleration parameter for time-to-breakdown and the value of breakdown voltage. Practical considerations favor ramp breakdown testing for gate oxide defect characterization. The effective thinning model is used for defect characterization and the ramp-voltage breakdown test is shown to be superior to the ramp-current Q_BD test for extraction of the defect distribution. Measurement issues are also discussed     

Electrical testing for process evaluations

MOS LSI process evaluation techniques based on electrical measurements are presented. Important processing parameters, such as gate length, gate oxide thickness, junction depth and channel doping which determine major device characteristics, e.g. threshold voltage and gain factor, are evaluated by electrical measurements, and compared with those measured by optical or in-process monitoring methods. Good agreement between these results indicates the effectiveness of this electrical evaluation technique. According to the analysis, threshold voltage variations across the wafer are primarily due to variations in gate oxide thickness, while anomalous threshold voltage reduction in the short channel region is attributed to MOSFET punch-through.     

Back gate effects on threshold voltage sensitivity to SOI thicknessin fully-depleted SOI MOSFETs

The dependence of threshold voltage on silicon-on-insulator (SOI) thickness is studied on fully-depleted SOI MOSFETs, and, for this purpose, back-gate oxide thickness and back gate voltage are varied. When the back gate oxide is thinner than the critical thickness dependent on the back gate voltage, the threshold voltage has a minimum in cases where the SOI film thickness is decreased, because of capacitive coupling between the SOI layer and the back gate. This fact suggests that threshold voltage fluctuations due to SOI thickness variations are reduced by controlling the back gate voltage and thinning the back gate oxide     

Ramped current stress for fast and reliable wafer level reliability monitoring of thin gate oxide reliability

A ramped dielectric stress measurement, suitable for fast wafer level reliability (fWLR) monitoring, is assessed for thin gate oxide thicknesses down to 2.2 nm. Severe difficulties usually occur for the reliable detection of soft/hard breakdown in a short time interval and due to high direct tunneling currents. These are discussed and an exponentially ramped current stress is introduced tackling the problems. Early oxide fails were covered by a fast voltage ramp carried out before the current ramp. The advantages of the method are highlighted which has already been implemented for fWLR monitoring in high volume production on scribe line structures.