The Formation of Shallow Low-Resistance Source-Drain Regions for VLSI CMOS Technologies

As a result of MOS device scaling, very shallow source-drain structures are needed to minimize short-channel effects in 1-/spl mu/m transistors. This can be readily achieved with highly doped arsenic regions for NMOS devices but is more difficult using boron for PMOS devices. In addition, shallow junctions suffer from inherently high sheet resistances due to dopant solid solubility limitations. This paper proposes an improved CMOS source-drain technology to overcome both these problems. The technique employs amorphizing silicon implants prior to dopant implantation to eliminate ion channeling and platinum silicidation to substantially reduce sheet resistance. Counterdoping of the p/sup +/ regions by high-concentration arsenic implantation is used to enable both NMOS and PMOS devices to be manufactured with only one photolithographic masking operation. Using this technique, n/sup +/ and p/sup +/ junction depths are 0.22 /spl mu/ and of 8 /spl Omega/sq. sheet resistance. By creating oxide sidewalls on gate conductors, polysilicon can be silicided simultaneously with diffusions. Results of extensive materials analysis are discussed in detail. The technique has been incorporated into a VLSI CMOS process schedule at our laboratories.     

Rapid isothermal processing with electron beams of small-geometry CMOS devices

Small-geometry CMOS devices with shallow n⁺and p⁺source-drain regions formed by arsenic and boron difluoride ion implantation, respectively, have been studied. Activation of implants was produced by a single rapid isothermal anneal using the multiple-scan electron-beam approach. Transistor and circuit simulations were used to determine a requirement for the source-drain region of a sheet resistance of < 100 Ω/square with a junction depth of less than 0.2 µm in 1-µm channel length devices. These values cannot be obtained by conventional furnace annealing at 950°C, but can be achieved by a single heat treatment With an e-beam. E-beam-annealed devices have a reverse-bias junction leakage similar to furnace-annealed control samples, and show improvements in short-channel effects such as short-channel threshold voltage shifts and punchthrough, without introducing other deleterious effects.     

Disposable polysilicon LDD spacer technology

An advanced 0.5-μm CMOS disposable lightly doped drain (LDD) spacer technology has been developed. This 0.5-μm CMOS technology features surface-channel LDD NMOS and PMOS devices, n⁺/p⁺ poly gates, 125-A-thick gate oxide, and Ti-salicided source/drain/gate regions. Using only two masking steps, the NMOS and PMOS LDD spacers are defined separately to provide deep arsenic n⁺ regions for lower salicided junction leakage, while simultaneously providing shallow phosphorus n^- and boron p^- regions for improved device short-channel effects. Additionally, the process allows independent adjustment of the LDD and salicide spacers to optimize the LDD design while avoiding salicide bridging of source/drain to gate regions. The results indicate extrapolated DC hot-carrier lifetimes in excess of 10 years for a 0.3-μm electrical channel-length NMOS device operated at a power-supply voltage of 3.3 V     

Mo- and Ti-silicided low-resistance shallow junctions formed using the ion implantation through metal technique

Mo-and Ti-silicided junctions were formed using the ITM technique, which consists of ion implantation through metal (ITM) to induce metal-Si interface mixing and subsequent thermal annealing. Double ion implantation, using nondopant ions (Si or Ar) implantation for the metal-Si interface mixing and dopant ion (As or B) implantation for doping, has resulted in ultrashallow ( ≤ 0.1-µm) p⁺-n or n⁺-p junctions with ∼30-Ω sheet resistance for Mo-silicided junctions and ∼5.5-Ω sheet resistance for Ti-silicided junctions. The leakage current levels for the Mo-silicided n⁺-p junctions (0.1-µm junction depth) and the Mo-silicided p⁺-n junction (0.16-µm junction depth) are comparable to that for unsilicided n⁺-p junction with greater junction depth ( ∼0.25 µm).     

A novel dual p-/p+ poly gate CMOS VLSItechnology

A CMOS VLSI technology using p^- and p⁺ poly gates for NMOS and PMOS devices is presented. Due to the midgap work function of the p^- poly gate, the NMOS native threshold voltage is 0.7 V and, therefore, no additional threshold adjust implantation is required. The NMOS transistor is a surface-channel device with improved field-effect mobility and lower body effect due to the reduction in the channel doping concentration. In addition, the p ^- poly gate is shown to be compatible with p⁺ poly-gated surface-channel PMOS devices     

Fabrication of submicrometer MOSFET's using gas immersion laser doping (GILD)

The fabrication of MOSFET's with submicrometer gate lengths using Gas Immersion Laser Doping (GILD) to dope the source-drain and gate regions of n-channel devices is described. The GILD step relies on a melt/regrowth process, initiated by a pulsed excimer laser (XeCl, λ = 308 nm), to drive in a dopant species adsorbed on the clean silicon surface. High dopant concentrations (1 × 10¹⁹to 2 × 10²¹cm^-3) and shallow junctions (600-1000 Å) make this process ideally suited for source-drain formation in submicrometer structures. In this work the transistors are fabricated using an otherwise conventional NMOS process. The resultant devices have similar source-drain Rsheetvalues and lower poly Rsheetwhen compared to devices fabricated using a conventional implanted source-drain and diffused polysilicon gate. Short-channel devices (L_{poly} = 0.9µm) exhibit excellent I-V characteristics and little change in Vt.     

Scaled CMOS technology using SEG isolation and buried well process

An advanced bulk CMOS technology has been developed using the selective epitaxial growth (SEG) isolation technique and buried n-well process. CMOS devices are fabricated on a selective epitaxial layer, isolated by a thick SiO2insulator over the p⁺substrate. p-channel devices are designed on buried n-wells, formed by introducing a phosphorus ion implantation into the p⁺substrate before the epitaxial growth. The use of an SiO2sidewall and square side direction is effective for defect-free selective epitaxy. The epitaxial autodoping effect from the p⁺substrate and the buried layer is estimated to be within less than 1 µm. A 20-nm-thick gate oxide and 500-nm-thick phosphorus-doped polysilicon gate electrode are used for both channel devices. Submicrometer gate CMOS operation is confirmed using the SEG isolation technique. This isolation structure, combined with the buried well, shows large latchup immunity for scaled CMOS circuits.     

Formation of shallow p+-n junctions using boron-nitride solid diffusion source

Shallow p⁺-n junctions on the order of 0.1-µm deep have been fabricated using boron-nitride (BN) solid diffusion sources. The process combines the hydrogen-injection method and rapid thermal processing (RTP). Sheet resistivities, in ranges from 50 to 130 Ω/sq with junction depths from 0.1 to 0.19 µm, are possible in this technique. Diode characteristics of 0.11-µm junctions show low reverse leakage current, of the order of 10 nA/cm², indicating the possibility of this method to form PMOS source-drain contacts.     

Process limitation and device design tradeoffs of self-aligned TiSi2 junction formation in submicrometer CMOS devices

Submicrometer CMOS transistors require shallow junctions to minimize punchthrough and short-channel effects. Salicide technology is a very attractive metallization scheme to solve many CMOS scaling problems. However, to achieve a shallow junction with a salicide structure requires careful optimization for device design tradeoffs. Several proposed techniques to form shallow titanium silicide junctions are critically examined. Boron, BF₂, arsenic, and phosphorus dopants were used to study the process parameters for low-leakage TiSi ₂ p⁺/n and n⁺/p junctions in submicrometer CMOS applications. It is concluded that the dopant drive-out (DDO) from the TiSi₂ layer to form a shallow junction scheme is not an efficient method for titanium salicide structure; poor device performance and unacceptably leaky junctions are obtained by this scheme. The conventional post junction salicide (PJS) scheme can produce shallow n⁺/p and p⁺/n junctions with junction depths of 0.12 to 0.20 μm below the TiSi₂. Deep submicrometer CMOS devices with channel length of 0.40 to 0.45 μm can be fabricated with such junctions     

High-transconductance p-channel AlGaAs/GaAs HFETs with low-energyberyllium and fluorine co-implantation self-alignment

The fabrication and electrical characteristics of p-channel AlGaAs/GaAs heterostructure FETs with self-aligned p⁺ source-drain regions formed by low-energy co-implantation of Be and F are reported. The devices utilize a sidewall-assisted refractory gate process and are fabricated on an undoped AlGaAs/GaAs heterostructure grown by MOVPE. Compared with Be implantation alone, the co-implantation of F⁺ at 8 keV with 2×10¹⁴ ions/cm² results in a 3× increase in the post-anneal Be concentration near the surface for a Be⁺ implantation at 15 keV with 4×10¹⁴ ions/cm². Co-implantation permits a low source resistance to be obtained with shallow p⁺ source-drain regions. Although short-channel effects must be further reduced at small gate lengths, the electrical characteristics are otherwise excellent and show a 77-K transconductance as high as 207 mS/mm for a 0.5-μm gate length     

A highly latchup-immune 1-µm CMOS technology fabricated with 1-MeV ion implantation and self-aligned TiSi2

A 1-µm n-well CMOS technology with high latchup immunity is designed, realized, and characterized. Important features in this technology include thin epi substrate, retrograde n-well formed by 1-MeV ion implantation, As-P graded junctions, and self-aligned titanium disilicide. The 1-µm CMOS technology has been characterized by examining the deviceI-Vcurves, avalanche-breakdown voltages, subthreshold characteristics, short-channel effect, and sheet resistances. The devices fabricated by using the 1-MeV ion implantation and self-aligned titanium disilicide do not deviate from the conventional devices constructed with the same level of technology. With the As-P double-diffused LDD structure for the n-channel device, the avalanche-breakdown voltage is increased and hot-electron reliability is greatly improved. The titanium disilicide process effectively reduces the sheet resistances of the source-drain and the polysilicon gate to 3 Ω/□ compared with 150 Ω/□ of the unsilicided counterparts. The optimized 1-µm device channel n-well CMOS resulted in a propagation delay time of 150 ps with a power dissipation of 0.3 mW. With the thin epi wafers and the retrograde n-well structure, latchup immunity is found to be greatly improved. Moreover, with the titanium disilicide formation on the source-drain, the latchup holding voltage is found to be extremely high (13 V) with the substrate grounded from the backside of the wafer. If the backside substrate is not grounded, self-aligned disilicide over n⁺and p⁺regions are found necessary to ensure high latchup immunity even in the case of thin epi on heavily doped substrate. The degradation of emitter efficiency due to the TiSi2is believed to be the dominant factor in raising the holding voltage. Detailed experimental results and discussions are presented.     

Forming of Very Shallow Junction for S/D Extension in Deep Sub-Micron CMOS Devices

Very shallow junctions for S/D extension in deep sub-micron CMOS devices are required to suppress the short channel effect as devices scaling down, and the surface concentrations (N,) of these junctions need to be kept in a higher value to reduce the series resistance of the lightly doped drain structure. But it is very difficult for the conventional ion implantation to meet the requirement above. This article presents the results of forming very shallow and ultrashallow junctions used in 0.25 micron and 0.10 micron CMOS devices respectively with low energy implantation (LEI) and pre-amorphization implantation plus low energy implantation (PAI+LEI). The LEI was performed on the modified normal ion-imptantor (IM-200M). Using LEI only the minimum junction depth,is 61nm for NMOS and 57nm for PMOS (Nsub=1×1018cm-3) respectively after 1000℃ RTA and both Ns are above 3×1019cm-3 While using Ge PAI+LEI,under the optimized processing condition,the junction depth of 58nm for NMOS and 42nm for PMOS are obtained,with the leakage current density being 4nA/cm2.     

Dual-type CMOS gate electrodes by dopant diffusion from silicide

Dual work function gate electrodes have been implemented in a 1-μm CMOS process. Dopant atoms were implanted into tungsten silicide simultaneously with the source-drain implantations and subsequently diffused into the underlying polycrystalline silicon layer by rapid thermal annealing. Physical analyses showed that arsenic and boron could easily be incorporated in the polysilicon to concentrations greater than 10²⁰ cm^-3. Capacitor and transistor measurements confirmed that n⁺ and p⁺ silicon could be obtained, with a difference of about 1 V between the respective flat-band voltages. By comparison with conventional n-type gate MOSFETs, it was verified that significantly improved subthreshold characteristics were obtained with p-type PMOS gate electrodes     

Sub-quarter-micrometer CMOS on ultrathin (400 Å) SOI

MOS transistors with effective channel lengths down to 0.2 μm have been fabricated in fully depleted, ultrathin (400 Å) silicon-on-insulator (SOI) films. These devices do not exhibit punchthrough, even for the smallest channel lengths, and have performance characteristics comparable to deep-submicrometer bulk transistors. The NMOS devices have a p⁺-polysilicon gate, and the PMOS devices have an n⁺-polysilicon gate, giving threshold voltages close to 1 V with very light channel doping. Because the series resistance associated with the source and drain regions can be very high in such thin SOI films, a titanium salicide process was used using a 0.25 μm oxide spacer. With this process, the sheet resistance of the silicided SOI layer is approximately 5 Ω/□. However, the devices still exhibit significant series resistance, which is likely due to contact resistance between the silicide and silicon source/drain regions     

A self-aligned 1-µm-channel CMOS technology with retrograde n-well and thin epitaxy

A six-mask 1-µm CMOS process with many self-aligned features is described. It uses a thin p-type epitaxial layer on a p⁺substrate and a retrograde n-well. Self-aligned TiSi2is formed on n⁺and p⁺diffusions to reduce the sheet resistance and to make butted source contacts. It is shown that n⁺poly-gated p-channel devices can be properly designed with low threshold magnitudes and good turn-off characteristics. With a 5-V supply, the minimum gate delay of unloaded CMOS ring oscillators is 150 ps/stage. Furthermore, it is demonstrated that this CMOS technology is latchup free since the holding voltage for latchup is higher than 5 V.     

A comprehensive study of suppression of boron penetration byamorphous-Si gate in P+-gate PMOS devices

This paper presents a comprehensive study of the impact of the silicon gate structure on the suppression of boron penetration in p⁺-gate devices. The characteristics and reliability for different gate structures (poly-Si, α-Si, poly-Si/poly-Si, poly-Si/α-Si, α-Si/poly-Si, and α-Si/α-Si) in p ⁺ polygate PMOS devices are investigated in detail. The suppression of boron penetration by the nitrided gate oxide is also discussed. The comparison is based on flatband voltage shift as well as the value of charge to breakdown. Results show that the effect of boron diffusion through the thin gate oxide in p⁺ polygate PMOS devices can be significantly suppressed by employing the as-deposited amorphous silicon gate. Stacked structures can also be employed to suppress boron penetration at the expense of higher polygate resistance. The single layer as-deposited amorphous silicon is a suitable silicon gate material in the p⁺-gate PMOS device for future dual-gate CMOS process. In addition, by employing a long time annealing at 600°C prior to p⁺-gate ion implantation and activation, further improvements in suppression of boron penetration, polygate resistance, and gate oxide reliability can be achieved for the as-deposited amorphous-Si gate. Modifying the silicon gate structure instead of the gate dielectrics is an effective approach to suppress the boron penetration effect     

On the resistivity of TiSi2: The implication for low-temperature applications

The electrical resistivity of TiSi2formed on polysilicon implanted with phosphorus and arsenic and on n⁺and p⁺diffusions implanted with arsenic and boron was measured in the 4.2-300 K temperature range. It is found that in all cases, the resistivity is reduced by a factor of 3-4 when TiSi2is cooled from room to liquid-nitrogen temperature. Sheet resistance as low as 1 Ω/sq. at liquid-nitrogen temperature can be easily achieved for self-aligned thin TiSi2layers over polysilicon and diffusion regions, which is very attractive for low-temperature CMOS applications. The residual resistivity ratio, which is a measure of the electron mean free path, decreases with growing surface concentration of dopants, regardless of doping species. The analysis of thickness effects in terms of surface scattering and of grain boundary resistivity models, suggests that degradation of sheet resistance Rswith increased implantation dose is due only partly to the difficulty in forming thick enough TiSi2at high doses, and that dopant impurities segregated at the grain boundaries can account for the observed increase.     

Subquarter-micrometer gate-length p-channel and n-channel MOSFETswith extremely shallow source-drain junctions

The fabrication of p-channel and n-channel MOSFETs with sub-quarter-micrometer n⁺ polysilicon gates, have been fabricated using extremely shallow source-drain (S-D) junctions, is reported p⁺-n junctions as shallow as 80 nm have been fabricated using preamorphization low-energy BF₂ ion implantation and rapid thermal annealing, and 80-nm n⁺-p junctions have been fabricated using low-energy arsenic ion implantation and rapid thermal annealing. n-channel MOSFETs with 80-mm S-D junctions and 0.16-μm gate lengths have been fabricated, and a maximum transconductance of 400 mS/mm has been obtained. 51-stage n-channel enhancement-mode/enhancement-mode (E/E) ring oscillators and p-channel E/E ring oscillators with extremely shallow S-D junctions have also been obtained     

Dramatic increases in latchup holding voltage for sub-0.5 μmCMOS using shallow S/D junctions

Large increases in the latchup holding voltage are demonstrated with the use of shallow source-drain junctions in a sub-0.5 μm CMOS process. Holding voltages well above the supply voltage for 2 μm n ⁺/p⁺ spacings are demonstrated without the use of complex processes such as retrograde wells or buried layers. SIMS data is presented to verify the reduction in junction depths to 0.15 μm for the p⁺/n-well and 0.14 μm for the n⁺/p-well junction. The improvement in holding voltage is attributed to reductions in parasitic bipolar transistor gains, due to the increase in base width. Well behaved transistor characteristics are presented using the shallow junction technology     

Channel ion implantation for small-geometry high-performance CMOS-SOS circuits

This paper describes an experimental study of channel ion implantation for optimization of small-geometry (1-1.5 µm) n- and p-channel silicon-on-sapphire (SOS) MOSFET's for high-performance CMOS applications. The influence of a wide range of channel implantation conditions on device characteristics are reported, and optimum channel doping profiles identified. Adequate performance of NMOS devices is achieved by the use of double boron channel implants, but excellent PMOS devices are obtained by the use of very lightly doped near-intrinsic device islands.