A 2-V 2.3/4.6-GHz dual-band frequency synthesizer in 0.35-/spl mu/m digital CMOS process

This brief describes the design of a frequency synthesizer for 2.3/4.6-GHz wireless applications in a 0.35-/spl mu/m digital CMOS process. This synthesizer provides dual-band output signals by means of frequency doubling techniques. Output frequency of the proposed synthesizer ranges from 1.87-2.3 GHz, and 3.74-4.6GHz. This chip consumes a total power of 80 mW from a single 2-V supply, including 45 mW for dual-band output buffers. Core size is 2200 /spl mu/m/spl times/1600 /spl mu/m.     

A 3-V, 0.35-/spl mu/m CMOS Bluetooth receiver IC

A fully integrated CMOS low-IF Bluetooth receiver is presented. The receiver consists of a radio frequency (RF) front end, a phase-locked loop (PLL), an active complex filter, a Gaussian frequency shift keying (GFSK) demodulator, and a frequency offset cancellation circuit. The highlights of the receiver include a low-power active complex filter with a nonconventional tuning scheme and a high-performance mixed-mode GFSK demodulator. The chip was fabricated on a 6.25-mm/sup 2/ die using TSMC 0.35-/spl mu/m standard CMOS process. -82 dBm sensitivity at 1e-3 bit error rate, -10 dBm IIP3, and 15 dB noise figure were achieved in the measurements. The receiver active current is about 65 mA from a 3-V power supply.     

A 3.3-V, 10-b, 25-MSample/s two-step ADC in 0.35-μm CMOS

This paper describes the design of a two-step analog-to-digital converter (ADC). By using techniques such as improved switching and offset compensated amplifiers, the high-speed two-step architecture can be expanded toward high resolution. The ADC presented here achieves 9 ENOB with a spurious-free dynamic range of more than 72 dB, at a sample rate of 25 MSample/s. The ADC is realized in a 0.35-μm mainstream CMOS process without options such as double poly. It measures 0.66 mm ² and dissipates 195 mW from a 3.3-V power supply     

A 1.5-V multi-mode quad-band RF receiver for GSM/EDGE/CDMA2K in 90-nm digital CMOS process

A single chip quad-band multi-mode (GSM900/ DCS1800/PCS1900/CDMA2K) direct-conversion RF receiver with integrated baseband ADCs is presented. The fully integrated RF receiver is implemented in a 90-nm single poly, six level metal, standard digital CMOS process with no additional analog and RF components. The highly digital multi-mode receiver uses minimum analog filtering and AGC stages, digitizing useful signal, dynamic DC offsets and blockers at the mixer output. The direct-conversion GSM front-end utilizes resistive loaded LNAs with only two coupled inductors per LNA. The GSM front-end achieves a 31.5 dB gain and a 2.1 dB integrated noise figure with a 5 dB noise figure under blocking conditions. The CDMA2K front-end utilizes a self-biased common-gate input amplifier followed by passive mixers, achieving wideband input matching from 900 MHz up to 2.1 GHz with an IIP3 of +8 dBm. The GSM receiver consumes 38 mA from a power supply of 1.5 V and CDMA2K receiver consumes 16 mA in the low band and 21 mA in the high band. The multi-mode receiver, including LO buffers and frequency dividers, ADCs, and reference buffers, occupies 2.5 mm/sup 2/.     

A 2D CMOS microfluxgate sensor system for digital detection of weakmagnetic fields

This paper presents a CMOS two-dimensional (2-D) vector magnetic sensor system integrating two planar microfluxgate sensors and the complete electronics for sensor excitation and signal readout. The system is based on an industrial 0.8-μm double-poly, double-metal CMOS technology with ferromagnetic NiFeMo cores added in a simple postprocessing sequence. The fluxgate sensors are embedded in a ΣΔ analog-to-digital converter for a stable and precise digital detection of weak magnetic fields. A cascaded ΣΔ modulator topology is utilized to obtain second-order noise shaping and to suppress pattern noise. Within the range of ±50 μT, the system nonlinearity is less than 1.5 μT. The angular resolution as a 2D vector sensor is less than 4° for a measured magnetic induction of 50 μT. This makes the 2-D microfluxgate magnetometer suitable for use as fully integrated electronic compass     

A 2.7-V CMOS single-chip baseband processor for CT2/CT2+ cordlesstelephones

A low-voltage, low-power CMOS single-chip baseband processor for CT2 and CT2+ cordless telephones is presented. The chip integrates a complete voiceband codec, a tone generator, a G721 adaptive differential pulse code modulation coder/decoder, a burst-mode logic controller for CT2/CT2+ framings, and an I/Q baseband signal generator. The only external components are made of two quartz crystals. The chip is interfaced with standard microcontrollers through a parallel interface. With a 2.7 V minimum supply, it consumes normal and standby powers of 35 mW and 25 μW, respectively. Maximum supply is 5.5 V, and temperature range is from -40 to 70°C. Chip area (including scribe line) is 55.5 mm² in a 0.8 μm N-well double-metal single-poly CMOS process with implanted capacitors     

A 2-V, 2-GHz low-power direct digital frequency synthesizerchip-set for wireless communication

A 2 GHz direct digital frequency synthesizer (DDFS) chip-set is presented which operates at a very low supply voltage of 2 V. The chip-set consists of a CMOS DDFS LSI which synthesizes a sine wave at 55 Msps with an internal 10 b digital-to-analog converter (DAC) and Si bipolar image-reject up-converters. To achieve both high purity and low power dissipation, we developed a distortion-free up-conversion architecture and an efficient ROM output bit-width reduction technique. Operation of 2 V for the entire chip-set becomes possible because of the use of both multithreshold-voltage CMOS in the D/A converters and current-folded double-balanced mixers in the microwave up-converters. The synthesizer achieves a wide spurious-free dynamic range of 50 dB and a low power dissipation of less than 160 mW at 2 GHz     

A 1-V, 82-dB, 2.5-MS/s,single loop,single bit delta-sigma modulator in 0.13-μm CMOS technology

It is challenging to design high speed Delta-Sigma modulator using sub-micron process with low supply voltage. Compared with multi-stage or multi-bit design, the single loop, single bit Delta-Sigma modulator has relaxed requirement for the building blocks under low-voltage operation, which make it possible to get high conversion rate by increasing sampling frequency. In this study, a low voltage, high speed 4th-order Delta-Sigma modulator using input feed-forward is presented. Implemented with 0.13-μm CMOS technology and 1.0-V supply voltage, the discrete-time Delta-Sigma modulator achieves 2.5-MS/s conversion rate and 82-dB dynamic range, with the sampling frequency of 160-MHz and OSR of 64.     

Full passive UHF RFID Tag with an ultra-low power,small area,high resolution temperature sensor suitable for environment monitoring

An UHF RFID Tag with an ultra-low power, small area, high resolution temperature sensor which adopted double voltage-controlled oscillators (VCO) has been designed and implemented using the SMIC CMOS 0.18 μm EEPROM 2P4M process. The core area of the tag (excluding the test bounding pad) is only 756×967 μm². The power-optimized tag allows a communication range of more than 6 m from a 1 W effective radiated output power reader.     

A 1.2-V RF front-end with on-chip VCO for PCS 1900 direct conversion receiver in 0.13-/spl mu/m CMOS

In this paper, a 1.2-V RF front-end realized for the personal communications services (PCS) direct conversion receiver is presented. The RF front-end comprises a low-noise amplifier (LNA), quadrature mixers, and active RC low-pass filters with gain control. Quadrature local oscillator (LO) signals are generated on chip by a double-frequency voltage-controlled oscillator (VCO) and frequency divider. A current-mode interface between the downconversion mixer output and analog baseband input together with a dynamic matching technique simultaneously improves the mixer linearity, allows the reduction of flicker noise due to the mixer switches, and minimizes the noise contribution of the analog baseband. The dynamic matching technique is employed to suppress the flicker noise of the common-mode feedback (CMFB) circuit utilized at the mixer output, which otherwise would dominate the low-frequency noise of the mixer. Various low-voltage circuit techniques are employed to enhance both the mixer second- and third-order linearity, and to lower the flicker noise. The RF front-end is fabricated in a 0.13-/spl mu/m CMOS process utilizing only standard process options. The RF front-end achieves a voltage gain of 50 dB, noise figure of 3.9 dB when integrated from 100 Hz to 135 kHz, IIP3 of -9 dBm, and at least IIP2 of +30dBm without calibration. The 4-GHz VCO meets the PCS 1900 phase noise specifications and has a phase noise of -132dBc/Hz at 3-MHz offset.     

A 2.5-V 57-MHz 15-tap SC bandpass interpolating filter with 320-MS/s output for DDFS system in 0.35-/spl mu/ hboxm CMOS

A switched-capacitor (SC) bandpass interpolating filter is proposed with the capability of achieving, simultaneously, channel selection and frequency up-translation, together with sampling rate increase, in a multirate configuration at high frequency. This filter has been designed for efficient use in a direct-digital frequency synthesis (DDFS) system with considerable rewards in terms of speed reduction of the digital core plus the digital-to-analog converter (DAC), as well as in the relaxation of the continuous-time (CT) smoothing filter order. It exhibits a 15-tap finite impulse response (FIR), with a bandpass frequency response centered at 57 MHz and a stop-band rejection higher than 45 dB. At the same time, it translates 22-24 MHz input signals at 80 MS/s, to the frequency range of 56-58 MHz in the output at 320 MS/s, allowing also a perfect operation at 400 MS/s, in 0.35-/spl mu/m CMOS technology. To implement a specific multi-notch FIR function, the filter architecture will comprise an effective low-speed polyphase-based interpolation structure with autozeroing capability, high-speed SC circuitry with fast opamps, and also ultra-low timing-skew multiple phase generation in order to achieve high-performance operation at high frequency. The prototype ICs present a signal-to-noise-and-distortion ratio (SNDR) of 61 dB, with a dynamic range of 69 dB, for 1% THD, and 61 dB, for 1% IM3. It consumes 2 mm/sup 2/ of active silicon area, 120 mW (analog) and 16 mW (digital) power, with a single 2.5-V supply, which corresponds to 8.6 mW of analog power per zero.     

A multiple sampling, single A/D conversion technique for I/Qdemodulation in CMOS

We have developed a CMOS A/D converter for I/Q demodulation with an analog mirror signal suppression filter in the sampling unit. The circuit directly converts a modulated 30 MHz IF signal to digitized I and Q values in the base band with an accuracy of more than 10 b. The output data rate is 2 MHz and the power consumption is 270 mW. By placing the I/Q split mirror suppression filter on the analog side, we can get a highly integrated system solution for a coherent receiver. The circuit uses multiple sampling, that gives the input values to the filter. The sizes of the sampling capacitors determine the coefficients for the filter multiplications. The sampled charges are then added in order to get the filter additions. This total charge is then converted to digital form in a single conversion. By requiring the filter to block DC, the filter subtraction becomes a part of the active offset reduction using correlated double sampling. Careful layout and very simple circuit solutions make the design possible     

A 55-V, 0.2-mΩ-cm2 vertical trench power MOSFET

Experimental results that demonstrate trench power MOSFETs with a specific on-state resistance of 0.2 mΩ-cm² and capable of sustaining 55 V across drain-source terminals in the off state are discussed. This performance was achieved by using an improved silicon trench processing technology. The forward conductivity reported is the highest ever obtained for a silicon power device     

A CMOS low power, process/temperature variation tolerant RSSI with an integrated AGC loop

A low voltage low power CMOS limiter and received signal strength indicator(RSSI) with an integrated automatic gain control(AGC) loop for a short-distance receiver are implemented in SMIC 0.13μm CMOS technology.The RSSI has a dynamic range of more than 60 dB and the RSSI linearity error is within i0.5 dB for an input power from -65 to -8 dBm.The RSSI output voltage is from 0.15 to 1 V and the slope of the curve is 14.17 mV/dB while consuming 1.5 mA(I and Q paths) from a 1.2 V supply.Auto LNA gain mode selection with a combined RSSI function is also presented.Furthermore,with the compensation circuit,the proposed RSSI shows good temperature-independent and good robustness against process variation characteristics.     

A 3.3-V power adaptive 1244/622/155 Mbit/s transceiver for ATM,SONET/SDH

This paper presents the implementation of a multirate 155-, 622-, or 1244-Mbit/s transceiver for ATM and SDH/SONET in a 0.5-μm BiCMOS. The internal high-speed clock generation is based on PLL's with 1.24-GHz VCO's. The solutions presented here allow us to get rid of the external trimming of the free-running frequency of VCO. The automatic adjustment of the clock and data recovery PLL VCO free running is performed, and thus, increases the robustness of the RX function without expenses in manual trimming. The architecture of this transceiver is thought to enable the full-frequency Wafer test of the whole core by specific loop-back modes. As the same core is used for 155-Mbit/s, 622-Mbit/s, and 1.2-Gbit/s power adaptation techniques are implemented which lead to a 660-mW consumption for 155-Mbit/s operation and 1.1 W for 1.24 Gbits/s. A specific digitally programmable power adaptive ECL cell library concept is presented. Noise precautions are also described, as well as an analog HDL top-down methodology developed by SGS-Thomson Central R&D to short-down the development time and increase reusability     

A 12 b 8 kS/s 16 μW 0.35 μm CMOS algorithmic ADC for sensor interface in ubiquitous environments

This work proposes a 12 b 8 kS/s ultra-low-power CMOS algorithmic analog-to-digital converter (ADC) for sensor interface applications such as accelerometers and gyro sensors requiring high-resolution, low-power, and small size simultaneously. The proposed ADC employs switched-bias power reduction and bias sharing circuits to minimize chip area and power dissipation. A signal-insensitive all directionally symmetric layout technique based on a double-poly CMOS process reduces capacitor mismatch in the multiplying D/A converter for 12 b-level high accuracy without additional conventional calibration schemes. Two independently generated currents with the same negative temperature coefficient are subtracted from each other to implement temperature- and supply-insensitive current and voltage references on-chip. The prototype ADC in a 0.35 μm 2P4M CMOS technology demonstrates a measured differential non-linearity and integral non-linearity within 0.15 and 0.56 LSB at 12 b and shows a maximum signal-to-noise-and-distortion ratio and spurious-free dynamic range of 68 and 77 dB at 8 kS/s, respectively. The ADC with an active die area of 0.70 mm² consumes 16 μW at 8 kS/s and 2.5 V.     

一种应用于WIA-PA收发机的高精度抗温度工艺偏差的CMOS 信号功率指示器

本文针对工业无线传感网WIA-PA标准设计出一款应用于WIA-PA收发机中的高精度抗温度工艺偏差的CMOS 接收信号功率指示器。本文提出信号功率指示器的采用TSMC 0.18 um 1P6MRF CMOS工艺流片,有效面积为0.24mm2。经测试,本文提出的信号功率指示器在输入信号从-70dBm到0dBm(50欧电阻匹配),线性误差在±0.5 dB以内,动态范围为70dB,检测灵敏度为12.1mV/dB,相应的输出电压从0.81V变化到1.657V。在1.8V电源供电情况下,整体功耗不超过2mA。进一步,本文提出的信号功率指示器中集成的修调和补偿电路,使得最大线性误差在-40到85度内不超过±1.5 dB,工艺角引起的线性误差不超过±0.25 dB。该功率检测器体现出良好的抗温度和工艺偏差的性能。     

A 1.8-V 128-Mb mobile DRAM with double boosting pump, hybrid current sense amplifier, and dual-referenced adjustment scheme for temperature sensor

To verify three important circuit schemes suitable for DRAMs in mobile applications, a 1.8-V 128-Mb SDRAM was implemented with a 0.15-/spl mu/m technology. To achieve an ideal 33% efficiency, the double boosting pump uses two capacitor's series connection at pumping phase, while they are precharged in parallel. The hybrid folded current sense amplifier together with a novel replica inverter connection improved power and speed performances. Also, a dual-referenced adjustment scheme for a temperature sensor was proposed to allow a very high accuracy in tuning. Without loss in productivity, the implemented dual-referenced searching technique achieved tuning error of less than /spl plusmn/2.5/spl deg/C.     

Heterogeneous integration technology for the thermal management of Ga2O3 power devices

<正>The more severe phonon-phonon scattering in gallium oxide(Ga₂O₃) crystals leads to lower thermal conductivity compared to most other semiconductor materials. To address this issue and enhance the heat dissipation in Ga₂O₃ devices, one practical solution is to integrate Ga₂O₃ with a highly thermally conductive substrate, such as SiC and Si. Currently,there are three methods employed for the heterogeneous integration of Ga<...